1*a47a12beSStefan Roese /* 2*a47a12beSStefan Roese * (C) Copyright 2002 3*a47a12beSStefan Roese * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4*a47a12beSStefan Roese * 5*a47a12beSStefan Roese * See file CREDITS for list of people who contributed to this 6*a47a12beSStefan Roese * project. 7*a47a12beSStefan Roese * 8*a47a12beSStefan Roese * This program is free software; you can redistribute it and/or 9*a47a12beSStefan Roese * modify it under the terms of the GNU General Public License as 10*a47a12beSStefan Roese * published by the Free Software Foundation; either version 2 of 11*a47a12beSStefan Roese * the License, or (at your option) any later version. 12*a47a12beSStefan Roese * 13*a47a12beSStefan Roese * This program is distributed in the hope that it will be useful, 14*a47a12beSStefan Roese * but WITHOUT ANY WARRANTY; without even the implied warranty of 15*a47a12beSStefan Roese * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16*a47a12beSStefan Roese * GNU General Public License for more details. 17*a47a12beSStefan Roese * 18*a47a12beSStefan Roese * You should have received a copy of the GNU General Public License 19*a47a12beSStefan Roese * along with this program; if not, write to the Free Software 20*a47a12beSStefan Roese * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21*a47a12beSStefan Roese * MA 02111-1307 USA 22*a47a12beSStefan Roese */ 23*a47a12beSStefan Roese 24*a47a12beSStefan Roese #include <common.h> 25*a47a12beSStefan Roese 26*a47a12beSStefan Roese /* 27*a47a12beSStefan Roese * CPU test 28*a47a12beSStefan Roese * Store instructions: stb(x)(u), sth(x)(u), stw(x)(u) 29*a47a12beSStefan Roese * 30*a47a12beSStefan Roese * All operations are performed on a 16-byte array. The array 31*a47a12beSStefan Roese * is 4-byte aligned. The base register points to offset 8. 32*a47a12beSStefan Roese * The immediate offset (index register) ranges in [-8 ... +7]. 33*a47a12beSStefan Roese * The test cases are composed so that they do not 34*a47a12beSStefan Roese * cause alignment exceptions. 35*a47a12beSStefan Roese * The test contains a pre-built table describing all test cases. 36*a47a12beSStefan Roese * The table entry contains: 37*a47a12beSStefan Roese * the instruction opcode, the value of the index register and 38*a47a12beSStefan Roese * the value of the source register. After executing the 39*a47a12beSStefan Roese * instruction, the test verifies the contents of the array 40*a47a12beSStefan Roese * and the value of the base register (it must change for "store 41*a47a12beSStefan Roese * with update" instructions). 42*a47a12beSStefan Roese */ 43*a47a12beSStefan Roese 44*a47a12beSStefan Roese #include <post.h> 45*a47a12beSStefan Roese #include "cpu_asm.h" 46*a47a12beSStefan Roese 47*a47a12beSStefan Roese #if CONFIG_POST & CONFIG_SYS_POST_CPU 48*a47a12beSStefan Roese 49*a47a12beSStefan Roese extern void cpu_post_exec_12w (ulong *code, ulong *op1, ulong op2, ulong op3); 50*a47a12beSStefan Roese extern void cpu_post_exec_11w (ulong *code, ulong *op1, ulong op2); 51*a47a12beSStefan Roese 52*a47a12beSStefan Roese static struct cpu_post_store_s 53*a47a12beSStefan Roese { 54*a47a12beSStefan Roese ulong cmd; 55*a47a12beSStefan Roese uint width; 56*a47a12beSStefan Roese int update; 57*a47a12beSStefan Roese int index; 58*a47a12beSStefan Roese ulong offset; 59*a47a12beSStefan Roese ulong value; 60*a47a12beSStefan Roese } cpu_post_store_table[] = 61*a47a12beSStefan Roese { 62*a47a12beSStefan Roese { 63*a47a12beSStefan Roese OP_STW, 64*a47a12beSStefan Roese 4, 65*a47a12beSStefan Roese 0, 66*a47a12beSStefan Roese 0, 67*a47a12beSStefan Roese -4, 68*a47a12beSStefan Roese 0xff00ff00 69*a47a12beSStefan Roese }, 70*a47a12beSStefan Roese { 71*a47a12beSStefan Roese OP_STH, 72*a47a12beSStefan Roese 2, 73*a47a12beSStefan Roese 0, 74*a47a12beSStefan Roese 0, 75*a47a12beSStefan Roese -2, 76*a47a12beSStefan Roese 0xff00 77*a47a12beSStefan Roese }, 78*a47a12beSStefan Roese { 79*a47a12beSStefan Roese OP_STB, 80*a47a12beSStefan Roese 1, 81*a47a12beSStefan Roese 0, 82*a47a12beSStefan Roese 0, 83*a47a12beSStefan Roese -1, 84*a47a12beSStefan Roese 0xff 85*a47a12beSStefan Roese }, 86*a47a12beSStefan Roese { 87*a47a12beSStefan Roese OP_STWU, 88*a47a12beSStefan Roese 4, 89*a47a12beSStefan Roese 1, 90*a47a12beSStefan Roese 0, 91*a47a12beSStefan Roese -4, 92*a47a12beSStefan Roese 0xff00ff00 93*a47a12beSStefan Roese }, 94*a47a12beSStefan Roese { 95*a47a12beSStefan Roese OP_STHU, 96*a47a12beSStefan Roese 2, 97*a47a12beSStefan Roese 1, 98*a47a12beSStefan Roese 0, 99*a47a12beSStefan Roese -2, 100*a47a12beSStefan Roese 0xff00 101*a47a12beSStefan Roese }, 102*a47a12beSStefan Roese { 103*a47a12beSStefan Roese OP_STBU, 104*a47a12beSStefan Roese 1, 105*a47a12beSStefan Roese 1, 106*a47a12beSStefan Roese 0, 107*a47a12beSStefan Roese -1, 108*a47a12beSStefan Roese 0xff 109*a47a12beSStefan Roese }, 110*a47a12beSStefan Roese { 111*a47a12beSStefan Roese OP_STWX, 112*a47a12beSStefan Roese 4, 113*a47a12beSStefan Roese 0, 114*a47a12beSStefan Roese 1, 115*a47a12beSStefan Roese -4, 116*a47a12beSStefan Roese 0xff00ff00 117*a47a12beSStefan Roese }, 118*a47a12beSStefan Roese { 119*a47a12beSStefan Roese OP_STHX, 120*a47a12beSStefan Roese 2, 121*a47a12beSStefan Roese 0, 122*a47a12beSStefan Roese 1, 123*a47a12beSStefan Roese -2, 124*a47a12beSStefan Roese 0xff00 125*a47a12beSStefan Roese }, 126*a47a12beSStefan Roese { 127*a47a12beSStefan Roese OP_STBX, 128*a47a12beSStefan Roese 1, 129*a47a12beSStefan Roese 0, 130*a47a12beSStefan Roese 1, 131*a47a12beSStefan Roese -1, 132*a47a12beSStefan Roese 0xff 133*a47a12beSStefan Roese }, 134*a47a12beSStefan Roese { 135*a47a12beSStefan Roese OP_STWUX, 136*a47a12beSStefan Roese 4, 137*a47a12beSStefan Roese 1, 138*a47a12beSStefan Roese 1, 139*a47a12beSStefan Roese -4, 140*a47a12beSStefan Roese 0xff00ff00 141*a47a12beSStefan Roese }, 142*a47a12beSStefan Roese { 143*a47a12beSStefan Roese OP_STHUX, 144*a47a12beSStefan Roese 2, 145*a47a12beSStefan Roese 1, 146*a47a12beSStefan Roese 1, 147*a47a12beSStefan Roese -2, 148*a47a12beSStefan Roese 0xff00 149*a47a12beSStefan Roese }, 150*a47a12beSStefan Roese { 151*a47a12beSStefan Roese OP_STBUX, 152*a47a12beSStefan Roese 1, 153*a47a12beSStefan Roese 1, 154*a47a12beSStefan Roese 1, 155*a47a12beSStefan Roese -1, 156*a47a12beSStefan Roese 0xff 157*a47a12beSStefan Roese }, 158*a47a12beSStefan Roese }; 159*a47a12beSStefan Roese static unsigned int cpu_post_store_size = 160*a47a12beSStefan Roese sizeof (cpu_post_store_table) / sizeof (struct cpu_post_store_s); 161*a47a12beSStefan Roese 162*a47a12beSStefan Roese int cpu_post_test_store (void) 163*a47a12beSStefan Roese { 164*a47a12beSStefan Roese int ret = 0; 165*a47a12beSStefan Roese unsigned int i; 166*a47a12beSStefan Roese int flag = disable_interrupts(); 167*a47a12beSStefan Roese 168*a47a12beSStefan Roese for (i = 0; i < cpu_post_store_size && ret == 0; i++) 169*a47a12beSStefan Roese { 170*a47a12beSStefan Roese struct cpu_post_store_s *test = cpu_post_store_table + i; 171*a47a12beSStefan Roese uchar data[16] = 172*a47a12beSStefan Roese { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 }; 173*a47a12beSStefan Roese ulong base0 = (ulong) (data + 8); 174*a47a12beSStefan Roese ulong base = base0; 175*a47a12beSStefan Roese 176*a47a12beSStefan Roese if (test->index) 177*a47a12beSStefan Roese { 178*a47a12beSStefan Roese ulong code[] = 179*a47a12beSStefan Roese { 180*a47a12beSStefan Roese ASM_12(test->cmd, 5, 3, 4), 181*a47a12beSStefan Roese ASM_BLR, 182*a47a12beSStefan Roese }; 183*a47a12beSStefan Roese 184*a47a12beSStefan Roese cpu_post_exec_12w (code, &base, test->offset, test->value); 185*a47a12beSStefan Roese } 186*a47a12beSStefan Roese else 187*a47a12beSStefan Roese { 188*a47a12beSStefan Roese ulong code[] = 189*a47a12beSStefan Roese { 190*a47a12beSStefan Roese ASM_11I(test->cmd, 4, 3, test->offset), 191*a47a12beSStefan Roese ASM_BLR, 192*a47a12beSStefan Roese }; 193*a47a12beSStefan Roese 194*a47a12beSStefan Roese cpu_post_exec_11w (code, &base, test->value); 195*a47a12beSStefan Roese } 196*a47a12beSStefan Roese 197*a47a12beSStefan Roese if (ret == 0) 198*a47a12beSStefan Roese { 199*a47a12beSStefan Roese if (test->update) 200*a47a12beSStefan Roese ret = base == base0 + test->offset ? 0 : -1; 201*a47a12beSStefan Roese else 202*a47a12beSStefan Roese ret = base == base0 ? 0 : -1; 203*a47a12beSStefan Roese } 204*a47a12beSStefan Roese 205*a47a12beSStefan Roese if (ret == 0) 206*a47a12beSStefan Roese { 207*a47a12beSStefan Roese switch (test->width) 208*a47a12beSStefan Roese { 209*a47a12beSStefan Roese case 1: 210*a47a12beSStefan Roese ret = *(uchar *)(base0 + test->offset) == test->value ? 211*a47a12beSStefan Roese 0 : -1; 212*a47a12beSStefan Roese break; 213*a47a12beSStefan Roese case 2: 214*a47a12beSStefan Roese ret = *(ushort *)(base0 + test->offset) == test->value ? 215*a47a12beSStefan Roese 0 : -1; 216*a47a12beSStefan Roese break; 217*a47a12beSStefan Roese case 4: 218*a47a12beSStefan Roese ret = *(ulong *)(base0 + test->offset) == test->value ? 219*a47a12beSStefan Roese 0 : -1; 220*a47a12beSStefan Roese break; 221*a47a12beSStefan Roese } 222*a47a12beSStefan Roese } 223*a47a12beSStefan Roese 224*a47a12beSStefan Roese if (ret != 0) 225*a47a12beSStefan Roese { 226*a47a12beSStefan Roese post_log ("Error at store test %d !\n", i); 227*a47a12beSStefan Roese } 228*a47a12beSStefan Roese } 229*a47a12beSStefan Roese 230*a47a12beSStefan Roese if (flag) 231*a47a12beSStefan Roese enable_interrupts(); 232*a47a12beSStefan Roese 233*a47a12beSStefan Roese return ret; 234*a47a12beSStefan Roese } 235*a47a12beSStefan Roese 236*a47a12beSStefan Roese #endif 237