1a47a12beSStefan Roese /* 2a47a12beSStefan Roese * (C) Copyright 2002 3a47a12beSStefan Roese * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4a47a12beSStefan Roese * 5*1a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 6a47a12beSStefan Roese */ 7a47a12beSStefan Roese 8a47a12beSStefan Roese #include <common.h> 9a47a12beSStefan Roese 10a47a12beSStefan Roese /* 11a47a12beSStefan Roese * CPU test 12a47a12beSStefan Roese * Load instructions: lbz(x)(u), lhz(x)(u), lha(x)(u), lwz(x)(u) 13a47a12beSStefan Roese * 14a47a12beSStefan Roese * All operations are performed on a 16-byte array. The array 15a47a12beSStefan Roese * is 4-byte aligned. The base register points to offset 8. 16a47a12beSStefan Roese * The immediate offset (index register) ranges in [-8 ... +7]. 17a47a12beSStefan Roese * The test cases are composed so that they do not 18a47a12beSStefan Roese * cause alignment exceptions. 19a47a12beSStefan Roese * The test contains a pre-built table describing all test cases. 20a47a12beSStefan Roese * The table entry contains: 21a47a12beSStefan Roese * the instruction opcode, the array contents, the value of the index 22a47a12beSStefan Roese * register and the expected value of the destination register. 23a47a12beSStefan Roese * After executing the instruction, the test verifies the 24a47a12beSStefan Roese * value of the destination register and the value of the base 25a47a12beSStefan Roese * register (it must change for "load with update" instructions). 26a47a12beSStefan Roese */ 27a47a12beSStefan Roese 28a47a12beSStefan Roese #include <post.h> 29a47a12beSStefan Roese #include "cpu_asm.h" 30a47a12beSStefan Roese 31a47a12beSStefan Roese #if CONFIG_POST & CONFIG_SYS_POST_CPU 32a47a12beSStefan Roese 33a47a12beSStefan Roese extern void cpu_post_exec_22w (ulong *code, ulong *op1, ulong op2, ulong *op3); 34a47a12beSStefan Roese extern void cpu_post_exec_21w (ulong *code, ulong *op1, ulong *op2); 35a47a12beSStefan Roese 36a47a12beSStefan Roese static struct cpu_post_load_s 37a47a12beSStefan Roese { 38a47a12beSStefan Roese ulong cmd; 39a47a12beSStefan Roese uint width; 40a47a12beSStefan Roese int update; 41a47a12beSStefan Roese int index; 42a47a12beSStefan Roese ulong offset; 43a47a12beSStefan Roese } cpu_post_load_table[] = 44a47a12beSStefan Roese { 45a47a12beSStefan Roese { 46a47a12beSStefan Roese OP_LWZ, 47a47a12beSStefan Roese 4, 48a47a12beSStefan Roese 0, 49a47a12beSStefan Roese 0, 50a47a12beSStefan Roese 4 51a47a12beSStefan Roese }, 52a47a12beSStefan Roese { 53a47a12beSStefan Roese OP_LHA, 54a47a12beSStefan Roese 3, 55a47a12beSStefan Roese 0, 56a47a12beSStefan Roese 0, 57a47a12beSStefan Roese 2 58a47a12beSStefan Roese }, 59a47a12beSStefan Roese { 60a47a12beSStefan Roese OP_LHZ, 61a47a12beSStefan Roese 2, 62a47a12beSStefan Roese 0, 63a47a12beSStefan Roese 0, 64a47a12beSStefan Roese 2 65a47a12beSStefan Roese }, 66a47a12beSStefan Roese { 67a47a12beSStefan Roese OP_LBZ, 68a47a12beSStefan Roese 1, 69a47a12beSStefan Roese 0, 70a47a12beSStefan Roese 0, 71a47a12beSStefan Roese 1 72a47a12beSStefan Roese }, 73a47a12beSStefan Roese { 74a47a12beSStefan Roese OP_LWZU, 75a47a12beSStefan Roese 4, 76a47a12beSStefan Roese 1, 77a47a12beSStefan Roese 0, 78a47a12beSStefan Roese 4 79a47a12beSStefan Roese }, 80a47a12beSStefan Roese { 81a47a12beSStefan Roese OP_LHAU, 82a47a12beSStefan Roese 3, 83a47a12beSStefan Roese 1, 84a47a12beSStefan Roese 0, 85a47a12beSStefan Roese 2 86a47a12beSStefan Roese }, 87a47a12beSStefan Roese { 88a47a12beSStefan Roese OP_LHZU, 89a47a12beSStefan Roese 2, 90a47a12beSStefan Roese 1, 91a47a12beSStefan Roese 0, 92a47a12beSStefan Roese 2 93a47a12beSStefan Roese }, 94a47a12beSStefan Roese { 95a47a12beSStefan Roese OP_LBZU, 96a47a12beSStefan Roese 1, 97a47a12beSStefan Roese 1, 98a47a12beSStefan Roese 0, 99a47a12beSStefan Roese 1 100a47a12beSStefan Roese }, 101a47a12beSStefan Roese { 102a47a12beSStefan Roese OP_LWZX, 103a47a12beSStefan Roese 4, 104a47a12beSStefan Roese 0, 105a47a12beSStefan Roese 1, 106a47a12beSStefan Roese 4 107a47a12beSStefan Roese }, 108a47a12beSStefan Roese { 109a47a12beSStefan Roese OP_LHAX, 110a47a12beSStefan Roese 3, 111a47a12beSStefan Roese 0, 112a47a12beSStefan Roese 1, 113a47a12beSStefan Roese 2 114a47a12beSStefan Roese }, 115a47a12beSStefan Roese { 116a47a12beSStefan Roese OP_LHZX, 117a47a12beSStefan Roese 2, 118a47a12beSStefan Roese 0, 119a47a12beSStefan Roese 1, 120a47a12beSStefan Roese 2 121a47a12beSStefan Roese }, 122a47a12beSStefan Roese { 123a47a12beSStefan Roese OP_LBZX, 124a47a12beSStefan Roese 1, 125a47a12beSStefan Roese 0, 126a47a12beSStefan Roese 1, 127a47a12beSStefan Roese 1 128a47a12beSStefan Roese }, 129a47a12beSStefan Roese { 130a47a12beSStefan Roese OP_LWZUX, 131a47a12beSStefan Roese 4, 132a47a12beSStefan Roese 1, 133a47a12beSStefan Roese 1, 134a47a12beSStefan Roese 4 135a47a12beSStefan Roese }, 136a47a12beSStefan Roese { 137a47a12beSStefan Roese OP_LHAUX, 138a47a12beSStefan Roese 3, 139a47a12beSStefan Roese 1, 140a47a12beSStefan Roese 1, 141a47a12beSStefan Roese 2 142a47a12beSStefan Roese }, 143a47a12beSStefan Roese { 144a47a12beSStefan Roese OP_LHZUX, 145a47a12beSStefan Roese 2, 146a47a12beSStefan Roese 1, 147a47a12beSStefan Roese 1, 148a47a12beSStefan Roese 2 149a47a12beSStefan Roese }, 150a47a12beSStefan Roese { 151a47a12beSStefan Roese OP_LBZUX, 152a47a12beSStefan Roese 1, 153a47a12beSStefan Roese 1, 154a47a12beSStefan Roese 1, 155a47a12beSStefan Roese 1 156a47a12beSStefan Roese }, 157a47a12beSStefan Roese }; 158d2397817SMike Frysinger static unsigned int cpu_post_load_size = ARRAY_SIZE(cpu_post_load_table); 159a47a12beSStefan Roese 160a47a12beSStefan Roese int cpu_post_test_load (void) 161a47a12beSStefan Roese { 162a47a12beSStefan Roese int ret = 0; 163a47a12beSStefan Roese unsigned int i; 164a47a12beSStefan Roese int flag = disable_interrupts(); 165a47a12beSStefan Roese 166a47a12beSStefan Roese for (i = 0; i < cpu_post_load_size && ret == 0; i++) 167a47a12beSStefan Roese { 168a47a12beSStefan Roese struct cpu_post_load_s *test = cpu_post_load_table + i; 169a47a12beSStefan Roese uchar data[16] = 170a47a12beSStefan Roese { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 }; 171a47a12beSStefan Roese ulong base0 = (ulong) (data + 8); 172a47a12beSStefan Roese ulong base = base0; 173a47a12beSStefan Roese ulong value; 174a47a12beSStefan Roese 175a47a12beSStefan Roese if (test->index) 176a47a12beSStefan Roese { 177a47a12beSStefan Roese ulong code[] = 178a47a12beSStefan Roese { 179a47a12beSStefan Roese ASM_12(test->cmd, 5, 3, 4), 180a47a12beSStefan Roese ASM_BLR, 181a47a12beSStefan Roese }; 182a47a12beSStefan Roese 183a47a12beSStefan Roese cpu_post_exec_22w (code, &base, test->offset, &value); 184a47a12beSStefan Roese } 185a47a12beSStefan Roese else 186a47a12beSStefan Roese { 187a47a12beSStefan Roese ulong code[] = 188a47a12beSStefan Roese { 189a47a12beSStefan Roese ASM_11I(test->cmd, 4, 3, test->offset), 190a47a12beSStefan Roese ASM_BLR, 191a47a12beSStefan Roese }; 192a47a12beSStefan Roese 193a47a12beSStefan Roese cpu_post_exec_21w (code, &base, &value); 194a47a12beSStefan Roese } 195a47a12beSStefan Roese 196a47a12beSStefan Roese if (ret == 0) 197a47a12beSStefan Roese { 198a47a12beSStefan Roese if (test->update) 199a47a12beSStefan Roese ret = base == base0 + test->offset ? 0 : -1; 200a47a12beSStefan Roese else 201a47a12beSStefan Roese ret = base == base0 ? 0 : -1; 202a47a12beSStefan Roese } 203a47a12beSStefan Roese 204a47a12beSStefan Roese if (ret == 0) 205a47a12beSStefan Roese { 206a47a12beSStefan Roese switch (test->width) 207a47a12beSStefan Roese { 208a47a12beSStefan Roese case 1: 209a47a12beSStefan Roese ret = *(uchar *)(base0 + test->offset) == value ? 210a47a12beSStefan Roese 0 : -1; 211a47a12beSStefan Roese break; 212a47a12beSStefan Roese case 2: 213a47a12beSStefan Roese ret = *(ushort *)(base0 + test->offset) == value ? 214a47a12beSStefan Roese 0 : -1; 215a47a12beSStefan Roese break; 216a47a12beSStefan Roese case 3: 217a47a12beSStefan Roese ret = *(short *)(base0 + test->offset) == value ? 218a47a12beSStefan Roese 0 : -1; 219a47a12beSStefan Roese break; 220a47a12beSStefan Roese case 4: 221a47a12beSStefan Roese ret = *(ulong *)(base0 + test->offset) == value ? 222a47a12beSStefan Roese 0 : -1; 223a47a12beSStefan Roese break; 224a47a12beSStefan Roese } 225a47a12beSStefan Roese } 226a47a12beSStefan Roese 227a47a12beSStefan Roese if (ret != 0) 228a47a12beSStefan Roese { 229a47a12beSStefan Roese post_log ("Error at load test %d !\n", i); 230a47a12beSStefan Roese } 231a47a12beSStefan Roese } 232a47a12beSStefan Roese 233a47a12beSStefan Roese if (flag) 234a47a12beSStefan Roese enable_interrupts(); 235a47a12beSStefan Roese 236a47a12beSStefan Roese return ret; 237a47a12beSStefan Roese } 238a47a12beSStefan Roese 239a47a12beSStefan Roese #endif 240