1a47a12beSStefan Roese /* 2a47a12beSStefan Roese * (C) Copyright 2002 3a47a12beSStefan Roese * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4a47a12beSStefan Roese * 5*1a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 6a47a12beSStefan Roese */ 7a47a12beSStefan Roese 8a47a12beSStefan Roese #include <common.h> 9a47a12beSStefan Roese 10a47a12beSStefan Roese /* 11a47a12beSStefan Roese * CPU test 12a47a12beSStefan Roese * 13a47a12beSStefan Roese * This test checks the arithmetic logic unit (ALU) of CPU. 14a47a12beSStefan Roese * It tests independently various groups of instructions using 15a47a12beSStefan Roese * run-time modification of the code to reduce the memory footprint. 16a47a12beSStefan Roese * For more details refer to post/cpu/ *.c files. 17a47a12beSStefan Roese */ 18a47a12beSStefan Roese 19a47a12beSStefan Roese #include <watchdog.h> 20a47a12beSStefan Roese #include <post.h> 21a47a12beSStefan Roese #include <asm/mmu.h> 22a47a12beSStefan Roese 23a47a12beSStefan Roese #if CONFIG_POST & CONFIG_SYS_POST_CPU 24a47a12beSStefan Roese 25a47a12beSStefan Roese extern int cpu_post_test_cmp (void); 26a47a12beSStefan Roese extern int cpu_post_test_cmpi (void); 27a47a12beSStefan Roese extern int cpu_post_test_two (void); 28a47a12beSStefan Roese extern int cpu_post_test_twox (void); 29a47a12beSStefan Roese extern int cpu_post_test_three (void); 30a47a12beSStefan Roese extern int cpu_post_test_threex (void); 31a47a12beSStefan Roese extern int cpu_post_test_threei (void); 32a47a12beSStefan Roese extern int cpu_post_test_andi (void); 33a47a12beSStefan Roese extern int cpu_post_test_srawi (void); 34a47a12beSStefan Roese extern int cpu_post_test_rlwnm (void); 35a47a12beSStefan Roese extern int cpu_post_test_rlwinm (void); 36a47a12beSStefan Roese extern int cpu_post_test_rlwimi (void); 37a47a12beSStefan Roese extern int cpu_post_test_store (void); 38a47a12beSStefan Roese extern int cpu_post_test_load (void); 39a47a12beSStefan Roese extern int cpu_post_test_cr (void); 40a47a12beSStefan Roese extern int cpu_post_test_b (void); 41a47a12beSStefan Roese extern int cpu_post_test_multi (void); 42a47a12beSStefan Roese extern int cpu_post_test_string (void); 43a47a12beSStefan Roese extern int cpu_post_test_complex (void); 44a47a12beSStefan Roese 45a47a12beSStefan Roese DECLARE_GLOBAL_DATA_PTR; 46a47a12beSStefan Roese 47a47a12beSStefan Roese ulong cpu_post_makecr (long v) 48a47a12beSStefan Roese { 49a47a12beSStefan Roese ulong cr = 0; 50a47a12beSStefan Roese 51a47a12beSStefan Roese if (v < 0) 52a47a12beSStefan Roese cr |= 0x80000000; 53a47a12beSStefan Roese if (v > 0) 54a47a12beSStefan Roese cr |= 0x40000000; 55a47a12beSStefan Roese if (v == 0) 56a47a12beSStefan Roese cr |= 0x20000000; 57a47a12beSStefan Roese 58a47a12beSStefan Roese return cr; 59a47a12beSStefan Roese } 60a47a12beSStefan Roese 61a47a12beSStefan Roese int cpu_post_test (int flags) 62a47a12beSStefan Roese { 63a47a12beSStefan Roese int ic = icache_status (); 64a47a12beSStefan Roese int ret = 0; 65a47a12beSStefan Roese 66a47a12beSStefan Roese WATCHDOG_RESET(); 67a47a12beSStefan Roese if (ic) 68a47a12beSStefan Roese icache_disable (); 69a47a12beSStefan Roese #ifdef CONFIG_4xx_DCACHE 70a47a12beSStefan Roese /* disable cache */ 71a47a12beSStefan Roese change_tlb(gd->bd->bi_memstart, gd->bd->bi_memsize, TLB_WORD2_I_ENABLE); 72a47a12beSStefan Roese #endif 73a47a12beSStefan Roese 74a47a12beSStefan Roese if (ret == 0) 75a47a12beSStefan Roese ret = cpu_post_test_cmp (); 76a47a12beSStefan Roese if (ret == 0) 77a47a12beSStefan Roese ret = cpu_post_test_cmpi (); 78a47a12beSStefan Roese if (ret == 0) 79a47a12beSStefan Roese ret = cpu_post_test_two (); 80a47a12beSStefan Roese if (ret == 0) 81a47a12beSStefan Roese ret = cpu_post_test_twox (); 82a47a12beSStefan Roese WATCHDOG_RESET(); 83a47a12beSStefan Roese if (ret == 0) 84a47a12beSStefan Roese ret = cpu_post_test_three (); 85a47a12beSStefan Roese if (ret == 0) 86a47a12beSStefan Roese ret = cpu_post_test_threex (); 87a47a12beSStefan Roese if (ret == 0) 88a47a12beSStefan Roese ret = cpu_post_test_threei (); 89a47a12beSStefan Roese if (ret == 0) 90a47a12beSStefan Roese ret = cpu_post_test_andi (); 91a47a12beSStefan Roese WATCHDOG_RESET(); 92a47a12beSStefan Roese if (ret == 0) 93a47a12beSStefan Roese ret = cpu_post_test_srawi (); 94a47a12beSStefan Roese if (ret == 0) 95a47a12beSStefan Roese ret = cpu_post_test_rlwnm (); 96a47a12beSStefan Roese if (ret == 0) 97a47a12beSStefan Roese ret = cpu_post_test_rlwinm (); 98a47a12beSStefan Roese if (ret == 0) 99a47a12beSStefan Roese ret = cpu_post_test_rlwimi (); 100a47a12beSStefan Roese WATCHDOG_RESET(); 101a47a12beSStefan Roese if (ret == 0) 102a47a12beSStefan Roese ret = cpu_post_test_store (); 103a47a12beSStefan Roese if (ret == 0) 104a47a12beSStefan Roese ret = cpu_post_test_load (); 105a47a12beSStefan Roese if (ret == 0) 106a47a12beSStefan Roese ret = cpu_post_test_cr (); 107a47a12beSStefan Roese if (ret == 0) 108a47a12beSStefan Roese ret = cpu_post_test_b (); 109a47a12beSStefan Roese WATCHDOG_RESET(); 110a47a12beSStefan Roese if (ret == 0) 111a47a12beSStefan Roese ret = cpu_post_test_multi (); 112a47a12beSStefan Roese WATCHDOG_RESET(); 113a47a12beSStefan Roese if (ret == 0) 114a47a12beSStefan Roese ret = cpu_post_test_string (); 115a47a12beSStefan Roese if (ret == 0) 116a47a12beSStefan Roese ret = cpu_post_test_complex (); 117a47a12beSStefan Roese WATCHDOG_RESET(); 118a47a12beSStefan Roese 119a47a12beSStefan Roese if (ic) 120a47a12beSStefan Roese icache_enable (); 121a47a12beSStefan Roese #ifdef CONFIG_4xx_DCACHE 122a47a12beSStefan Roese /* enable cache */ 123a47a12beSStefan Roese change_tlb(gd->bd->bi_memstart, gd->bd->bi_memsize, 0); 124a47a12beSStefan Roese #endif 125a47a12beSStefan Roese 126a47a12beSStefan Roese WATCHDOG_RESET(); 127a47a12beSStefan Roese 128a47a12beSStefan Roese return ret; 129a47a12beSStefan Roese } 130a47a12beSStefan Roese 131a47a12beSStefan Roese #endif /* CONFIG_POST & CONFIG_SYS_POST_CPU */ 132