1*a47a12beSStefan Roese /* 2*a47a12beSStefan Roese * (C) Copyright 2002 3*a47a12beSStefan Roese * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4*a47a12beSStefan Roese * 5*a47a12beSStefan Roese * See file CREDITS for list of people who contributed to this 6*a47a12beSStefan Roese * project. 7*a47a12beSStefan Roese * 8*a47a12beSStefan Roese * This program is free software; you can redistribute it and/or 9*a47a12beSStefan Roese * modify it under the terms of the GNU General Public License as 10*a47a12beSStefan Roese * published by the Free Software Foundation; either version 2 of 11*a47a12beSStefan Roese * the License, or (at your option) any later version. 12*a47a12beSStefan Roese * 13*a47a12beSStefan Roese * This program is distributed in the hope that it will be useful, 14*a47a12beSStefan Roese * but WITHOUT ANY WARRANTY; without even the implied warranty of 15*a47a12beSStefan Roese * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16*a47a12beSStefan Roese * GNU General Public License for more details. 17*a47a12beSStefan Roese * 18*a47a12beSStefan Roese * You should have received a copy of the GNU General Public License 19*a47a12beSStefan Roese * along with this program; if not, write to the Free Software 20*a47a12beSStefan Roese * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21*a47a12beSStefan Roese * MA 02111-1307 USA 22*a47a12beSStefan Roese */ 23*a47a12beSStefan Roese 24*a47a12beSStefan Roese #include <common.h> 25*a47a12beSStefan Roese 26*a47a12beSStefan Roese /* 27*a47a12beSStefan Roese * CPU test 28*a47a12beSStefan Roese * Integer compare instructions: cmpw, cmplw 29*a47a12beSStefan Roese * 30*a47a12beSStefan Roese * To verify these instructions the test runs them with 31*a47a12beSStefan Roese * different combinations of operands, reads the condition 32*a47a12beSStefan Roese * register value and compares it with the expected one. 33*a47a12beSStefan Roese * The test contains a pre-built table 34*a47a12beSStefan Roese * containing the description of each test case: the instruction, 35*a47a12beSStefan Roese * the values of the operands, the condition field to save 36*a47a12beSStefan Roese * the result in and the expected result. 37*a47a12beSStefan Roese */ 38*a47a12beSStefan Roese 39*a47a12beSStefan Roese #include <post.h> 40*a47a12beSStefan Roese #include "cpu_asm.h" 41*a47a12beSStefan Roese 42*a47a12beSStefan Roese #if CONFIG_POST & CONFIG_SYS_POST_CPU 43*a47a12beSStefan Roese 44*a47a12beSStefan Roese extern void cpu_post_exec_12 (ulong *code, ulong *res, ulong op1, ulong op2); 45*a47a12beSStefan Roese 46*a47a12beSStefan Roese static struct cpu_post_cmp_s 47*a47a12beSStefan Roese { 48*a47a12beSStefan Roese ulong cmd; 49*a47a12beSStefan Roese ulong op1; 50*a47a12beSStefan Roese ulong op2; 51*a47a12beSStefan Roese ulong cr; 52*a47a12beSStefan Roese ulong res; 53*a47a12beSStefan Roese } cpu_post_cmp_table[] = 54*a47a12beSStefan Roese { 55*a47a12beSStefan Roese { 56*a47a12beSStefan Roese OP_CMPW, 57*a47a12beSStefan Roese 123, 58*a47a12beSStefan Roese 123, 59*a47a12beSStefan Roese 2, 60*a47a12beSStefan Roese 0x02 61*a47a12beSStefan Roese }, 62*a47a12beSStefan Roese { 63*a47a12beSStefan Roese OP_CMPW, 64*a47a12beSStefan Roese 123, 65*a47a12beSStefan Roese 133, 66*a47a12beSStefan Roese 3, 67*a47a12beSStefan Roese 0x08 68*a47a12beSStefan Roese }, 69*a47a12beSStefan Roese { 70*a47a12beSStefan Roese OP_CMPW, 71*a47a12beSStefan Roese 123, 72*a47a12beSStefan Roese -133, 73*a47a12beSStefan Roese 4, 74*a47a12beSStefan Roese 0x04 75*a47a12beSStefan Roese }, 76*a47a12beSStefan Roese { 77*a47a12beSStefan Roese OP_CMPLW, 78*a47a12beSStefan Roese 123, 79*a47a12beSStefan Roese 123, 80*a47a12beSStefan Roese 2, 81*a47a12beSStefan Roese 0x02 82*a47a12beSStefan Roese }, 83*a47a12beSStefan Roese { 84*a47a12beSStefan Roese OP_CMPLW, 85*a47a12beSStefan Roese 123, 86*a47a12beSStefan Roese -133, 87*a47a12beSStefan Roese 3, 88*a47a12beSStefan Roese 0x08 89*a47a12beSStefan Roese }, 90*a47a12beSStefan Roese { 91*a47a12beSStefan Roese OP_CMPLW, 92*a47a12beSStefan Roese 123, 93*a47a12beSStefan Roese 113, 94*a47a12beSStefan Roese 4, 95*a47a12beSStefan Roese 0x04 96*a47a12beSStefan Roese }, 97*a47a12beSStefan Roese }; 98*a47a12beSStefan Roese static unsigned int cpu_post_cmp_size = 99*a47a12beSStefan Roese sizeof (cpu_post_cmp_table) / sizeof (struct cpu_post_cmp_s); 100*a47a12beSStefan Roese 101*a47a12beSStefan Roese int cpu_post_test_cmp (void) 102*a47a12beSStefan Roese { 103*a47a12beSStefan Roese int ret = 0; 104*a47a12beSStefan Roese unsigned int i; 105*a47a12beSStefan Roese int flag = disable_interrupts(); 106*a47a12beSStefan Roese 107*a47a12beSStefan Roese for (i = 0; i < cpu_post_cmp_size && ret == 0; i++) 108*a47a12beSStefan Roese { 109*a47a12beSStefan Roese struct cpu_post_cmp_s *test = cpu_post_cmp_table + i; 110*a47a12beSStefan Roese unsigned long code[] = 111*a47a12beSStefan Roese { 112*a47a12beSStefan Roese ASM_2C(test->cmd, test->cr, 3, 4), 113*a47a12beSStefan Roese ASM_MFCR(3), 114*a47a12beSStefan Roese ASM_BLR 115*a47a12beSStefan Roese }; 116*a47a12beSStefan Roese ulong res; 117*a47a12beSStefan Roese 118*a47a12beSStefan Roese cpu_post_exec_12 (code, & res, test->op1, test->op2); 119*a47a12beSStefan Roese 120*a47a12beSStefan Roese ret = ((res >> (28 - 4 * test->cr)) & 0xe) == test->res ? 0 : -1; 121*a47a12beSStefan Roese 122*a47a12beSStefan Roese if (ret != 0) 123*a47a12beSStefan Roese { 124*a47a12beSStefan Roese post_log ("Error at cmp test %d !\n", i); 125*a47a12beSStefan Roese } 126*a47a12beSStefan Roese } 127*a47a12beSStefan Roese 128*a47a12beSStefan Roese if (flag) 129*a47a12beSStefan Roese enable_interrupts(); 130*a47a12beSStefan Roese 131*a47a12beSStefan Roese return ret; 132*a47a12beSStefan Roese } 133*a47a12beSStefan Roese 134*a47a12beSStefan Roese #endif 135