1*a47a12beSStefan Roese /* 2*a47a12beSStefan Roese * (C) Copyright 2002 3*a47a12beSStefan Roese * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4*a47a12beSStefan Roese * 5*a47a12beSStefan Roese * See file CREDITS for list of people who contributed to this 6*a47a12beSStefan Roese * project. 7*a47a12beSStefan Roese * 8*a47a12beSStefan Roese * This program is free software; you can redistribute it and/or 9*a47a12beSStefan Roese * modify it under the terms of the GNU General Public License as 10*a47a12beSStefan Roese * published by the Free Software Foundation; either version 2 of 11*a47a12beSStefan Roese * the License, or (at your option) any later version. 12*a47a12beSStefan Roese * 13*a47a12beSStefan Roese * This program is distributed in the hope that it will be useful, 14*a47a12beSStefan Roese * but WITHOUT ANY WARRANTY; without even the implied warranty of 15*a47a12beSStefan Roese * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16*a47a12beSStefan Roese * GNU General Public License for more details. 17*a47a12beSStefan Roese * 18*a47a12beSStefan Roese * You should have received a copy of the GNU General Public License 19*a47a12beSStefan Roese * along with this program; if not, write to the Free Software 20*a47a12beSStefan Roese * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21*a47a12beSStefan Roese * MA 02111-1307 USA 22*a47a12beSStefan Roese */ 23*a47a12beSStefan Roese 24*a47a12beSStefan Roese #include <common.h> 25*a47a12beSStefan Roese 26*a47a12beSStefan Roese /* 27*a47a12beSStefan Roese * CPU test 28*a47a12beSStefan Roese * Branch instructions: b, bl, bc 29*a47a12beSStefan Roese * 30*a47a12beSStefan Roese * The first 2 instructions (b, bl) are verified by jumping 31*a47a12beSStefan Roese * to a fixed address and checking whether control was transfered 32*a47a12beSStefan Roese * to that very point. For the bl instruction the value of the 33*a47a12beSStefan Roese * link register is checked as well (using mfspr). 34*a47a12beSStefan Roese * To verify the bc instruction various combinations of the BI/BO 35*a47a12beSStefan Roese * fields, the CTR and the condition register values are 36*a47a12beSStefan Roese * checked. The list of such combinations is pre-built and 37*a47a12beSStefan Roese * linked in U-Boot at build time. 38*a47a12beSStefan Roese */ 39*a47a12beSStefan Roese 40*a47a12beSStefan Roese #include <post.h> 41*a47a12beSStefan Roese #include "cpu_asm.h" 42*a47a12beSStefan Roese 43*a47a12beSStefan Roese #if CONFIG_POST & CONFIG_SYS_POST_CPU 44*a47a12beSStefan Roese 45*a47a12beSStefan Roese extern void cpu_post_exec_11 (ulong *code, ulong *res, ulong op1); 46*a47a12beSStefan Roese extern void cpu_post_exec_31 (ulong *code, ulong *ctr, ulong *lr, ulong *jump, 47*a47a12beSStefan Roese ulong cr); 48*a47a12beSStefan Roese 49*a47a12beSStefan Roese static int cpu_post_test_bc (ulong cmd, ulong bo, ulong bi, 50*a47a12beSStefan Roese int pjump, int decr, int link, ulong pctr, ulong cr) 51*a47a12beSStefan Roese { 52*a47a12beSStefan Roese int ret = 0; 53*a47a12beSStefan Roese ulong lr = 0; 54*a47a12beSStefan Roese ulong ctr = pctr; 55*a47a12beSStefan Roese ulong jump; 56*a47a12beSStefan Roese 57*a47a12beSStefan Roese unsigned long code[] = 58*a47a12beSStefan Roese { 59*a47a12beSStefan Roese ASM_MTCR(6), 60*a47a12beSStefan Roese ASM_MFLR(6), 61*a47a12beSStefan Roese ASM_MTCTR(3), 62*a47a12beSStefan Roese ASM_MTLR(4), 63*a47a12beSStefan Roese ASM_LI(5, 1), 64*a47a12beSStefan Roese ASM_3O(cmd, bo, bi, 8), 65*a47a12beSStefan Roese ASM_LI(5, 0), 66*a47a12beSStefan Roese ASM_MFCTR(3), 67*a47a12beSStefan Roese ASM_MFLR(4), 68*a47a12beSStefan Roese ASM_MTLR(6), 69*a47a12beSStefan Roese ASM_BLR, 70*a47a12beSStefan Roese }; 71*a47a12beSStefan Roese 72*a47a12beSStefan Roese cpu_post_exec_31 (code, &ctr, &lr, &jump, cr); 73*a47a12beSStefan Roese 74*a47a12beSStefan Roese if (ret == 0) 75*a47a12beSStefan Roese ret = pjump == jump ? 0 : -1; 76*a47a12beSStefan Roese if (ret == 0) 77*a47a12beSStefan Roese { 78*a47a12beSStefan Roese if (decr) 79*a47a12beSStefan Roese ret = pctr == ctr + 1 ? 0 : -1; 80*a47a12beSStefan Roese else 81*a47a12beSStefan Roese ret = pctr == ctr ? 0 : -1; 82*a47a12beSStefan Roese } 83*a47a12beSStefan Roese if (ret == 0) 84*a47a12beSStefan Roese { 85*a47a12beSStefan Roese if (link) 86*a47a12beSStefan Roese ret = lr == (ulong) code + 24 ? 0 : -1; 87*a47a12beSStefan Roese else 88*a47a12beSStefan Roese ret = lr == 0 ? 0 : -1; 89*a47a12beSStefan Roese } 90*a47a12beSStefan Roese 91*a47a12beSStefan Roese return ret; 92*a47a12beSStefan Roese } 93*a47a12beSStefan Roese 94*a47a12beSStefan Roese int cpu_post_test_b (void) 95*a47a12beSStefan Roese { 96*a47a12beSStefan Roese int ret = 0; 97*a47a12beSStefan Roese unsigned int i; 98*a47a12beSStefan Roese int flag = disable_interrupts(); 99*a47a12beSStefan Roese 100*a47a12beSStefan Roese if (ret == 0) 101*a47a12beSStefan Roese { 102*a47a12beSStefan Roese ulong code[] = 103*a47a12beSStefan Roese { 104*a47a12beSStefan Roese ASM_MFLR(4), 105*a47a12beSStefan Roese ASM_MTLR(3), 106*a47a12beSStefan Roese ASM_B(4), 107*a47a12beSStefan Roese ASM_MFLR(3), 108*a47a12beSStefan Roese ASM_MTLR(4), 109*a47a12beSStefan Roese ASM_BLR, 110*a47a12beSStefan Roese }; 111*a47a12beSStefan Roese ulong res; 112*a47a12beSStefan Roese 113*a47a12beSStefan Roese cpu_post_exec_11 (code, &res, 0); 114*a47a12beSStefan Roese 115*a47a12beSStefan Roese ret = res == 0 ? 0 : -1; 116*a47a12beSStefan Roese 117*a47a12beSStefan Roese if (ret != 0) 118*a47a12beSStefan Roese { 119*a47a12beSStefan Roese post_log ("Error at b1 test !\n"); 120*a47a12beSStefan Roese } 121*a47a12beSStefan Roese } 122*a47a12beSStefan Roese 123*a47a12beSStefan Roese if (ret == 0) 124*a47a12beSStefan Roese { 125*a47a12beSStefan Roese ulong code[] = 126*a47a12beSStefan Roese { 127*a47a12beSStefan Roese ASM_MFLR(4), 128*a47a12beSStefan Roese ASM_MTLR(3), 129*a47a12beSStefan Roese ASM_BL(4), 130*a47a12beSStefan Roese ASM_MFLR(3), 131*a47a12beSStefan Roese ASM_MTLR(4), 132*a47a12beSStefan Roese ASM_BLR, 133*a47a12beSStefan Roese }; 134*a47a12beSStefan Roese ulong res; 135*a47a12beSStefan Roese 136*a47a12beSStefan Roese cpu_post_exec_11 (code, &res, 0); 137*a47a12beSStefan Roese 138*a47a12beSStefan Roese ret = res == (ulong)code + 12 ? 0 : -1; 139*a47a12beSStefan Roese 140*a47a12beSStefan Roese if (ret != 0) 141*a47a12beSStefan Roese { 142*a47a12beSStefan Roese post_log ("Error at b2 test !\n"); 143*a47a12beSStefan Roese } 144*a47a12beSStefan Roese } 145*a47a12beSStefan Roese 146*a47a12beSStefan Roese if (ret == 0) 147*a47a12beSStefan Roese { 148*a47a12beSStefan Roese ulong cc, cd; 149*a47a12beSStefan Roese int cond; 150*a47a12beSStefan Roese ulong ctr; 151*a47a12beSStefan Roese int link; 152*a47a12beSStefan Roese 153*a47a12beSStefan Roese i = 0; 154*a47a12beSStefan Roese 155*a47a12beSStefan Roese for (cc = 0; cc < 4 && ret == 0; cc++) 156*a47a12beSStefan Roese { 157*a47a12beSStefan Roese for (cd = 0; cd < 4 && ret == 0; cd++) 158*a47a12beSStefan Roese { 159*a47a12beSStefan Roese for (link = 0; link <= 1 && ret == 0; link++) 160*a47a12beSStefan Roese { 161*a47a12beSStefan Roese for (cond = 0; cond <= 1 && ret == 0; cond++) 162*a47a12beSStefan Roese { 163*a47a12beSStefan Roese for (ctr = 1; ctr <= 2 && ret == 0; ctr++) 164*a47a12beSStefan Roese { 165*a47a12beSStefan Roese int decr = cd < 2; 166*a47a12beSStefan Roese int cr = cond ? 0x80000000 : 0x00000000; 167*a47a12beSStefan Roese int jumpc = cc >= 2 || 168*a47a12beSStefan Roese (cc == 0 && !cond) || 169*a47a12beSStefan Roese (cc == 1 && cond); 170*a47a12beSStefan Roese int jumpd = cd >= 2 || 171*a47a12beSStefan Roese (cd == 0 && ctr != 1) || 172*a47a12beSStefan Roese (cd == 1 && ctr == 1); 173*a47a12beSStefan Roese int jump = jumpc && jumpd; 174*a47a12beSStefan Roese 175*a47a12beSStefan Roese ret = cpu_post_test_bc (link ? OP_BCL : OP_BC, 176*a47a12beSStefan Roese (cc << 3) + (cd << 1), 0, jump, decr, link, 177*a47a12beSStefan Roese ctr, cr); 178*a47a12beSStefan Roese 179*a47a12beSStefan Roese if (ret != 0) 180*a47a12beSStefan Roese { 181*a47a12beSStefan Roese post_log ("Error at b3 test %d !\n", i); 182*a47a12beSStefan Roese } 183*a47a12beSStefan Roese 184*a47a12beSStefan Roese i++; 185*a47a12beSStefan Roese } 186*a47a12beSStefan Roese } 187*a47a12beSStefan Roese } 188*a47a12beSStefan Roese } 189*a47a12beSStefan Roese } 190*a47a12beSStefan Roese } 191*a47a12beSStefan Roese 192*a47a12beSStefan Roese if (flag) 193*a47a12beSStefan Roese enable_interrupts(); 194*a47a12beSStefan Roese 195*a47a12beSStefan Roese return ret; 196*a47a12beSStefan Roese } 197*a47a12beSStefan Roese 198*a47a12beSStefan Roese #endif 199