xref: /rk3399_rockchip-uboot/post/lib_powerpc/asm.S (revision a47a12becf66f02a56da91c161e2edb625e9f20c)
1*a47a12beSStefan Roese/*
2*a47a12beSStefan Roese *  Copyright (C) 2002 Wolfgang Denk <wd@denx.de>
3*a47a12beSStefan Roese *
4*a47a12beSStefan Roese * See file CREDITS for list of people who contributed to this
5*a47a12beSStefan Roese * project.
6*a47a12beSStefan Roese *
7*a47a12beSStefan Roese * This program is free software; you can redistribute it and/or
8*a47a12beSStefan Roese * modify it under the terms of the GNU General Public License as
9*a47a12beSStefan Roese * published by the Free Software Foundation; either version 2 of
10*a47a12beSStefan Roese * the License, or (at your option) any later version.
11*a47a12beSStefan Roese *
12*a47a12beSStefan Roese * This program is distributed in the hope that it will be useful,
13*a47a12beSStefan Roese * but WITHOUT ANY WARRANTY; without even the implied warranty of
14*a47a12beSStefan Roese * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15*a47a12beSStefan Roese * GNU General Public License for more details.
16*a47a12beSStefan Roese *
17*a47a12beSStefan Roese * You should have received a copy of the GNU General Public License
18*a47a12beSStefan Roese * along with this program; if not, write to the Free Software
19*a47a12beSStefan Roese * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20*a47a12beSStefan Roese * MA 02111-1307 USA
21*a47a12beSStefan Roese */
22*a47a12beSStefan Roese
23*a47a12beSStefan Roese#include <config.h>
24*a47a12beSStefan Roese
25*a47a12beSStefan Roese#include <post.h>
26*a47a12beSStefan Roese#include <ppc_asm.tmpl>
27*a47a12beSStefan Roese#include <ppc_defs.h>
28*a47a12beSStefan Roese#include <asm/cache.h>
29*a47a12beSStefan Roese
30*a47a12beSStefan Roese#if CONFIG_POST & CONFIG_SYS_POST_CPU
31*a47a12beSStefan Roese
32*a47a12beSStefan Roese/* void cpu_post_exec_02 (ulong *code, ulong op1, ulong op2); */
33*a47a12beSStefan Roese	.global	cpu_post_exec_02
34*a47a12beSStefan Roesecpu_post_exec_02:
35*a47a12beSStefan Roese	isync
36*a47a12beSStefan Roese	mflr	r0
37*a47a12beSStefan Roese	stwu	r0, -4(r1)
38*a47a12beSStefan Roese
39*a47a12beSStefan Roese	subi	r1, r1, 104
40*a47a12beSStefan Roese	stmw	r6, 0(r1)
41*a47a12beSStefan Roese
42*a47a12beSStefan Roese	mtlr	r3
43*a47a12beSStefan Roese	mr	r3, r4
44*a47a12beSStefan Roese	mr	r4, r5
45*a47a12beSStefan Roese	blrl
46*a47a12beSStefan Roese
47*a47a12beSStefan Roese	lmw	r6, 0(r1)
48*a47a12beSStefan Roese	addi	r1, r1, 104
49*a47a12beSStefan Roese
50*a47a12beSStefan Roese	lwz	r0, 0(r1)
51*a47a12beSStefan Roese	addi	r1, r1, 4
52*a47a12beSStefan Roese	mtlr	r0
53*a47a12beSStefan Roese	blr
54*a47a12beSStefan Roese
55*a47a12beSStefan Roese/* void cpu_post_exec_04 (ulong *code, ulong op1, ulong op2, ulong op3, ulong op4); */
56*a47a12beSStefan Roese	.global	cpu_post_exec_04
57*a47a12beSStefan Roesecpu_post_exec_04:
58*a47a12beSStefan Roese	isync
59*a47a12beSStefan Roese	mflr	r0
60*a47a12beSStefan Roese	stwu	r0, -4(r1)
61*a47a12beSStefan Roese
62*a47a12beSStefan Roese	subi	r1, r1, 96
63*a47a12beSStefan Roese	stmw	r8, 0(r1)
64*a47a12beSStefan Roese
65*a47a12beSStefan Roese	mtlr	r3
66*a47a12beSStefan Roese	mr	r3, r4
67*a47a12beSStefan Roese	mr	r4, r5
68*a47a12beSStefan Roese	mr	r5, r6
69*a47a12beSStefan Roese	mtxer	r7
70*a47a12beSStefan Roese	blrl
71*a47a12beSStefan Roese
72*a47a12beSStefan Roese	lmw	r8, 0(r1)
73*a47a12beSStefan Roese	addi	r1, r1, 96
74*a47a12beSStefan Roese
75*a47a12beSStefan Roese	lwz	r0, 0(r1)
76*a47a12beSStefan Roese	addi	r1, r1, 4
77*a47a12beSStefan Roese	mtlr	r0
78*a47a12beSStefan Roese	blr
79*a47a12beSStefan Roese
80*a47a12beSStefan Roese/* void cpu_post_exec_12 (ulong *code, ulong *res, ulong op1, ulong op2); */
81*a47a12beSStefan Roese	.global	cpu_post_exec_12
82*a47a12beSStefan Roesecpu_post_exec_12:
83*a47a12beSStefan Roese	isync
84*a47a12beSStefan Roese	mflr	r0
85*a47a12beSStefan Roese	stwu	r0, -4(r1)
86*a47a12beSStefan Roese	stwu	r4, -4(r1)
87*a47a12beSStefan Roese
88*a47a12beSStefan Roese	mtlr	r3
89*a47a12beSStefan Roese	mr	r3, r5
90*a47a12beSStefan Roese	mr	r4, r6
91*a47a12beSStefan Roese	blrl
92*a47a12beSStefan Roese
93*a47a12beSStefan Roese	lwz	r4, 0(r1)
94*a47a12beSStefan Roese	stw	r3, 0(r4)
95*a47a12beSStefan Roese
96*a47a12beSStefan Roese	lwz	r0, 4(r1)
97*a47a12beSStefan Roese	addi	r1, r1, 8
98*a47a12beSStefan Roese	mtlr	r0
99*a47a12beSStefan Roese	blr
100*a47a12beSStefan Roese
101*a47a12beSStefan Roese/* void cpu_post_exec_11 (ulong *code, ulong *res, ulong op1); */
102*a47a12beSStefan Roese	.global	cpu_post_exec_11
103*a47a12beSStefan Roesecpu_post_exec_11:
104*a47a12beSStefan Roese	isync
105*a47a12beSStefan Roese	mflr	r0
106*a47a12beSStefan Roese	stwu	r0, -4(r1)
107*a47a12beSStefan Roese	stwu	r4, -4(r1)
108*a47a12beSStefan Roese
109*a47a12beSStefan Roese	mtlr	r3
110*a47a12beSStefan Roese	mr	r3, r5
111*a47a12beSStefan Roese	blrl
112*a47a12beSStefan Roese
113*a47a12beSStefan Roese	lwz	r4, 0(r1)
114*a47a12beSStefan Roese	stw	r3, 0(r4)
115*a47a12beSStefan Roese
116*a47a12beSStefan Roese	lwz	r0, 4(r1)
117*a47a12beSStefan Roese	addi	r1, r1, 8
118*a47a12beSStefan Roese	mtlr	r0
119*a47a12beSStefan Roese	blr
120*a47a12beSStefan Roese
121*a47a12beSStefan Roese/* void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op1); */
122*a47a12beSStefan Roese	.global	cpu_post_exec_21
123*a47a12beSStefan Roesecpu_post_exec_21:
124*a47a12beSStefan Roese	isync
125*a47a12beSStefan Roese	mflr	r0
126*a47a12beSStefan Roese	stwu	r0, -4(r1)
127*a47a12beSStefan Roese	stwu	r4, -4(r1)
128*a47a12beSStefan Roese	stwu	r5, -4(r1)
129*a47a12beSStefan Roese
130*a47a12beSStefan Roese	li	r0, 0
131*a47a12beSStefan Roese	mtxer	r0
132*a47a12beSStefan Roese	lwz	r0, 0(r4)
133*a47a12beSStefan Roese	mtcr	r0
134*a47a12beSStefan Roese
135*a47a12beSStefan Roese	mtlr	r3
136*a47a12beSStefan Roese	mr	r3, r6
137*a47a12beSStefan Roese	blrl
138*a47a12beSStefan Roese
139*a47a12beSStefan Roese	mfcr	r0
140*a47a12beSStefan Roese	lwz	r4, 4(r1)
141*a47a12beSStefan Roese	stw	r0, 0(r4)
142*a47a12beSStefan Roese	lwz	r4, 0(r1)
143*a47a12beSStefan Roese	stw	r3, 0(r4)
144*a47a12beSStefan Roese
145*a47a12beSStefan Roese	lwz	r0, 8(r1)
146*a47a12beSStefan Roese	addi	r1, r1, 12
147*a47a12beSStefan Roese	mtlr	r0
148*a47a12beSStefan Roese	blr
149*a47a12beSStefan Roese
150*a47a12beSStefan Roese/* void cpu_post_exec_22 (ulong *code, ulong *cr, ulong *res, ulong op1,
151*a47a12beSStefan Roese    ulong op2); */
152*a47a12beSStefan Roese	.global	cpu_post_exec_22
153*a47a12beSStefan Roesecpu_post_exec_22:
154*a47a12beSStefan Roese	isync
155*a47a12beSStefan Roese	mflr	r0
156*a47a12beSStefan Roese	stwu	r0, -4(r1)
157*a47a12beSStefan Roese	stwu	r4, -4(r1)
158*a47a12beSStefan Roese	stwu	r5, -4(r1)
159*a47a12beSStefan Roese
160*a47a12beSStefan Roese	li	r0, 0
161*a47a12beSStefan Roese	mtxer	r0
162*a47a12beSStefan Roese	lwz	r0, 0(r4)
163*a47a12beSStefan Roese	mtcr	r0
164*a47a12beSStefan Roese
165*a47a12beSStefan Roese	mtlr	r3
166*a47a12beSStefan Roese	mr	r3, r6
167*a47a12beSStefan Roese	mr	r4, r7
168*a47a12beSStefan Roese	blrl
169*a47a12beSStefan Roese
170*a47a12beSStefan Roese	mfcr	r0
171*a47a12beSStefan Roese	lwz	r4, 4(r1)
172*a47a12beSStefan Roese	stw	r0, 0(r4)
173*a47a12beSStefan Roese	lwz	r4, 0(r1)
174*a47a12beSStefan Roese	stw	r3, 0(r4)
175*a47a12beSStefan Roese
176*a47a12beSStefan Roese	lwz	r0, 8(r1)
177*a47a12beSStefan Roese	addi	r1, r1, 12
178*a47a12beSStefan Roese	mtlr	r0
179*a47a12beSStefan Roese	blr
180*a47a12beSStefan Roese
181*a47a12beSStefan Roese/* void cpu_post_exec_12w (ulong *code, ulong *op1, ulong op2, ulong op3); */
182*a47a12beSStefan Roese	.global	cpu_post_exec_12w
183*a47a12beSStefan Roesecpu_post_exec_12w:
184*a47a12beSStefan Roese	isync
185*a47a12beSStefan Roese	mflr	r0
186*a47a12beSStefan Roese	stwu	r0, -4(r1)
187*a47a12beSStefan Roese	stwu	r4, -4(r1)
188*a47a12beSStefan Roese
189*a47a12beSStefan Roese	mtlr	r3
190*a47a12beSStefan Roese	lwz	r3, 0(r4)
191*a47a12beSStefan Roese	mr	r4, r5
192*a47a12beSStefan Roese	mr	r5, r6
193*a47a12beSStefan Roese	blrl
194*a47a12beSStefan Roese
195*a47a12beSStefan Roese	lwz	r4, 0(r1)
196*a47a12beSStefan Roese	stw	r3, 0(r4)
197*a47a12beSStefan Roese
198*a47a12beSStefan Roese	lwz	r0, 4(r1)
199*a47a12beSStefan Roese	addi	r1, r1, 8
200*a47a12beSStefan Roese	mtlr	r0
201*a47a12beSStefan Roese	blr
202*a47a12beSStefan Roese
203*a47a12beSStefan Roese/* void cpu_post_exec_11w (ulong *code, ulong *op1, ulong op2); */
204*a47a12beSStefan Roese	.global	cpu_post_exec_11w
205*a47a12beSStefan Roesecpu_post_exec_11w:
206*a47a12beSStefan Roese	isync
207*a47a12beSStefan Roese	mflr	r0
208*a47a12beSStefan Roese	stwu	r0, -4(r1)
209*a47a12beSStefan Roese	stwu	r4, -4(r1)
210*a47a12beSStefan Roese
211*a47a12beSStefan Roese	mtlr	r3
212*a47a12beSStefan Roese	lwz	r3, 0(r4)
213*a47a12beSStefan Roese	mr	r4, r5
214*a47a12beSStefan Roese	blrl
215*a47a12beSStefan Roese
216*a47a12beSStefan Roese	lwz	r4, 0(r1)
217*a47a12beSStefan Roese	stw	r3, 0(r4)
218*a47a12beSStefan Roese
219*a47a12beSStefan Roese	lwz	r0, 4(r1)
220*a47a12beSStefan Roese	addi	r1, r1, 8
221*a47a12beSStefan Roese	mtlr	r0
222*a47a12beSStefan Roese	blr
223*a47a12beSStefan Roese
224*a47a12beSStefan Roese/* void cpu_post_exec_22w (ulong *code, ulong *op1, ulong op2, ulong *op3); */
225*a47a12beSStefan Roese	.global	cpu_post_exec_22w
226*a47a12beSStefan Roesecpu_post_exec_22w:
227*a47a12beSStefan Roese	isync
228*a47a12beSStefan Roese	mflr	r0
229*a47a12beSStefan Roese	stwu	r0, -4(r1)
230*a47a12beSStefan Roese	stwu	r4, -4(r1)
231*a47a12beSStefan Roese	stwu	r6, -4(r1)
232*a47a12beSStefan Roese
233*a47a12beSStefan Roese	mtlr	r3
234*a47a12beSStefan Roese	lwz	r3, 0(r4)
235*a47a12beSStefan Roese	mr	r4, r5
236*a47a12beSStefan Roese	blrl
237*a47a12beSStefan Roese
238*a47a12beSStefan Roese	lwz	r4, 4(r1)
239*a47a12beSStefan Roese	stw	r3, 0(r4)
240*a47a12beSStefan Roese	lwz	r4, 0(r1)
241*a47a12beSStefan Roese	stw	r5, 0(r4)
242*a47a12beSStefan Roese
243*a47a12beSStefan Roese	lwz	r0, 8(r1)
244*a47a12beSStefan Roese	addi	r1, r1, 12
245*a47a12beSStefan Roese	mtlr	r0
246*a47a12beSStefan Roese	blr
247*a47a12beSStefan Roese
248*a47a12beSStefan Roese/* void cpu_post_exec_21w (ulong *code, ulong *op1, ulong *op2); */
249*a47a12beSStefan Roese	.global	cpu_post_exec_21w
250*a47a12beSStefan Roesecpu_post_exec_21w:
251*a47a12beSStefan Roese	isync
252*a47a12beSStefan Roese	mflr	r0
253*a47a12beSStefan Roese	stwu	r0, -4(r1)
254*a47a12beSStefan Roese	stwu	r4, -4(r1)
255*a47a12beSStefan Roese	stwu	r5, -4(r1)
256*a47a12beSStefan Roese
257*a47a12beSStefan Roese	mtlr	r3
258*a47a12beSStefan Roese	lwz	r3, 0(r4)
259*a47a12beSStefan Roese	blrl
260*a47a12beSStefan Roese
261*a47a12beSStefan Roese	lwz	r5, 4(r1)
262*a47a12beSStefan Roese	stw	r3, 0(r5)
263*a47a12beSStefan Roese	lwz	r5, 0(r1)
264*a47a12beSStefan Roese	stw	r4, 0(r5)
265*a47a12beSStefan Roese
266*a47a12beSStefan Roese	lwz	r0, 8(r1)
267*a47a12beSStefan Roese	addi	r1, r1, 12
268*a47a12beSStefan Roese	mtlr	r0
269*a47a12beSStefan Roese	blr
270*a47a12beSStefan Roese
271*a47a12beSStefan Roese/* void cpu_post_exec_21x (ulong *code, ulong *op1, ulong *op2, ulong op3); */
272*a47a12beSStefan Roese	.global	cpu_post_exec_21x
273*a47a12beSStefan Roesecpu_post_exec_21x:
274*a47a12beSStefan Roese	isync
275*a47a12beSStefan Roese	mflr	r0
276*a47a12beSStefan Roese	stwu	r0, -4(r1)
277*a47a12beSStefan Roese	stwu	r4, -4(r1)
278*a47a12beSStefan Roese	stwu	r5, -4(r1)
279*a47a12beSStefan Roese
280*a47a12beSStefan Roese	mtlr	r3
281*a47a12beSStefan Roese	mr	r3, r6
282*a47a12beSStefan Roese	blrl
283*a47a12beSStefan Roese
284*a47a12beSStefan Roese	lwz	r5, 4(r1)
285*a47a12beSStefan Roese	stw	r3, 0(r5)
286*a47a12beSStefan Roese	lwz	r5, 0(r1)
287*a47a12beSStefan Roese	stw	r4, 0(r5)
288*a47a12beSStefan Roese
289*a47a12beSStefan Roese	lwz	r0, 8(r1)
290*a47a12beSStefan Roese	addi	r1, r1, 12
291*a47a12beSStefan Roese	mtlr	r0
292*a47a12beSStefan Roese	blr
293*a47a12beSStefan Roese
294*a47a12beSStefan Roese/* void cpu_post_exec_31 (ulong *code, ulong *ctr, ulong *lr, ulong *jump,
295*a47a12beSStefan Roese    ulong cr); */
296*a47a12beSStefan Roese	.global	cpu_post_exec_31
297*a47a12beSStefan Roesecpu_post_exec_31:
298*a47a12beSStefan Roese	isync
299*a47a12beSStefan Roese	mflr	r0
300*a47a12beSStefan Roese	stwu	r0, -4(r1)
301*a47a12beSStefan Roese	stwu	r4, -4(r1)
302*a47a12beSStefan Roese	stwu	r5, -4(r1)
303*a47a12beSStefan Roese	stwu	r6, -4(r1)
304*a47a12beSStefan Roese
305*a47a12beSStefan Roese	mtlr	r3
306*a47a12beSStefan Roese	lwz	r3, 0(r4)
307*a47a12beSStefan Roese	lwz	r4, 0(r5)
308*a47a12beSStefan Roese	mr	r6, r7
309*a47a12beSStefan Roese
310*a47a12beSStefan Roese	mfcr	r7
311*a47a12beSStefan Roese	blrl
312*a47a12beSStefan Roese	mtcr	r7
313*a47a12beSStefan Roese
314*a47a12beSStefan Roese	lwz	r7, 8(r1)
315*a47a12beSStefan Roese	stw	r3, 0(r7)
316*a47a12beSStefan Roese	lwz	r7, 4(r1)
317*a47a12beSStefan Roese	stw	r4, 0(r7)
318*a47a12beSStefan Roese	lwz	r7, 0(r1)
319*a47a12beSStefan Roese	stw	r5, 0(r7)
320*a47a12beSStefan Roese
321*a47a12beSStefan Roese	lwz	r0, 12(r1)
322*a47a12beSStefan Roese	addi	r1, r1, 16
323*a47a12beSStefan Roese	mtlr	r0
324*a47a12beSStefan Roese	blr
325*a47a12beSStefan Roese
326*a47a12beSStefan Roese/* int cpu_post_complex_1_asm (int a1, int a2, int a3, int a4, int n); */
327*a47a12beSStefan Roese	.global	cpu_post_complex_1_asm
328*a47a12beSStefan Roesecpu_post_complex_1_asm:
329*a47a12beSStefan Roese	li	r9,0
330*a47a12beSStefan Roese	cmpw	r9,r7
331*a47a12beSStefan Roese	bge	cpu_post_complex_1_done
332*a47a12beSStefan Roese	mtctr	r7
333*a47a12beSStefan Roesecpu_post_complex_1_loop:
334*a47a12beSStefan Roese	mullw	r0,r3,r4
335*a47a12beSStefan Roese	subf	r0,r5,r0
336*a47a12beSStefan Roese	divw	r0,r0,r6
337*a47a12beSStefan Roese	add	r9,r9,r0
338*a47a12beSStefan Roese	bdnz	cpu_post_complex_1_loop
339*a47a12beSStefan Roesecpu_post_complex_1_done:
340*a47a12beSStefan Roese	mr	r3,r9
341*a47a12beSStefan Roese	blr
342*a47a12beSStefan Roese
343*a47a12beSStefan Roese/* int cpu_post_complex_2_asm (int x, int n); */
344*a47a12beSStefan Roese	.global	cpu_post_complex_2_asm
345*a47a12beSStefan Roesecpu_post_complex_2_asm:
346*a47a12beSStefan Roese	mr.	r0,r4
347*a47a12beSStefan Roese	mtctr	r0
348*a47a12beSStefan Roese	mr	r0,r3
349*a47a12beSStefan Roese	li	r3,1
350*a47a12beSStefan Roese	li	r4,1
351*a47a12beSStefan Roese	blelr
352*a47a12beSStefan Roesecpu_post_complex_2_loop:
353*a47a12beSStefan Roese	mullw	r3,r3,r0
354*a47a12beSStefan Roese	add	r3,r3,r4
355*a47a12beSStefan Roese	bdnz	cpu_post_complex_2_loop
356*a47a12beSStefan Roeseblr
357*a47a12beSStefan Roese
358*a47a12beSStefan Roese#endif
359