1*a47a12beSStefan Roese /* 2*a47a12beSStefan Roese * (C) Copyright 2002 3*a47a12beSStefan Roese * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4*a47a12beSStefan Roese * 5*a47a12beSStefan Roese * See file CREDITS for list of people who contributed to this 6*a47a12beSStefan Roese * project. 7*a47a12beSStefan Roese * 8*a47a12beSStefan Roese * This program is free software; you can redistribute it and/or 9*a47a12beSStefan Roese * modify it under the terms of the GNU General Public License as 10*a47a12beSStefan Roese * published by the Free Software Foundation; either version 2 of 11*a47a12beSStefan Roese * the License, or (at your option) any later version. 12*a47a12beSStefan Roese * 13*a47a12beSStefan Roese * This program is distributed in the hope that it will be useful, 14*a47a12beSStefan Roese * but WITHOUT ANY WARRANTY; without even the implied warranty of 15*a47a12beSStefan Roese * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16*a47a12beSStefan Roese * GNU General Public License for more details. 17*a47a12beSStefan Roese * 18*a47a12beSStefan Roese * You should have received a copy of the GNU General Public License 19*a47a12beSStefan Roese * along with this program; if not, write to the Free Software 20*a47a12beSStefan Roese * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21*a47a12beSStefan Roese * MA 02111-1307 USA 22*a47a12beSStefan Roese */ 23*a47a12beSStefan Roese 24*a47a12beSStefan Roese #include <common.h> 25*a47a12beSStefan Roese 26*a47a12beSStefan Roese /* 27*a47a12beSStefan Roese * CPU test 28*a47a12beSStefan Roese * Logic instructions: andi., andis. 29*a47a12beSStefan Roese * 30*a47a12beSStefan Roese * The test contains a pre-built table of instructions, operands and 31*a47a12beSStefan Roese * expected results. For each table entry, the test will cyclically use 32*a47a12beSStefan Roese * different sets of operand registers and result registers. 33*a47a12beSStefan Roese */ 34*a47a12beSStefan Roese 35*a47a12beSStefan Roese #include <post.h> 36*a47a12beSStefan Roese #include "cpu_asm.h" 37*a47a12beSStefan Roese 38*a47a12beSStefan Roese #if CONFIG_POST & CONFIG_SYS_POST_CPU 39*a47a12beSStefan Roese 40*a47a12beSStefan Roese extern void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op); 41*a47a12beSStefan Roese extern ulong cpu_post_makecr (long v); 42*a47a12beSStefan Roese 43*a47a12beSStefan Roese static struct cpu_post_andi_s 44*a47a12beSStefan Roese { 45*a47a12beSStefan Roese ulong cmd; 46*a47a12beSStefan Roese ulong op1; 47*a47a12beSStefan Roese ushort op2; 48*a47a12beSStefan Roese ulong res; 49*a47a12beSStefan Roese } cpu_post_andi_table[] = 50*a47a12beSStefan Roese { 51*a47a12beSStefan Roese { 52*a47a12beSStefan Roese OP_ANDI_, 53*a47a12beSStefan Roese 0x80008000, 54*a47a12beSStefan Roese 0xffff, 55*a47a12beSStefan Roese 0x00008000 56*a47a12beSStefan Roese }, 57*a47a12beSStefan Roese { 58*a47a12beSStefan Roese OP_ANDIS_, 59*a47a12beSStefan Roese 0x80008000, 60*a47a12beSStefan Roese 0xffff, 61*a47a12beSStefan Roese 0x80000000 62*a47a12beSStefan Roese }, 63*a47a12beSStefan Roese }; 64*a47a12beSStefan Roese static unsigned int cpu_post_andi_size = 65*a47a12beSStefan Roese sizeof (cpu_post_andi_table) / sizeof (struct cpu_post_andi_s); 66*a47a12beSStefan Roese 67*a47a12beSStefan Roese int cpu_post_test_andi (void) 68*a47a12beSStefan Roese { 69*a47a12beSStefan Roese int ret = 0; 70*a47a12beSStefan Roese unsigned int i, reg; 71*a47a12beSStefan Roese int flag = disable_interrupts(); 72*a47a12beSStefan Roese 73*a47a12beSStefan Roese for (i = 0; i < cpu_post_andi_size && ret == 0; i++) 74*a47a12beSStefan Roese { 75*a47a12beSStefan Roese struct cpu_post_andi_s *test = cpu_post_andi_table + i; 76*a47a12beSStefan Roese 77*a47a12beSStefan Roese for (reg = 0; reg < 32 && ret == 0; reg++) 78*a47a12beSStefan Roese { 79*a47a12beSStefan Roese unsigned int reg0 = (reg + 0) % 32; 80*a47a12beSStefan Roese unsigned int reg1 = (reg + 1) % 32; 81*a47a12beSStefan Roese unsigned int stk = reg < 16 ? 31 : 15; 82*a47a12beSStefan Roese unsigned long codecr[] = 83*a47a12beSStefan Roese { 84*a47a12beSStefan Roese ASM_STW(stk, 1, -4), 85*a47a12beSStefan Roese ASM_ADDI(stk, 1, -16), 86*a47a12beSStefan Roese ASM_STW(3, stk, 8), 87*a47a12beSStefan Roese ASM_STW(reg0, stk, 4), 88*a47a12beSStefan Roese ASM_STW(reg1, stk, 0), 89*a47a12beSStefan Roese ASM_LWZ(reg0, stk, 8), 90*a47a12beSStefan Roese ASM_11IX(test->cmd, reg1, reg0, test->op2), 91*a47a12beSStefan Roese ASM_STW(reg1, stk, 8), 92*a47a12beSStefan Roese ASM_LWZ(reg1, stk, 0), 93*a47a12beSStefan Roese ASM_LWZ(reg0, stk, 4), 94*a47a12beSStefan Roese ASM_LWZ(3, stk, 8), 95*a47a12beSStefan Roese ASM_ADDI(1, stk, 16), 96*a47a12beSStefan Roese ASM_LWZ(stk, 1, -4), 97*a47a12beSStefan Roese ASM_BLR, 98*a47a12beSStefan Roese }; 99*a47a12beSStefan Roese ulong res; 100*a47a12beSStefan Roese ulong cr; 101*a47a12beSStefan Roese 102*a47a12beSStefan Roese cpu_post_exec_21 (codecr, & cr, & res, test->op1); 103*a47a12beSStefan Roese 104*a47a12beSStefan Roese ret = res == test->res && 105*a47a12beSStefan Roese (cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1; 106*a47a12beSStefan Roese 107*a47a12beSStefan Roese if (ret != 0) 108*a47a12beSStefan Roese { 109*a47a12beSStefan Roese post_log ("Error at andi test %d !\n", i); 110*a47a12beSStefan Roese } 111*a47a12beSStefan Roese } 112*a47a12beSStefan Roese } 113*a47a12beSStefan Roese 114*a47a12beSStefan Roese if (flag) 115*a47a12beSStefan Roese enable_interrupts(); 116*a47a12beSStefan Roese 117*a47a12beSStefan Roese return ret; 118*a47a12beSStefan Roese } 119*a47a12beSStefan Roese 120*a47a12beSStefan Roese #endif 121