1a47a12beSStefan Roese /* 2a47a12beSStefan Roese * (C) Copyright 2002 3a47a12beSStefan Roese * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4a47a12beSStefan Roese * 5*1a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 6a47a12beSStefan Roese */ 7a47a12beSStefan Roese 8a47a12beSStefan Roese #include <common.h> 9a47a12beSStefan Roese 10a47a12beSStefan Roese /* 11a47a12beSStefan Roese * CPU test 12a47a12beSStefan Roese * Logic instructions: andi., andis. 13a47a12beSStefan Roese * 14a47a12beSStefan Roese * The test contains a pre-built table of instructions, operands and 15a47a12beSStefan Roese * expected results. For each table entry, the test will cyclically use 16a47a12beSStefan Roese * different sets of operand registers and result registers. 17a47a12beSStefan Roese */ 18a47a12beSStefan Roese 19a47a12beSStefan Roese #include <post.h> 20a47a12beSStefan Roese #include "cpu_asm.h" 21a47a12beSStefan Roese 22a47a12beSStefan Roese #if CONFIG_POST & CONFIG_SYS_POST_CPU 23a47a12beSStefan Roese 24a47a12beSStefan Roese extern void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op); 25a47a12beSStefan Roese extern ulong cpu_post_makecr (long v); 26a47a12beSStefan Roese 27a47a12beSStefan Roese static struct cpu_post_andi_s 28a47a12beSStefan Roese { 29a47a12beSStefan Roese ulong cmd; 30a47a12beSStefan Roese ulong op1; 31a47a12beSStefan Roese ushort op2; 32a47a12beSStefan Roese ulong res; 33a47a12beSStefan Roese } cpu_post_andi_table[] = 34a47a12beSStefan Roese { 35a47a12beSStefan Roese { 36a47a12beSStefan Roese OP_ANDI_, 37a47a12beSStefan Roese 0x80008000, 38a47a12beSStefan Roese 0xffff, 39a47a12beSStefan Roese 0x00008000 40a47a12beSStefan Roese }, 41a47a12beSStefan Roese { 42a47a12beSStefan Roese OP_ANDIS_, 43a47a12beSStefan Roese 0x80008000, 44a47a12beSStefan Roese 0xffff, 45a47a12beSStefan Roese 0x80000000 46a47a12beSStefan Roese }, 47a47a12beSStefan Roese }; 48d2397817SMike Frysinger static unsigned int cpu_post_andi_size = ARRAY_SIZE(cpu_post_andi_table); 49a47a12beSStefan Roese 50a47a12beSStefan Roese int cpu_post_test_andi (void) 51a47a12beSStefan Roese { 52a47a12beSStefan Roese int ret = 0; 53a47a12beSStefan Roese unsigned int i, reg; 54a47a12beSStefan Roese int flag = disable_interrupts(); 55a47a12beSStefan Roese 56a47a12beSStefan Roese for (i = 0; i < cpu_post_andi_size && ret == 0; i++) 57a47a12beSStefan Roese { 58a47a12beSStefan Roese struct cpu_post_andi_s *test = cpu_post_andi_table + i; 59a47a12beSStefan Roese 60a47a12beSStefan Roese for (reg = 0; reg < 32 && ret == 0; reg++) 61a47a12beSStefan Roese { 62a47a12beSStefan Roese unsigned int reg0 = (reg + 0) % 32; 63a47a12beSStefan Roese unsigned int reg1 = (reg + 1) % 32; 64a47a12beSStefan Roese unsigned int stk = reg < 16 ? 31 : 15; 65a47a12beSStefan Roese unsigned long codecr[] = 66a47a12beSStefan Roese { 67a47a12beSStefan Roese ASM_STW(stk, 1, -4), 68a47a12beSStefan Roese ASM_ADDI(stk, 1, -16), 69a47a12beSStefan Roese ASM_STW(3, stk, 8), 70a47a12beSStefan Roese ASM_STW(reg0, stk, 4), 71a47a12beSStefan Roese ASM_STW(reg1, stk, 0), 72a47a12beSStefan Roese ASM_LWZ(reg0, stk, 8), 73a47a12beSStefan Roese ASM_11IX(test->cmd, reg1, reg0, test->op2), 74a47a12beSStefan Roese ASM_STW(reg1, stk, 8), 75a47a12beSStefan Roese ASM_LWZ(reg1, stk, 0), 76a47a12beSStefan Roese ASM_LWZ(reg0, stk, 4), 77a47a12beSStefan Roese ASM_LWZ(3, stk, 8), 78a47a12beSStefan Roese ASM_ADDI(1, stk, 16), 79a47a12beSStefan Roese ASM_LWZ(stk, 1, -4), 80a47a12beSStefan Roese ASM_BLR, 81a47a12beSStefan Roese }; 82a47a12beSStefan Roese ulong res; 83a47a12beSStefan Roese ulong cr; 84a47a12beSStefan Roese 85a47a12beSStefan Roese cpu_post_exec_21 (codecr, & cr, & res, test->op1); 86a47a12beSStefan Roese 87a47a12beSStefan Roese ret = res == test->res && 88a47a12beSStefan Roese (cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1; 89a47a12beSStefan Roese 90a47a12beSStefan Roese if (ret != 0) 91a47a12beSStefan Roese { 92a47a12beSStefan Roese post_log ("Error at andi test %d !\n", i); 93a47a12beSStefan Roese } 94a47a12beSStefan Roese } 95a47a12beSStefan Roese } 96a47a12beSStefan Roese 97a47a12beSStefan Roese if (flag) 98a47a12beSStefan Roese enable_interrupts(); 99a47a12beSStefan Roese 100a47a12beSStefan Roese return ret; 101a47a12beSStefan Roese } 102a47a12beSStefan Roese 103a47a12beSStefan Roese #endif 104