1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd 4 */ 5 6 #include <common.h> 7 #include <lmb.h> 8 #include <bidram.h> 9 #include <malloc.h> 10 #include <sysmem.h> 11 #include <asm/io.h> 12 #include <asm/arch/rk_atags.h> 13 14 DECLARE_GLOBAL_DATA_PTR; 15 16 #define MAX_BAD_MEMBLK 8 17 18 #define BIDRAM_R(fmt, args...) printf(fmt, ##args) 19 #define BIDRAM_I(fmt, args...) printf("Bidram: "fmt, ##args) 20 #define BIDRAM_W(fmt, args...) printf("Bidram Warn: "fmt, ##args) 21 #define BIDRAM_E(fmt, args...) printf("Bidram Error: "fmt, ##args) 22 #define BIDRAM_D(fmt, args...) debug("Bidram Debug: "fmt, ##args) 23 24 struct bidram plat_bidram __section(".data") = { .has_init = false, }; 25 26 static int bidram_has_init(void) 27 { 28 if (!plat_bidram.has_init) { 29 BIDRAM_E("Framework is not initialized\n"); 30 return 0; 31 } 32 33 return 1; 34 } 35 36 void bidram_dump(void) 37 { 38 struct bidram *bidram = &plat_bidram; 39 struct lmb *lmb = &bidram->lmb; 40 struct memblock *mem; 41 struct list_head *node; 42 ulong memory_size = 0; 43 ulong reserved_size = 0; 44 ulong i; 45 46 if (!bidram_has_init()) 47 return; 48 49 printf("\n\nbidram_dump_all:\n"); 50 51 /* Memory pool */ 52 printf(" --------------------------------------------------------------------\n"); 53 for (i = 0; i < lmb->memory.cnt; i++) { 54 memory_size += lmb->memory.region[i].size; 55 printf(" memory.rgn[%ld].addr = 0x%08lx - 0x%08lx (size: 0x%08lx)\n", i, 56 (ulong)lmb->memory.region[i].base, 57 (ulong)lmb->memory.region[i].base + 58 (ulong)lmb->memory.region[i].size, 59 (ulong)lmb->memory.region[i].size); 60 } 61 printf("\n memory.total = 0x%08lx (%ld MiB. %ld KiB)\n", 62 (ulong)memory_size, 63 SIZE_MB((ulong)memory_size), 64 SIZE_KB((ulong)memory_size)); 65 66 /* Reserved */ 67 i = 0; 68 printf(" --------------------------------------------------------------------\n"); 69 list_for_each(node, &bidram->reserved_head) { 70 mem = list_entry(node, struct memblock, node); 71 reserved_size += mem->size; 72 printf(" reserved.rgn[%ld].name = \"%s\"\n", i, mem->attr.name); 73 printf(" .addr = 0x%08lx - 0x%08lx (size: 0x%08lx)\n", 74 (ulong)mem->base, (ulong)mem->base + (ulong)mem->size, 75 (ulong)mem->size); 76 i++; 77 } 78 printf("\n reserved.total = 0x%08lx (%ld MiB. %ld KiB)\n", 79 (ulong)reserved_size, 80 SIZE_MB((ulong)reserved_size), 81 SIZE_KB((ulong)reserved_size)); 82 83 /* LMB core reserved */ 84 printf(" --------------------------------------------------------------------\n"); 85 reserved_size = 0; 86 for (i = 0; i < lmb->reserved.cnt; i++) { 87 reserved_size += lmb->reserved.region[i].size; 88 printf(" LMB.reserved[%ld].addr = 0x%08lx - 0x%08lx (size: 0x%08lx)\n", i, 89 (ulong)lmb->reserved.region[i].base, 90 (ulong)lmb->reserved.region[i].base + 91 (ulong)lmb->reserved.region[i].size, 92 (ulong)lmb->reserved.region[i].size); 93 } 94 95 printf("\n reserved.core.total = 0x%08lx (%ld MiB. %ld KiB)\n", 96 (ulong)reserved_size, 97 SIZE_MB((ulong)reserved_size), 98 SIZE_KB((ulong)reserved_size)); 99 printf(" --------------------------------------------------------------------\n\n"); 100 } 101 102 static int bidram_add(phys_addr_t base, phys_size_t size) 103 { 104 struct bidram *bidram = &plat_bidram; 105 int ret; 106 107 if (!bidram_has_init()) 108 return -ENOSYS; 109 110 if (!size) 111 return -EINVAL; 112 113 ret = lmb_add(&bidram->lmb, base, size); 114 if (ret < 0) 115 BIDRAM_E("Failed to add bidram at 0x%08lx - 0x%08lx\n", 116 (ulong)base, (ulong)(base + size)); 117 118 return (ret >= 0) ? 0 : ret; 119 } 120 121 void bidram_gen_gd_bi_dram(void) 122 { 123 struct bidram *bidram = &plat_bidram; 124 struct lmb *lmb = &plat_bidram.lmb; 125 struct lmb_property *mem_rgn = lmb->memory.region; 126 struct lmb_property *res_rgn = lmb->reserved.region; 127 int rsv_cnt = lmb->reserved.cnt; 128 int i, idx = 0; 129 130 if (!gd || !gd->bd) { 131 BIDRAM_D("Ignore bi dram bank update\n"); 132 return; 133 } 134 135 /* 136 * LBM default init: 137 * lmb->reserved.cnt = 1; 138 * lmb->reserved.region[0].base = 0; 139 * lmb->reserved.region[0].size = 0; 140 * 141 * Here handle that: there is the only one dram bank available. 142 */ 143 if (rsv_cnt == 1 && !res_rgn[0].base && !res_rgn[0].size) { 144 gd->bd->bi_dram[idx].start = mem_rgn[0].base; 145 gd->bd->bi_dram[idx].size = mem_rgn[0].size; 146 idx++; 147 goto done; 148 } 149 150 /* If reserved rgn is not from sdram start */ 151 if (res_rgn[0].base != mem_rgn[0].base) { 152 gd->bd->bi_dram[idx].start = mem_rgn[0].base; 153 gd->bd->bi_dram[idx].size = res_rgn[0].base - 154 gd->bd->bi_dram[idx].start; 155 idx++; 156 } 157 158 /* 159 * Note: If reserved rgn is not from sdram start, idx=1 now, otherwise 0. 160 */ 161 for (i = 0; i < rsv_cnt; i++, idx++) { 162 if (res_rgn[i].base + res_rgn[i].size >= gd->ram_top) 163 goto done; 164 165 gd->bd->bi_dram[idx].start = res_rgn[i].base + res_rgn[i].size; 166 if (i + 1 < rsv_cnt) 167 gd->bd->bi_dram[idx].size = res_rgn[i + 1].base - 168 gd->bd->bi_dram[idx].start; 169 else 170 gd->bd->bi_dram[idx].size = gd->ram_top - 171 gd->bd->bi_dram[idx].start; 172 } 173 done: 174 /* Append 4GB+ memory blocks and extend ram top */ 175 if (bidram->fixup) { 176 /* extend ram top */ 177 if (gd->ram_top_ext_size) { 178 int pos = idx - 1; 179 ulong top; 180 181 if (gd->bd->bi_dram[pos].start + 182 gd->bd->bi_dram[pos].size == gd->ram_top) { 183 top = gd->bd->bi_dram[pos].start + gd->bd->bi_dram[pos].size; 184 gd->bd->bi_dram[pos].size += gd->ram_top_ext_size; 185 printf("Extend top: 0x%08lx -> 0x%08lx\n", 186 top, top + (ulong)gd->ram_top_ext_size); 187 } 188 } 189 190 /* append 4GB+ */ 191 for (i = 0; i < MEM_RESV_COUNT; i++) { 192 if (!bidram->size_u64[i]) 193 continue; 194 gd->bd->bi_dram[idx].start = bidram->base_u64[i]; 195 gd->bd->bi_dram[idx].size = bidram->size_u64[i]; 196 BIDRAM_D("FIXUP: gd->bi_dram[%d]: start=0x%llx, size=0x%llx\n", 197 idx, bidram->base_u64[i], bidram->size_u64[i]); 198 idx++; 199 } 200 } 201 202 for (i = 0; i < idx; i++) { 203 BIDRAM_D("GEN: gd->bi_dram[%d]: start=0x%llx, end=0x%llx\n", 204 i, (u64)gd->bd->bi_dram[i].start, 205 (u64)gd->bd->bi_dram[i].start + 206 (u64)gd->bd->bi_dram[i].size); 207 } 208 } 209 210 int bidram_fixup(void) 211 { 212 struct bidram *bidram = &plat_bidram; 213 214 bidram->fixup = true; 215 bidram_gen_gd_bi_dram(); 216 217 return 0; 218 } 219 220 u64 bidram_append_size(void) 221 { 222 struct bidram *bidram = &plat_bidram; 223 u64 size = 0; 224 int i; 225 226 /* 4GB+ */ 227 for (i = 0; i < MEM_RESV_COUNT; i++) 228 size += bidram->size_u64[i]; 229 230 if (gd->ram_top_ext_size) 231 size += gd->ram_top_ext_size; 232 233 return size; 234 } 235 236 static int bidram_is_overlap(phys_addr_t base1, phys_size_t size1, 237 phys_addr_t base2, phys_size_t size2) 238 { 239 return ((base1 < (base2 + size2)) && (base2 < (base1 + size1))); 240 } 241 242 struct memblock *bidram_reserved_is_overlap(phys_addr_t base, phys_size_t size) 243 { 244 struct bidram *bidram = &plat_bidram; 245 struct list_head *node; 246 struct memblock *mem; 247 248 if (!bidram_has_init()) 249 return false; 250 251 list_for_each(node, &bidram->reserved_head) { 252 mem = list_entry(node, struct memblock, node); 253 if (bidram_is_overlap(mem->base, mem->size, base, size)) 254 return mem; 255 } 256 257 return NULL; 258 } 259 260 static int bidram_core_reserve(enum memblk_id id, const char *mem_name, 261 phys_addr_t base, phys_size_t size) 262 { 263 struct bidram *bidram = &plat_bidram; 264 struct memblk_attr attr; 265 struct memblock *mem; 266 struct list_head *node; 267 const char *name; 268 int ret; 269 270 if (!bidram_has_init()) 271 return -ENOSYS; 272 273 if (id == MEM_BY_NAME) { 274 if (!mem_name) { 275 BIDRAM_E("NULL name for reserve bidram\n"); 276 return -EINVAL; 277 } else { 278 name = mem_name; 279 } 280 } else { 281 if (id > MEM_UNK && id < MEM_MAX) { 282 attr = mem_attr[id]; 283 name = attr.name; 284 } else { 285 BIDRAM_E("Unsupport memblk id %d for reserve bidram\n", id); 286 return -EINVAL; 287 } 288 } 289 290 if (!name) { 291 BIDRAM_E("NULL name for reserved bidram\n"); 292 return -EINVAL; 293 } 294 295 if (!size) 296 return 0; 297 298 /* Check overlap */ 299 list_for_each(node, &bidram->reserved_head) { 300 mem = list_entry(node, struct memblock, node); 301 BIDRAM_D("Has reserved: %s 0x%08lx - 0x%08lx\n", 302 mem->attr.name, (ulong)mem->base, 303 (ulong)(mem->base + mem->size)); 304 if (!strcmp(mem->attr.name, name)) { 305 BIDRAM_E("Failed to double reserve for existence \"%s\"\n", name); 306 return -EEXIST; 307 } else if (bidram_is_overlap(mem->base, mem->size, base, size)) { 308 BIDRAM_D("\"%s\" (0x%08lx - 0x%08lx) reserve is " 309 "overlap with existence \"%s\" (0x%08lx - " 310 "0x%08lx)\n", 311 name, (ulong)base, (ulong)(base + size), mem->attr.name, 312 (ulong)mem->base, (ulong)(mem->base + mem->size)); 313 } 314 } 315 316 BIDRAM_D("Reserve: \"%s\" 0x%08lx - 0x%08lx\n", 317 name, (ulong)base, (ulong)(base + size)); 318 319 ret = lmb_reserve(&bidram->lmb, base, size); 320 if (ret >= 0) { 321 mem = malloc(sizeof(*mem)); 322 if (!mem) { 323 BIDRAM_E("No memory for \"%s\" reserve bidram\n", name); 324 return -ENOMEM; 325 } 326 327 #ifdef CONFIG_SYSMEM 328 /* Sync to sysmem */ 329 if (sysmem_has_init()) { 330 void *paddr; 331 332 if (id == MEM_BY_NAME) 333 paddr = sysmem_alloc_base_by_name(name, base, size); 334 else 335 paddr = sysmem_alloc_base(id, base, size); 336 if (!paddr) { 337 BIDRAM_E("Sync \"%s\" to sysmem failed\n", name); 338 return -ENOMEM; 339 } 340 } 341 #endif 342 mem->base = base; 343 mem->size = size; 344 if (id == MEM_BY_NAME) { 345 mem->attr.name = name; 346 mem->attr.flags = 0; 347 } else { 348 mem->attr = attr; 349 } 350 list_add_tail(&mem->node, &bidram->reserved_head); 351 } else { 352 BIDRAM_E("Failed to reserve \"%s\" 0x%08lx - 0x%08lx\n", 353 name, (ulong)base, (ulong)(base + size)); 354 return -EINVAL; 355 } 356 357 return 0; 358 } 359 360 int bidram_reserve(enum memblk_id id, phys_addr_t base, phys_size_t size) 361 { 362 int ret; 363 364 ret = bidram_core_reserve(id, NULL, base, size); 365 if (!ret) 366 bidram_gen_gd_bi_dram(); 367 else 368 bidram_dump(); 369 370 return ret; 371 } 372 373 int bidram_reserve_by_name(const char *name, 374 phys_addr_t base, phys_size_t size) 375 { 376 int ret; 377 378 ret = bidram_core_reserve(MEM_BY_NAME, name, base, size); 379 if (!ret) 380 bidram_gen_gd_bi_dram(); 381 else 382 bidram_dump(); 383 384 return ret; 385 } 386 387 int bidram_initr(void) 388 { 389 return !bidram_get_ram_size(); 390 } 391 392 phys_size_t bidram_get_ram_size(void) 393 { 394 struct bidram *bidram = &plat_bidram; 395 struct memblock bad[MAX_BAD_MEMBLK]; 396 struct memblock *list; 397 phys_size_t ram_addr_end = CONFIG_SYS_SDRAM_BASE; 398 phys_addr_t end_addr; 399 parse_fn_t parse_fn; 400 int i, count, ret; 401 int bad_cnt = 0, n = 0; 402 char bad_name[12]; 403 404 parse_fn = board_bidram_parse_fn(); 405 if (!parse_fn) { 406 BIDRAM_E("Can't find dram parse fn\n"); 407 return 0; 408 } 409 410 list = parse_fn(&count); 411 if (!list) { 412 BIDRAM_E("Can't get dram banks\n"); 413 return 0; 414 } 415 416 if (count > CONFIG_NR_DRAM_BANKS) { 417 BIDRAM_E("Too many dram banks, %d is over max: %d\n", 418 count, CONFIG_NR_DRAM_BANKS); 419 return 0; 420 } 421 422 /* Initial plat_bidram */ 423 lmb_init(&bidram->lmb); 424 INIT_LIST_HEAD(&bidram->reserved_head); 425 bidram->has_init = true; 426 427 /* Initial memory pool */ 428 for (i = 0; i < count; i++) { 429 BIDRAM_D("Add bank[%d] start=0x%08lx, end=0x%08lx\n", 430 i, (ulong)list[i].base, 431 (ulong)list[i].base + (ulong)list[i].size); 432 433 if (!list[i].size) { 434 /* handle 4GB+ */ 435 if (list[i].size_u64 && n < MEM_RESV_COUNT) { 436 bidram->base_u64[n] = list[i].base_u64; 437 bidram->size_u64[n] = list[i].size_u64; 438 n++; 439 } 440 continue; 441 } 442 443 /* We assume the last block gives the ram addr end */ 444 ram_addr_end = list[i].base + list[i].size; 445 446 /* This is a bad dram bank? record it */ 447 if (i > 0) { 448 end_addr = list[i - 1].base + list[i - 1].size; 449 450 if (list[i].base != end_addr) { 451 snprintf(bad_name, 12, "%s%d", "BAD_RAM.", i - 1); 452 bad[bad_cnt].attr.name = strdup(bad_name); 453 bad[bad_cnt].base = end_addr; 454 bad[bad_cnt].size = list[i].base - end_addr; 455 bad_cnt++; 456 if (bad_cnt > MAX_BAD_MEMBLK) { 457 BIDRAM_E("Too many bad memory blocks\n"); 458 return 0; 459 } 460 } 461 } 462 } 463 464 ret = bidram_add(CONFIG_SYS_SDRAM_BASE, 465 ram_addr_end - CONFIG_SYS_SDRAM_BASE); 466 if (ret) { 467 BIDRAM_E("Failed to add bidram from bi_dram[%d]\n", i); 468 return 0; 469 } 470 471 /* Reserve bad dram bank after bidram_add(), treat as reserved region */ 472 for (i = 0; i < bad_cnt; i++) { 473 if (gd->flags & GD_FLG_RELOC) 474 BIDRAM_R("Bad memblk%d: 0x%08lx - 0x%08lx\n", 475 i, (ulong)bad[i].base, 476 (ulong)bad[i].base + (ulong)bad[i].size); 477 478 ret = bidram_reserve_by_name(bad[i].attr.name, 479 bad[i].base, bad[i].size); 480 if (ret) { 481 BIDRAM_E("Failed to add bad memblk[%d]\n", i); 482 return 0; 483 } 484 } 485 486 /* Reserved for board */ 487 ret = board_bidram_reserve(bidram); 488 if (ret) { 489 BIDRAM_E("Failed to reserve bidram for board\n"); 490 return 0; 491 } 492 493 BIDRAM_D("DRAM size: 0x%08lx\n", 494 (ulong)ram_addr_end - CONFIG_SYS_SDRAM_BASE); 495 496 #ifdef DEBUG 497 bidram_dump(); 498 #endif 499 500 return (ram_addr_end - CONFIG_SYS_SDRAM_BASE); 501 } 502 503 __weak parse_fn_t board_bidram_parse_fn(void) 504 { 505 /* please define platform specific board_bidram_parse_fn() */ 506 return NULL; 507 } 508 509 __weak int board_bidram_reserve(struct bidram *bidram) 510 { 511 /* please define platform specific board_bidram_reserve() */ 512 return 0; 513 } 514 515 static int do_bidram_dump(cmd_tbl_t *cmdtp, int flag, 516 int argc, char *const argv[]) 517 { 518 bidram_dump(); 519 return 0; 520 } 521 522 U_BOOT_CMD( 523 bidram_dump, 1, 1, do_bidram_dump, 524 "Dump bidram layout", 525 "" 526 ); 527