1d5dae85fSMichal Simek /* 2d5dae85fSMichal Simek * (C) Copyright 2012-2013, Xilinx, Michal Simek 3d5dae85fSMichal Simek * 4d5dae85fSMichal Simek * (C) Copyright 2012 5d5dae85fSMichal Simek * Joe Hershberger <joe.hershberger@ni.com> 6d5dae85fSMichal Simek * 71a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 8d5dae85fSMichal Simek */ 9d5dae85fSMichal Simek 10d5dae85fSMichal Simek #ifndef _ZYNQPL_H_ 11d5dae85fSMichal Simek #define _ZYNQPL_H_ 12d5dae85fSMichal Simek 13d5dae85fSMichal Simek #include <xilinx.h> 14d5dae85fSMichal Simek 15345f9e19SMichal Simek #if defined(CONFIG_FPGA_ZYNQPL) 1614cfc4f3SMichal Simek extern struct xilinx_fpga_op zynq_op; 17345f9e19SMichal Simek # define FPGA_ZYNQPL_OPS &zynq_op 18345f9e19SMichal Simek #else 19345f9e19SMichal Simek # define FPGA_ZYNQPL_OPS NULL 20345f9e19SMichal Simek #endif 21d5dae85fSMichal Simek 22d5dae85fSMichal Simek #define XILINX_ZYNQ_7010 0x2 2331993d6aSMichal Simek #define XILINX_ZYNQ_7015 0x1b 24d5dae85fSMichal Simek #define XILINX_ZYNQ_7020 0x7 25d5dae85fSMichal Simek #define XILINX_ZYNQ_7030 0xc 26*b9103809SSiva Durga Prasad Paladugu #define XILINX_ZYNQ_7035 0x12 27d5dae85fSMichal Simek #define XILINX_ZYNQ_7045 0x11 28fd2b10b6SMichal Simek #define XILINX_ZYNQ_7100 0x16 29d5dae85fSMichal Simek 30d5dae85fSMichal Simek /* Device Image Sizes */ 31d5dae85fSMichal Simek #define XILINX_XC7Z010_SIZE 16669920/8 3231993d6aSMichal Simek #define XILINX_XC7Z015_SIZE 28085344/8 33d5dae85fSMichal Simek #define XILINX_XC7Z020_SIZE 32364512/8 34d5dae85fSMichal Simek #define XILINX_XC7Z030_SIZE 47839328/8 35*b9103809SSiva Durga Prasad Paladugu #define XILINX_XC7Z035_SIZE 106571232/8 36d5dae85fSMichal Simek #define XILINX_XC7Z045_SIZE 106571232/8 37fd2b10b6SMichal Simek #define XILINX_XC7Z100_SIZE 139330784/8 38d5dae85fSMichal Simek 39d5dae85fSMichal Simek /* Descriptor Macros */ 40d5dae85fSMichal Simek #define XILINX_XC7Z010_DESC(cookie) \ 41345f9e19SMichal Simek { xilinx_zynq, devcfg, XILINX_XC7Z010_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \ 42345f9e19SMichal Simek "7z010" } 43d5dae85fSMichal Simek 4431993d6aSMichal Simek #define XILINX_XC7Z015_DESC(cookie) \ 45345f9e19SMichal Simek { xilinx_zynq, devcfg, XILINX_XC7Z015_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \ 46345f9e19SMichal Simek "7z015" } 4731993d6aSMichal Simek 48d5dae85fSMichal Simek #define XILINX_XC7Z020_DESC(cookie) \ 49345f9e19SMichal Simek { xilinx_zynq, devcfg, XILINX_XC7Z020_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \ 50345f9e19SMichal Simek "7z020" } 51d5dae85fSMichal Simek 52d5dae85fSMichal Simek #define XILINX_XC7Z030_DESC(cookie) \ 53345f9e19SMichal Simek { xilinx_zynq, devcfg, XILINX_XC7Z030_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \ 54345f9e19SMichal Simek "7z030" } 55d5dae85fSMichal Simek 56*b9103809SSiva Durga Prasad Paladugu #define XILINX_XC7Z035_DESC(cookie) \ 57*b9103809SSiva Durga Prasad Paladugu { xilinx_zynq, devcfg, XILINX_XC7Z035_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \ 58*b9103809SSiva Durga Prasad Paladugu "7z035" } 59*b9103809SSiva Durga Prasad Paladugu 60d5dae85fSMichal Simek #define XILINX_XC7Z045_DESC(cookie) \ 61345f9e19SMichal Simek { xilinx_zynq, devcfg, XILINX_XC7Z045_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \ 62345f9e19SMichal Simek "7z045" } 63d5dae85fSMichal Simek 64fd2b10b6SMichal Simek #define XILINX_XC7Z100_DESC(cookie) \ 65345f9e19SMichal Simek { xilinx_zynq, devcfg, XILINX_XC7Z100_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \ 66345f9e19SMichal Simek "7z100" } 67fd2b10b6SMichal Simek 68d5dae85fSMichal Simek #endif /* _ZYNQPL_H_ */ 69