1d5dae85fSMichal Simek /* 2d5dae85fSMichal Simek * (C) Copyright 2012-2013, Xilinx, Michal Simek 3d5dae85fSMichal Simek * 4d5dae85fSMichal Simek * (C) Copyright 2012 5d5dae85fSMichal Simek * Joe Hershberger <joe.hershberger@ni.com> 6d5dae85fSMichal Simek * 71a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 8d5dae85fSMichal Simek */ 9d5dae85fSMichal Simek 10d5dae85fSMichal Simek #ifndef _ZYNQPL_H_ 11d5dae85fSMichal Simek #define _ZYNQPL_H_ 12d5dae85fSMichal Simek 13d5dae85fSMichal Simek #include <xilinx.h> 14d5dae85fSMichal Simek 15*345f9e19SMichal Simek #if defined(CONFIG_FPGA_ZYNQPL) 1614cfc4f3SMichal Simek extern struct xilinx_fpga_op zynq_op; 17*345f9e19SMichal Simek # define FPGA_ZYNQPL_OPS &zynq_op 18*345f9e19SMichal Simek #else 19*345f9e19SMichal Simek # define FPGA_ZYNQPL_OPS NULL 20*345f9e19SMichal Simek #endif 21d5dae85fSMichal Simek 22d5dae85fSMichal Simek #define XILINX_ZYNQ_7010 0x2 2331993d6aSMichal Simek #define XILINX_ZYNQ_7015 0x1b 24d5dae85fSMichal Simek #define XILINX_ZYNQ_7020 0x7 25d5dae85fSMichal Simek #define XILINX_ZYNQ_7030 0xc 26d5dae85fSMichal Simek #define XILINX_ZYNQ_7045 0x11 27fd2b10b6SMichal Simek #define XILINX_ZYNQ_7100 0x16 28d5dae85fSMichal Simek 29d5dae85fSMichal Simek /* Device Image Sizes */ 30d5dae85fSMichal Simek #define XILINX_XC7Z010_SIZE 16669920/8 3131993d6aSMichal Simek #define XILINX_XC7Z015_SIZE 28085344/8 32d5dae85fSMichal Simek #define XILINX_XC7Z020_SIZE 32364512/8 33d5dae85fSMichal Simek #define XILINX_XC7Z030_SIZE 47839328/8 34d5dae85fSMichal Simek #define XILINX_XC7Z045_SIZE 106571232/8 35fd2b10b6SMichal Simek #define XILINX_XC7Z100_SIZE 139330784/8 36d5dae85fSMichal Simek 37d5dae85fSMichal Simek /* Descriptor Macros */ 38d5dae85fSMichal Simek #define XILINX_XC7Z010_DESC(cookie) \ 39*345f9e19SMichal Simek { xilinx_zynq, devcfg, XILINX_XC7Z010_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \ 40*345f9e19SMichal Simek "7z010" } 41d5dae85fSMichal Simek 4231993d6aSMichal Simek #define XILINX_XC7Z015_DESC(cookie) \ 43*345f9e19SMichal Simek { xilinx_zynq, devcfg, XILINX_XC7Z015_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \ 44*345f9e19SMichal Simek "7z015" } 4531993d6aSMichal Simek 46d5dae85fSMichal Simek #define XILINX_XC7Z020_DESC(cookie) \ 47*345f9e19SMichal Simek { xilinx_zynq, devcfg, XILINX_XC7Z020_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \ 48*345f9e19SMichal Simek "7z020" } 49d5dae85fSMichal Simek 50d5dae85fSMichal Simek #define XILINX_XC7Z030_DESC(cookie) \ 51*345f9e19SMichal Simek { xilinx_zynq, devcfg, XILINX_XC7Z030_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \ 52*345f9e19SMichal Simek "7z030" } 53d5dae85fSMichal Simek 54d5dae85fSMichal Simek #define XILINX_XC7Z045_DESC(cookie) \ 55*345f9e19SMichal Simek { xilinx_zynq, devcfg, XILINX_XC7Z045_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \ 56*345f9e19SMichal Simek "7z045" } 57d5dae85fSMichal Simek 58fd2b10b6SMichal Simek #define XILINX_XC7Z100_DESC(cookie) \ 59*345f9e19SMichal Simek { xilinx_zynq, devcfg, XILINX_XC7Z100_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \ 60*345f9e19SMichal Simek "7z100" } 61fd2b10b6SMichal Simek 62d5dae85fSMichal Simek #endif /* _ZYNQPL_H_ */ 63