1c609719bSwdenk /* 2c609719bSwdenk * (C) Copyright 2002 3c609719bSwdenk * Rich Ireland, Enterasys Networks, rireland@enterasys.com. 4c609719bSwdenk * 51a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 6c609719bSwdenk */ 7c609719bSwdenk 8c609719bSwdenk #include <fpga.h> 9c609719bSwdenk 10c609719bSwdenk #ifndef _XILINX_H_ 11c609719bSwdenk #define _XILINX_H_ 12c609719bSwdenk 13c609719bSwdenk /* Xilinx types 14c609719bSwdenk *********************************************************************/ 15c609719bSwdenk typedef enum { /* typedef Xilinx_iface */ 16c609719bSwdenk min_xilinx_iface_type, /* low range check value */ 17c609719bSwdenk slave_serial, /* serial data and external clock */ 18c609719bSwdenk master_serial, /* serial data w/ internal clock (not used) */ 19c609719bSwdenk slave_parallel, /* parallel data w/ external latch */ 20c609719bSwdenk jtag_mode, /* jtag/tap serial (not used ) */ 21c609719bSwdenk master_selectmap, /* master SelectMap (virtex2) */ 22c609719bSwdenk slave_selectmap, /* slave SelectMap (virtex2) */ 23d5dae85fSMichal Simek devcfg, /* devcfg interface (zynq) */ 24c609719bSwdenk max_xilinx_iface_type /* insert all new types before this */ 25c609719bSwdenk } Xilinx_iface; /* end, typedef Xilinx_iface */ 26c609719bSwdenk 27c609719bSwdenk typedef enum { /* typedef Xilinx_Family */ 28c609719bSwdenk min_xilinx_type, /* low range check value */ 29b625b9aeSMichal Simek xilinx_spartan2, /* Spartan-II Family */ 30c609719bSwdenk Xilinx_VirtexE, /* Virtex-E Family */ 31*d9071ce0SMichal Simek xilinx_virtex2, /* Virtex2 Family */ 322a6e3869SMichal Simek xilinx_spartan3, /* Spartan-III Family */ 33d5dae85fSMichal Simek xilinx_zynq, /* Zynq Family */ 34c609719bSwdenk max_xilinx_type /* insert all new types before this */ 35c609719bSwdenk } Xilinx_Family; /* end, typedef Xilinx_Family */ 36c609719bSwdenk 37c609719bSwdenk typedef struct { /* typedef Xilinx_desc */ 38c609719bSwdenk Xilinx_Family family; /* part type */ 39c609719bSwdenk Xilinx_iface iface; /* interface type */ 40c609719bSwdenk size_t size; /* bytes of data part can accept */ 41c609719bSwdenk void *iface_fns; /* interface function table */ 42c609719bSwdenk int cookie; /* implementation specific cookie */ 436631db47SMichal Simek char *name; /* device name in bitstream */ 44c609719bSwdenk } Xilinx_desc; /* end, typedef Xilinx_desc */ 45c609719bSwdenk 46c609719bSwdenk /* Generic Xilinx Functions 47c609719bSwdenk *********************************************************************/ 48e6a857daSWolfgang Denk extern int xilinx_load(Xilinx_desc *desc, const void *image, size_t size); 49e6a857daSWolfgang Denk extern int xilinx_dump(Xilinx_desc *desc, const void *buf, size_t bsize); 50c609719bSwdenk extern int xilinx_info(Xilinx_desc *desc); 51c609719bSwdenk 52c609719bSwdenk /* Board specific implementation specific function types 53c609719bSwdenk *********************************************************************/ 54c609719bSwdenk typedef int (*Xilinx_pgm_fn)( int assert_pgm, int flush, int cookie ); 55c609719bSwdenk typedef int (*Xilinx_init_fn)( int cookie ); 56c609719bSwdenk typedef int (*Xilinx_err_fn)( int cookie ); 57c609719bSwdenk typedef int (*Xilinx_done_fn)( int cookie ); 58c609719bSwdenk typedef int (*Xilinx_clk_fn)( int assert_clk, int flush, int cookie ); 59c609719bSwdenk typedef int (*Xilinx_cs_fn)( int assert_cs, int flush, int cookie ); 60c609719bSwdenk typedef int (*Xilinx_wr_fn)( int assert_write, int flush, int cookie ); 61c609719bSwdenk typedef int (*Xilinx_rdata_fn)( unsigned char *data, int cookie ); 62c609719bSwdenk typedef int (*Xilinx_wdata_fn)( unsigned char data, int flush, int cookie ); 63c609719bSwdenk typedef int (*Xilinx_busy_fn)( int cookie ); 64c609719bSwdenk typedef int (*Xilinx_abort_fn)( int cookie ); 65c609719bSwdenk typedef int (*Xilinx_pre_fn)( int cookie ); 66c609719bSwdenk typedef int (*Xilinx_post_fn)( int cookie ); 6789083346SWolfgang Wegner typedef int (*Xilinx_bwr_fn)( void *buf, size_t len, int flush, int cookie ); 68c609719bSwdenk 69c609719bSwdenk #endif /* _XILINX_H_ */ 70