1*c609719bSwdenk /* 2*c609719bSwdenk * (C) Copyright 2002 3*c609719bSwdenk * Rich Ireland, Enterasys Networks, rireland@enterasys.com. 4*c609719bSwdenk * 5*c609719bSwdenk * See file CREDITS for list of people who contributed to this 6*c609719bSwdenk * project. 7*c609719bSwdenk * 8*c609719bSwdenk * This program is free software; you can redistribute it and/or 9*c609719bSwdenk * modify it under the terms of the GNU General Public License as 10*c609719bSwdenk * published by the Free Software Foundation; either version 2 of 11*c609719bSwdenk * the License, or (at your option) any later version. 12*c609719bSwdenk * 13*c609719bSwdenk * This program is distributed in the hope that it will be useful, 14*c609719bSwdenk * but WITHOUT ANY WARRANTY; without even the implied warranty of 15*c609719bSwdenk * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16*c609719bSwdenk * GNU General Public License for more details. 17*c609719bSwdenk * 18*c609719bSwdenk * You should have received a copy of the GNU General Public License 19*c609719bSwdenk * along with this program; if not, write to the Free Software 20*c609719bSwdenk * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21*c609719bSwdenk * MA 02111-1307 USA 22*c609719bSwdenk * 23*c609719bSwdenk */ 24*c609719bSwdenk 25*c609719bSwdenk #include <fpga.h> 26*c609719bSwdenk 27*c609719bSwdenk #ifndef _XILINX_H_ 28*c609719bSwdenk #define _XILINX_H_ 29*c609719bSwdenk 30*c609719bSwdenk /* Xilinx Model definitions 31*c609719bSwdenk *********************************************************************/ 32*c609719bSwdenk #define CFG_SPARTAN2 CFG_FPGA_DEV( 0x1 ) 33*c609719bSwdenk #define CFG_VIRTEX_E CFG_FPGA_DEV( 0x2 ) 34*c609719bSwdenk #define CFG_VIRTEX2 CFG_FPGA_DEV( 0x4 ) 35*c609719bSwdenk #define CFG_XILINX_SPARTAN2 (CFG_FPGA_XILINX | CFG_SPARTAN2) 36*c609719bSwdenk #define CFG_XILINX_VIRTEX_E (CFG_FPGA_XILINX | CFG_VIRTEX_E) 37*c609719bSwdenk #define CFG_XILINX_VIRTEX2 (CFG_FPGA_XILINX | CFG_VIRTEX2) 38*c609719bSwdenk /* XXX - Add new models here */ 39*c609719bSwdenk 40*c609719bSwdenk 41*c609719bSwdenk /* Xilinx Interface definitions 42*c609719bSwdenk *********************************************************************/ 43*c609719bSwdenk #define CFG_XILINX_IF_SS CFG_FPGA_IF( 0x1 ) /* slave serial */ 44*c609719bSwdenk #define CFG_XILINX_IF_MS CFG_FPGA_IF( 0x2 ) /* master serial */ 45*c609719bSwdenk #define CFG_XILINX_IF_SP CFG_FPGA_IF( 0x4 ) /* slave parallel */ 46*c609719bSwdenk #define CFG_XILINX_IF_JTAG CFG_FPGA_IF( 0x8 ) /* jtag */ 47*c609719bSwdenk #define CFG_XILINX_IF_MSM CFG_FPGA_IF( 0x10 ) /* master selectmap */ 48*c609719bSwdenk #define CFG_XILINX_IF_SSM CFG_FPGA_IF( 0x20 ) /* slave selectmap */ 49*c609719bSwdenk 50*c609719bSwdenk /* Xilinx types 51*c609719bSwdenk *********************************************************************/ 52*c609719bSwdenk typedef enum { /* typedef Xilinx_iface */ 53*c609719bSwdenk min_xilinx_iface_type, /* low range check value */ 54*c609719bSwdenk slave_serial, /* serial data and external clock */ 55*c609719bSwdenk master_serial, /* serial data w/ internal clock (not used) */ 56*c609719bSwdenk slave_parallel, /* parallel data w/ external latch */ 57*c609719bSwdenk jtag_mode, /* jtag/tap serial (not used ) */ 58*c609719bSwdenk master_selectmap, /* master SelectMap (virtex2) */ 59*c609719bSwdenk slave_selectmap, /* slave SelectMap (virtex2) */ 60*c609719bSwdenk max_xilinx_iface_type /* insert all new types before this */ 61*c609719bSwdenk } Xilinx_iface; /* end, typedef Xilinx_iface */ 62*c609719bSwdenk 63*c609719bSwdenk typedef enum { /* typedef Xilinx_Family */ 64*c609719bSwdenk min_xilinx_type, /* low range check value */ 65*c609719bSwdenk Xilinx_Spartan2, /* Spartan-II Family */ 66*c609719bSwdenk Xilinx_VirtexE, /* Virtex-E Family */ 67*c609719bSwdenk Xilinx_Virtex2, /* Virtex2 Family */ 68*c609719bSwdenk max_xilinx_type /* insert all new types before this */ 69*c609719bSwdenk } Xilinx_Family; /* end, typedef Xilinx_Family */ 70*c609719bSwdenk 71*c609719bSwdenk typedef struct { /* typedef Xilinx_desc */ 72*c609719bSwdenk Xilinx_Family family; /* part type */ 73*c609719bSwdenk Xilinx_iface iface; /* interface type */ 74*c609719bSwdenk size_t size; /* bytes of data part can accept */ 75*c609719bSwdenk void * iface_fns; /* interface function table */ 76*c609719bSwdenk int cookie; /* implementation specific cookie */ 77*c609719bSwdenk } Xilinx_desc; /* end, typedef Xilinx_desc */ 78*c609719bSwdenk 79*c609719bSwdenk /* Generic Xilinx Functions 80*c609719bSwdenk *********************************************************************/ 81*c609719bSwdenk extern int xilinx_load( Xilinx_desc *desc, void *image, size_t size ); 82*c609719bSwdenk extern int xilinx_dump( Xilinx_desc *desc, void *buf, size_t bsize ); 83*c609719bSwdenk extern int xilinx_info( Xilinx_desc *desc ); 84*c609719bSwdenk extern int xilinx_reloc( Xilinx_desc *desc, ulong reloc_offset ); 85*c609719bSwdenk 86*c609719bSwdenk /* Board specific implementation specific function types 87*c609719bSwdenk *********************************************************************/ 88*c609719bSwdenk typedef int (*Xilinx_pgm_fn)( int assert_pgm, int flush, int cookie ); 89*c609719bSwdenk typedef int (*Xilinx_init_fn)( int cookie ); 90*c609719bSwdenk typedef int (*Xilinx_err_fn)( int cookie ); 91*c609719bSwdenk typedef int (*Xilinx_done_fn)( int cookie ); 92*c609719bSwdenk typedef int (*Xilinx_clk_fn)( int assert_clk, int flush, int cookie ); 93*c609719bSwdenk typedef int (*Xilinx_cs_fn)( int assert_cs, int flush, int cookie ); 94*c609719bSwdenk typedef int (*Xilinx_wr_fn)( int assert_write, int flush, int cookie ); 95*c609719bSwdenk typedef int (*Xilinx_rdata_fn)( unsigned char *data, int cookie ); 96*c609719bSwdenk typedef int (*Xilinx_wdata_fn)( unsigned char data, int flush, int cookie ); 97*c609719bSwdenk typedef int (*Xilinx_busy_fn)( int cookie ); 98*c609719bSwdenk typedef int (*Xilinx_abort_fn)( int cookie ); 99*c609719bSwdenk typedef int (*Xilinx_pre_fn)( int cookie ); 100*c609719bSwdenk typedef int (*Xilinx_post_fn)( int cookie ); 101*c609719bSwdenk 102*c609719bSwdenk #endif /* _XILINX_H_ */ 103