1*85056932SStefan Roese /* 2*85056932SStefan Roese * Copyright (C) 2016 Stefan Roese <sr@denx.de> 3*85056932SStefan Roese * 4*85056932SStefan Roese * SPDX-License-Identifier: GPL-2.0+ 5*85056932SStefan Roese */ 6*85056932SStefan Roese 7*85056932SStefan Roese #ifndef _WINBOND_W83627_H_ 8*85056932SStefan Roese #define _WINBOND_W83627_H_ 9*85056932SStefan Roese 10*85056932SStefan Roese /* I/O address of Winbond Super IO chip */ 11*85056932SStefan Roese #define WINBOND_IO_PORT 0x2e 12*85056932SStefan Roese 13*85056932SStefan Roese /* Logical device number */ 14*85056932SStefan Roese #define W83627DHG_FDC 0 /* Floppy */ 15*85056932SStefan Roese #define W83627DHG_PP 1 /* Parallel port */ 16*85056932SStefan Roese #define W83627DHG_SP1 2 /* Com1 */ 17*85056932SStefan Roese #define W83627DHG_SP2 3 /* Com2 */ 18*85056932SStefan Roese #define W83627DHG_KBC 5 /* PS/2 keyboard & mouse */ 19*85056932SStefan Roese #define W83627DHG_SPI 6 /* Serial peripheral interface */ 20*85056932SStefan Roese #define W83627DHG_WDTO_PLED 8 /* WDTO#, PLED */ 21*85056932SStefan Roese #define W83627DHG_ACPI 10 /* ACPI */ 22*85056932SStefan Roese #define W83627DHG_HWM 11 /* Hardware monitor */ 23*85056932SStefan Roese #define W83627DHG_PECI_SST 12 /* PECI, SST */ 24*85056932SStefan Roese 25*85056932SStefan Roese /** 26*85056932SStefan Roese * Configure the base I/O port of the specified serial device and enable the 27*85056932SStefan Roese * serial device. 28*85056932SStefan Roese * 29*85056932SStefan Roese * @dev: high 8 bits = super I/O port, low 8 bits = logical device number 30*85056932SStefan Roese * @iobase: processor I/O port address to assign to this serial device 31*85056932SStefan Roese * @irq: processor IRQ number to assign to this serial device 32*85056932SStefan Roese */ 33*85056932SStefan Roese void winbond_enable_serial(uint dev, uint iobase, uint irq); 34*85056932SStefan Roese 35*85056932SStefan Roese #endif /* _WINBOND_W83627_H_ */ 36