1 /* 2 * Copyright (c) 2005, 2009 Freescale Semiconductor, Inc 3 * Copyright (c) 2005 MontaVista Software 4 * Copyright (c) 2008 Excito Elektronik i Sk=E5ne AB 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef _EHCI_CI_H 10 #define _EHCI_CI_H 11 12 #include <asm/processor.h> 13 14 #define CONTROL_REGISTER_W1C_MASK 0x00020000 /* W1C: PHY_CLK_VALID */ 15 16 /* Global offsets */ 17 #define FSL_SKIP_PCI 0x100 18 19 /* offsets for the non-ehci registers in the FSL SOC USB controller */ 20 #define FSL_SOC_USB_ULPIVP 0x170 21 #define FSL_SOC_USB_PORTSC1 0x184 22 #define PORT_PTS_MSK (3 << 30) 23 #define PORT_PTS_UTMI (0 << 30) 24 #define PORT_PTS_ULPI (2 << 30) 25 #define PORT_PTS_SERIAL (3 << 30) 26 #define PORT_PTS_PTW (1 << 28) 27 #define PORT_PFSC (1 << 24) /* Defined on Page 39-44 of the mpc5151 ERM */ 28 #define PORT_PTS_PHCD (1 << 23) 29 #define PORT_PP (1 << 12) 30 #define PORT_PR (1 << 8) 31 32 /* USBMODE Register bits */ 33 #define CM_IDLE (0 << 0) 34 #define CM_RESERVED (1 << 0) 35 #define CM_DEVICE (2 << 0) 36 #define CM_HOST (3 << 0) 37 #define ES_BE (1 << 2) /* Big Endian Select, default is LE */ 38 #define USBMODE_RESERVED_2 (0 << 2) 39 #define SLOM (1 << 3) 40 #define SDIS (1 << 4) 41 42 /* CONTROL Register bits */ 43 #define ULPI_INT_EN (1 << 0) 44 #define WU_INT_EN (1 << 1) 45 #define USB_EN (1 << 2) 46 #define LSF_EN (1 << 3) 47 #define KEEP_OTG_ON (1 << 4) 48 #define OTG_PORT (1 << 5) 49 #define REFSEL_12MHZ (0 << 6) 50 #define REFSEL_16MHZ (1 << 6) 51 #define REFSEL_48MHZ (2 << 6) 52 #define PLL_RESET (1 << 8) 53 #define UTMI_PHY_EN (1 << 9) 54 #define PHY_CLK_SEL_UTMI (0 << 10) 55 #define PHY_CLK_SEL_ULPI (1 << 10) 56 #define CLKIN_SEL_USB_CLK (0 << 11) 57 #define CLKIN_SEL_USB_CLK2 (1 << 11) 58 #define CLKIN_SEL_SYS_CLK (2 << 11) 59 #define CLKIN_SEL_SYS_CLK2 (3 << 11) 60 #define RESERVED_18 (0 << 13) 61 #define RESERVED_17 (0 << 14) 62 #define RESERVED_16 (0 << 15) 63 #define WU_INT (1 << 16) 64 #define PHY_CLK_VALID (1 << 17) 65 66 #define FSL_SOC_USB_PORTSC2 0x188 67 68 /* OTG Status Control Register bits */ 69 #define FSL_SOC_USB_OTGSC 0x1a4 70 #define CTRL_VBUS_DISCHARGE (0x1<<0) 71 #define CTRL_VBUS_CHARGE (0x1<<1) 72 #define CTRL_OTG_TERMINATION (0x1<<3) 73 #define CTRL_DATA_PULSING (0x1<<4) 74 #define CTRL_ID_PULL_EN (0x1<<5) 75 #define HA_DATA_PULSE (0x1<<6) 76 #define HA_BA (0x1<<7) 77 #define STS_USB_ID (0x1<<8) 78 #define STS_A_VBUS_VALID (0x1<<9) 79 #define STS_A_SESSION_VALID (0x1<<10) 80 #define STS_B_SESSION_VALID (0x1<<11) 81 #define STS_B_SESSION_END (0x1<<12) 82 #define STS_1MS_TOGGLE (0x1<<13) 83 #define STS_DATA_PULSING (0x1<<14) 84 #define INTSTS_USB_ID (0x1<<16) 85 #define INTSTS_A_VBUS_VALID (0x1<<17) 86 #define INTSTS_A_SESSION_VALID (0x1<<18) 87 #define INTSTS_B_SESSION_VALID (0x1<<19) 88 #define INTSTS_B_SESSION_END (0x1<<20) 89 #define INTSTS_1MS (0x1<<21) 90 #define INTSTS_DATA_PULSING (0x1<<22) 91 #define INTR_USB_ID_EN (0x1<<24) 92 #define INTR_A_VBUS_VALID_EN (0x1<<25) 93 #define INTR_A_SESSION_VALID_EN (0x1<<26) 94 #define INTR_B_SESSION_VALID_EN (0x1<<27) 95 #define INTR_B_SESSION_END_EN (0x1<<28) 96 #define INTR_1MS_TIMER_EN (0x1<<29) 97 #define INTR_DATA_PULSING_EN (0x1<<30) 98 #define INTSTS_MASK (0x00ff0000) 99 100 /* USBCMD Bits of interest */ 101 #define EHCI_FSL_USBCMD_RST (1 << 1) 102 #define EHCI_FSL_USBCMD_RS (1 << 0) 103 104 #define INTERRUPT_ENABLE_BITS_MASK \ 105 (INTR_USB_ID_EN | \ 106 INTR_1MS_TIMER_EN | \ 107 INTR_A_VBUS_VALID_EN | \ 108 INTR_A_SESSION_VALID_EN | \ 109 INTR_B_SESSION_VALID_EN | \ 110 INTR_B_SESSION_END_EN | \ 111 INTR_DATA_PULSING_EN) 112 113 #define INTERRUPT_STATUS_BITS_MASK \ 114 (INTSTS_USB_ID | \ 115 INTR_1MS_TIMER_EN | \ 116 INTSTS_A_VBUS_VALID | \ 117 INTSTS_A_SESSION_VALID | \ 118 INTSTS_B_SESSION_VALID | \ 119 INTSTS_B_SESSION_END | \ 120 INTSTS_DATA_PULSING) 121 122 #define FSL_SOC_USB_USBMODE 0x1a8 123 124 #define USBGENCTRL 0x200 /* NOTE: big endian */ 125 #define GC_WU_INT_CLR (1 << 5) /* Wakeup int clear */ 126 #define GC_ULPI_SEL (1 << 4) /* ULPI i/f select (usb0 only)*/ 127 #define GC_PPP (1 << 3) /* Port Power Polarity */ 128 #define GC_PFP (1 << 2) /* Power Fault Polarity */ 129 #define GC_WU_ULPI_EN (1 << 1) /* Wakeup on ULPI event */ 130 #define GC_WU_IE (1 << 1) /* Wakeup interrupt enable */ 131 132 #define ISIPHYCTRL 0x204 /* NOTE: big endian */ 133 #define PHYCTRL_PHYE (1 << 4) /* On-chip UTMI PHY enable */ 134 #define PHYCTRL_BSENH (1 << 3) /* Bit Stuff Enable High */ 135 #define PHYCTRL_BSEN (1 << 2) /* Bit Stuff Enable */ 136 #define PHYCTRL_LSFE (1 << 1) /* Line State Filter Enable */ 137 #define PHYCTRL_PXE (1 << 0) /* PHY oscillator enable */ 138 139 #define FSL_SOC_USB_SNOOP1 0x400 /* NOTE: big-endian */ 140 #define FSL_SOC_USB_SNOOP2 0x404 /* NOTE: big-endian */ 141 #define FSL_SOC_USB_AGECNTTHRSH 0x408 /* NOTE: big-endian */ 142 #define FSL_SOC_USB_PRICTRL 0x40c /* NOTE: big-endian */ 143 #define FSL_SOC_USB_SICTRL 0x410 /* NOTE: big-endian */ 144 #define FSL_SOC_USB_CTRL 0x500 /* NOTE: big-endian */ 145 #define SNOOP_SIZE_2GB 0x1e 146 147 /* System Clock Control Register */ 148 #define MPC83XX_SCCR_USB_MASK 0x00f00000 149 #define MPC83XX_SCCR_USB_DRCM_11 0x00300000 150 #define MPC83XX_SCCR_USB_DRCM_01 0x00100000 151 #define MPC83XX_SCCR_USB_DRCM_10 0x00200000 152 153 #if defined(CONFIG_MPC83xx) 154 #define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_MPC83xx_USB1_ADDR 155 #if defined(CONFIG_MPC834x) 156 #define CONFIG_SYS_FSL_USB2_ADDR CONFIG_SYS_MPC83xx_USB2_ADDR 157 #else 158 #define CONFIG_SYS_FSL_USB2_ADDR 0 159 #endif 160 #elif defined(CONFIG_MPC85xx) 161 #define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_MPC85xx_USB1_ADDR 162 #define CONFIG_SYS_FSL_USB2_ADDR CONFIG_SYS_MPC85xx_USB2_ADDR 163 #elif defined(CONFIG_MPC512X) 164 #define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_MPC512x_USB1_ADDR 165 #define CONFIG_SYS_FSL_USB2_ADDR 0 166 #elif defined(CONFIG_LS102XA) 167 #define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_LS102XA_USB1_ADDR 168 #define CONFIG_SYS_FSL_USB2_ADDR 0 169 #endif 170 171 /* 172 * Increasing TX FIFO threshold value from 2 to 4 decreases 173 * data burst rate with which data packets are posted from the TX 174 * latency FIFO to compensate for latencies in DDR pipeline during DMA 175 */ 176 #define TXFIFOTHRESH 4 177 178 /* 179 * USB Registers 180 */ 181 struct usb_ehci { 182 u32 id; /* 0x000 - Identification register */ 183 u32 hwgeneral; /* 0x004 - General hardware parameters */ 184 u32 hwhost; /* 0x008 - Host hardware parameters */ 185 u32 hwdevice; /* 0x00C - Device hardware parameters */ 186 u32 hwtxbuf; /* 0x010 - TX buffer hardware parameters */ 187 u32 hwrxbuf; /* 0x014 - RX buffer hardware parameters */ 188 u8 res1[0x68]; 189 u32 gptimer0_ld; /* 0x080 - General Purpose Timer 0 load value */ 190 u32 gptimer0_ctrl; /* 0x084 - General Purpose Timer 0 control */ 191 u32 gptimer1_ld; /* 0x088 - General Purpose Timer 1 load value */ 192 u32 gptimer1_ctrl; /* 0x08C - General Purpose Timer 1 control */ 193 u32 sbuscfg; /* 0x090 - System Bus Interface Control */ 194 u32 sbusstatus; /* 0x094 - System Bus Interface Status */ 195 u32 sbusmode; /* 0x098 - System Bus Interface Mode */ 196 u32 genconfig; /* 0x09C - USB Core Configuration */ 197 u32 genconfig2; /* 0x0A0 - USB Core Configuration 2 */ 198 u8 res2[0x5c]; 199 u8 caplength; /* 0x100 - Capability Register Length */ 200 u8 res3[0x1]; 201 u16 hciversion; /* 0x102 - Host Interface Version */ 202 u32 hcsparams; /* 0x104 - Host Structural Parameters */ 203 u32 hccparams; /* 0x108 - Host Capability Parameters */ 204 u8 res4[0x14]; 205 u32 dciversion; /* 0x120 - Device Interface Version */ 206 u32 dciparams; /* 0x124 - Device Controller Params */ 207 u8 res5[0x18]; 208 u32 usbcmd; /* 0x140 - USB Command */ 209 u32 usbsts; /* 0x144 - USB Status */ 210 u32 usbintr; /* 0x148 - USB Interrupt Enable */ 211 u32 frindex; /* 0x14C - USB Frame Index */ 212 u8 res6[0x4]; 213 u32 perlistbase; /* 0x154 - Periodic List Base 214 - USB Device Address */ 215 u32 ep_list_addr; /* 0x158 - Next Asynchronous List 216 - End Point Address */ 217 u8 res7[0x4]; 218 u32 burstsize; /* 0x160 - Programmable Burst Size */ 219 #define FSL_EHCI_TXPBURST(X) ((X) << 8) 220 #define FSL_EHCI_RXPBURST(X) (X) 221 u32 txfilltuning; /* 0x164 - Host TT Transmit 222 pre-buffer packet tuning */ 223 u8 res8[0x8]; 224 u32 ulpi_viewpoint; /* 0x170 - ULPI Reister Access */ 225 u8 res9[0xc]; 226 u32 config_flag; /* 0x180 - Configured Flag Register */ 227 u32 portsc; /* 0x184 - Port status/control */ 228 u8 res10[0x1C]; 229 u32 otgsc; /* 0x1a4 - Oo-The-Go status and control */ 230 u32 usbmode; /* 0x1a8 - USB Device Mode */ 231 u32 epsetupstat; /* 0x1ac - End Point Setup Status */ 232 u32 epprime; /* 0x1b0 - End Point Init Status */ 233 u32 epflush; /* 0x1b4 - End Point De-initlialize */ 234 u32 epstatus; /* 0x1b8 - End Point Status */ 235 u32 epcomplete; /* 0x1bc - End Point Complete */ 236 u32 epctrl0; /* 0x1c0 - End Point Control 0 */ 237 u32 epctrl1; /* 0x1c4 - End Point Control 1 */ 238 u32 epctrl2; /* 0x1c8 - End Point Control 2 */ 239 u32 epctrl3; /* 0x1cc - End Point Control 3 */ 240 u32 epctrl4; /* 0x1d0 - End Point Control 4 */ 241 u32 epctrl5; /* 0x1d4 - End Point Control 5 */ 242 u8 res11[0x28]; 243 u32 usbgenctrl; /* 0x200 - USB General Control */ 244 u32 isiphyctrl; /* 0x204 - On-Chip PHY Control */ 245 u8 res12[0x1F8]; 246 u32 snoop1; /* 0x400 - Snoop 1 */ 247 u32 snoop2; /* 0x404 - Snoop 2 */ 248 u32 age_cnt_limit; /* 0x408 - Age Count Threshold */ 249 u32 prictrl; /* 0x40c - Priority Control */ 250 u32 sictrl; /* 0x410 - System Interface Control */ 251 u8 res13[0xEC]; 252 u32 control; /* 0x500 - Control */ 253 u8 res14[0xafc]; 254 }; 255 256 /* 257 * For MXC SOCs 258 */ 259 260 /* values for portsc field */ 261 #define MXC_EHCI_PHY_LOW_POWER_SUSPEND (1 << 23) 262 #define MXC_EHCI_FORCE_FS (1 << 24) 263 #define MXC_EHCI_UTMI_8BIT (0 << 28) 264 #define MXC_EHCI_UTMI_16BIT (1 << 28) 265 #define MXC_EHCI_SERIAL (1 << 29) 266 #define MXC_EHCI_MODE_UTMI (0 << 30) 267 #define MXC_EHCI_MODE_PHILIPS (1 << 30) 268 #define MXC_EHCI_MODE_ULPI (2 << 30) 269 #define MXC_EHCI_MODE_SERIAL (3 << 30) 270 271 /* values for flags field */ 272 #define MXC_EHCI_INTERFACE_DIFF_UNI (0 << 0) 273 #define MXC_EHCI_INTERFACE_DIFF_BI (1 << 0) 274 #define MXC_EHCI_INTERFACE_SINGLE_UNI (2 << 0) 275 #define MXC_EHCI_INTERFACE_SINGLE_BI (3 << 0) 276 #define MXC_EHCI_INTERFACE_MASK (0xf) 277 278 #define MXC_EHCI_POWER_PINS_ENABLED (1 << 5) 279 #define MXC_EHCI_PWR_PIN_ACTIVE_HIGH (1 << 6) 280 #define MXC_EHCI_OC_PIN_ACTIVE_LOW (1 << 7) 281 #define MXC_EHCI_TTL_ENABLED (1 << 8) 282 283 #define MXC_EHCI_INTERNAL_PHY (1 << 9) 284 #define MXC_EHCI_IPPUE_DOWN (1 << 10) 285 #define MXC_EHCI_IPPUE_UP (1 << 11) 286 287 int usb_phy_mode(int port); 288 /* Board-specific initialization */ 289 int board_ehci_hcd_init(int port); 290 int board_usb_phy_mode(int port); 291 292 #endif /* _EHCI_CI_H */ 293