18966eb4cSTom Rix /* 28966eb4cSTom Rix * Copyright (c) 2009 Wind River Systems, Inc. 38966eb4cSTom Rix * Tom Rix <Tom.Rix at windriver.com> 48966eb4cSTom Rix * 51a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 68966eb4cSTom Rix * 78966eb4cSTom Rix * Derived from code on omapzoom, git://git.omapzoom.com/repo/u-boot.git 88966eb4cSTom Rix * 98966eb4cSTom Rix * Copyright (C) 2007-2009 Texas Instruments, Inc. 108966eb4cSTom Rix */ 118966eb4cSTom Rix 128966eb4cSTom Rix #ifndef TWL4030_H 138966eb4cSTom Rix #define TWL4030_H 148966eb4cSTom Rix 158966eb4cSTom Rix #include <common.h> 168966eb4cSTom Rix #include <i2c.h> 178966eb4cSTom Rix 188966eb4cSTom Rix /* I2C chip addresses */ 198966eb4cSTom Rix 208966eb4cSTom Rix /* USB */ 218966eb4cSTom Rix #define TWL4030_CHIP_USB 0x48 228966eb4cSTom Rix /* AUD */ 238966eb4cSTom Rix #define TWL4030_CHIP_AUDIO_VOICE 0x49 248966eb4cSTom Rix #define TWL4030_CHIP_GPIO 0x49 258966eb4cSTom Rix #define TWL4030_CHIP_INTBR 0x49 268966eb4cSTom Rix #define TWL4030_CHIP_PIH 0x49 278966eb4cSTom Rix #define TWL4030_CHIP_TEST 0x49 288966eb4cSTom Rix /* AUX */ 298966eb4cSTom Rix #define TWL4030_CHIP_KEYPAD 0x4a 308966eb4cSTom Rix #define TWL4030_CHIP_MADC 0x4a 318966eb4cSTom Rix #define TWL4030_CHIP_INTERRUPTS 0x4a 328966eb4cSTom Rix #define TWL4030_CHIP_LED 0x4a 338966eb4cSTom Rix #define TWL4030_CHIP_MAIN_CHARGE 0x4a 348966eb4cSTom Rix #define TWL4030_CHIP_PRECHARGE 0x4a 358966eb4cSTom Rix #define TWL4030_CHIP_PWM0 0x4a 368966eb4cSTom Rix #define TWL4030_CHIP_PWM1 0x4a 378966eb4cSTom Rix #define TWL4030_CHIP_PWMA 0x4a 388966eb4cSTom Rix #define TWL4030_CHIP_PWMB 0x4a 398966eb4cSTom Rix /* POWER */ 408966eb4cSTom Rix #define TWL4030_CHIP_BACKUP 0x4b 418966eb4cSTom Rix #define TWL4030_CHIP_INT 0x4b 428966eb4cSTom Rix #define TWL4030_CHIP_PM_MASTER 0x4b 438966eb4cSTom Rix #define TWL4030_CHIP_PM_RECEIVER 0x4b 448966eb4cSTom Rix #define TWL4030_CHIP_RTC 0x4b 458966eb4cSTom Rix #define TWL4030_CHIP_SECURED_REG 0x4b 468966eb4cSTom Rix 478966eb4cSTom Rix /* Register base addresses */ 488966eb4cSTom Rix 498966eb4cSTom Rix /* USB */ 508966eb4cSTom Rix #define TWL4030_BASEADD_USB 0x0000 518966eb4cSTom Rix /* AUD */ 528966eb4cSTom Rix #define TWL4030_BASEADD_AUDIO_VOICE 0x0000 538966eb4cSTom Rix #define TWL4030_BASEADD_GPIO 0x0098 548966eb4cSTom Rix #define TWL4030_BASEADD_INTBR 0x0085 558966eb4cSTom Rix #define TWL4030_BASEADD_PIH 0x0080 568966eb4cSTom Rix #define TWL4030_BASEADD_TEST 0x004C 578966eb4cSTom Rix /* AUX */ 588966eb4cSTom Rix #define TWL4030_BASEADD_INTERRUPTS 0x00B9 598966eb4cSTom Rix #define TWL4030_BASEADD_LED 0x00EE 608966eb4cSTom Rix #define TWL4030_BASEADD_MADC 0x0000 618966eb4cSTom Rix #define TWL4030_BASEADD_MAIN_CHARGE 0x0074 628966eb4cSTom Rix #define TWL4030_BASEADD_PRECHARGE 0x00AA 638966eb4cSTom Rix #define TWL4030_BASEADD_PWM0 0x00F8 648966eb4cSTom Rix #define TWL4030_BASEADD_PWM1 0x00FB 658966eb4cSTom Rix #define TWL4030_BASEADD_PWMA 0x00EF 668966eb4cSTom Rix #define TWL4030_BASEADD_PWMB 0x00F1 678966eb4cSTom Rix #define TWL4030_BASEADD_KEYPAD 0x00D2 688966eb4cSTom Rix /* POWER */ 698966eb4cSTom Rix #define TWL4030_BASEADD_BACKUP 0x0014 708966eb4cSTom Rix #define TWL4030_BASEADD_INT 0x002E 718966eb4cSTom Rix #define TWL4030_BASEADD_PM_MASTER 0x0036 728966eb4cSTom Rix #define TWL4030_BASEADD_PM_RECIEVER 0x005B 738966eb4cSTom Rix #define TWL4030_BASEADD_RTC 0x001C 748966eb4cSTom Rix #define TWL4030_BASEADD_SECURED_REG 0x0000 758966eb4cSTom Rix 768966eb4cSTom Rix /* 778966eb4cSTom Rix * Power Management Master 788966eb4cSTom Rix */ 798966eb4cSTom Rix #define TWL4030_PM_MASTER_CFG_P1_TRANSITION 0x36 808966eb4cSTom Rix #define TWL4030_PM_MASTER_CFG_P2_TRANSITION 0x37 818966eb4cSTom Rix #define TWL4030_PM_MASTER_CFG_P3_TRANSITION 0x38 828966eb4cSTom Rix #define TWL4030_PM_MASTER_CFG_P123_TRANSITION 0x39 838966eb4cSTom Rix #define TWL4030_PM_MASTER_STS_BOOT 0x3A 848966eb4cSTom Rix #define TWL4030_PM_MASTER_CFG_BOOT 0x3B 858966eb4cSTom Rix #define TWL4030_PM_MASTER_SHUNDAN 0x3C 868966eb4cSTom Rix #define TWL4030_PM_MASTER_BOOT_BCI 0x3D 878966eb4cSTom Rix #define TWL4030_PM_MASTER_CFG_PWRANA1 0x3E 888966eb4cSTom Rix #define TWL4030_PM_MASTER_CFG_PWRANA2 0x3F 898966eb4cSTom Rix #define TWL4030_PM_MASTER_BGAP_TRIM 0x40 908966eb4cSTom Rix #define TWL4030_PM_MASTER_BACKUP_MISC_STS 0x41 918966eb4cSTom Rix #define TWL4030_PM_MASTER_BACKUP_MISC_CFG 0x42 928966eb4cSTom Rix #define TWL4030_PM_MASTER_BACKUP_MISC_TST 0x43 938966eb4cSTom Rix #define TWL4030_PM_MASTER_PROTECT_KEY 0x44 948966eb4cSTom Rix #define TWL4030_PM_MASTER_STS_HW_CONDITIONS 0x45 958966eb4cSTom Rix #define TWL4030_PM_MASTER_P1_SW_EVENTS 0x46 968966eb4cSTom Rix #define TWL4030_PM_MASTER_P2_SW_EVENTS 0x47 978966eb4cSTom Rix #define TWL4030_PM_MASTER_P3_SW_EVENTS 0x48 988966eb4cSTom Rix #define TWL4030_PM_MASTER_STS_P123_STATE 0x49 998966eb4cSTom Rix #define TWL4030_PM_MASTER_PB_CFG 0x4A 1008966eb4cSTom Rix #define TWL4030_PM_MASTER_PB_WORD_MSB 0x4B 1018966eb4cSTom Rix #define TWL4030_PM_MASTER_PB_WORD_LSB 0x4C 1028966eb4cSTom Rix #define TWL4030_PM_MASTER_SEQ_ADD_W2P 0x52 1038966eb4cSTom Rix #define TWL4030_PM_MASTER_SEQ_ADD_P2A 0x53 1048966eb4cSTom Rix #define TWL4030_PM_MASTER_SEQ_ADD_A2W 0x54 1058966eb4cSTom Rix #define TWL4030_PM_MASTER_SEQ_ADD_A2S 0x55 1068966eb4cSTom Rix #define TWL4030_PM_MASTER_SEQ_ADD_S2A12 0x56 1078966eb4cSTom Rix #define TWL4030_PM_MASTER_SEQ_ADD_S2A3 0x57 1088966eb4cSTom Rix #define TWL4030_PM_MASTER_SEQ_ADD_WARM 0x58 1098966eb4cSTom Rix #define TWL4030_PM_MASTER_MEMORY_ADDRESS 0x59 1108966eb4cSTom Rix #define TWL4030_PM_MASTER_MEMORY_DATA 0x5A 1118966eb4cSTom Rix #define TWL4030_PM_MASTER_SC_CONFIG 0x5B 1128966eb4cSTom Rix #define TWL4030_PM_MASTER_SC_DETECT1 0x5C 1138966eb4cSTom Rix #define TWL4030_PM_MASTER_SC_DETECT2 0x5D 1148966eb4cSTom Rix #define TWL4030_PM_MASTER_WATCHDOG_CFG 0x5E 1158966eb4cSTom Rix #define TWL4030_PM_MASTER_IT_CHECK_CFG 0x5F 1168966eb4cSTom Rix #define TWL4030_PM_MASTER_VIBRATOR_CFG 0x60 1178966eb4cSTom Rix #define TWL4030_PM_MASTER_DCDC_GLOBAL_CFG 0x61 1188966eb4cSTom Rix #define TWL4030_PM_MASTER_VDD1_TRIM1 0x62 1198966eb4cSTom Rix #define TWL4030_PM_MASTER_VDD1_TRIM2 0x63 1208966eb4cSTom Rix #define TWL4030_PM_MASTER_VDD2_TRIM1 0x64 1218966eb4cSTom Rix #define TWL4030_PM_MASTER_VDD2_TRIM2 0x65 1228966eb4cSTom Rix #define TWL4030_PM_MASTER_VIO_TRIM1 0x66 1238966eb4cSTom Rix #define TWL4030_PM_MASTER_VIO_TRIM2 0x67 1248966eb4cSTom Rix #define TWL4030_PM_MASTER_MISC_CFG 0x68 1258966eb4cSTom Rix #define TWL4030_PM_MASTER_LS_TST_A 0x69 1268966eb4cSTom Rix #define TWL4030_PM_MASTER_LS_TST_B 0x6A 1278966eb4cSTom Rix #define TWL4030_PM_MASTER_LS_TST_C 0x6B 1288966eb4cSTom Rix #define TWL4030_PM_MASTER_LS_TST_D 0x6C 1298966eb4cSTom Rix #define TWL4030_PM_MASTER_BB_CFG 0x6D 1308966eb4cSTom Rix #define TWL4030_PM_MASTER_MISC_TST 0x6E 1318966eb4cSTom Rix #define TWL4030_PM_MASTER_TRIM1 0x6F 1328966eb4cSTom Rix 133318e70e2SPali Rohár /* Power bus message definitions */ 134318e70e2SPali Rohár 135318e70e2SPali Rohár /* The TWL4030/5030 splits its power-management resources (the various 136318e70e2SPali Rohár * regulators, clock and reset lines) into 3 processor groups - P1, P2 and 137318e70e2SPali Rohár * P3. These groups can then be configured to transition between sleep, wait-on 138318e70e2SPali Rohár * and active states by sending messages to the power bus. See Section 5.4.2 139318e70e2SPali Rohár * Power Resources of TWL4030 TRM 140318e70e2SPali Rohár */ 141318e70e2SPali Rohár 142318e70e2SPali Rohár /* Processor groups */ 143318e70e2SPali Rohár #define DEV_GRP_NULL 0x0 144318e70e2SPali Rohár #define DEV_GRP_P1 0x1 /* P1: all OMAP devices */ 145318e70e2SPali Rohár #define DEV_GRP_P2 0x2 /* P2: all Modem devices */ 146318e70e2SPali Rohár #define DEV_GRP_P3 0x4 /* P3: all peripheral devices */ 147318e70e2SPali Rohár 148318e70e2SPali Rohár /* Resource groups */ 149318e70e2SPali Rohár #define RES_GRP_RES 0x0 /* Reserved */ 150318e70e2SPali Rohár #define RES_GRP_PP 0x1 /* Power providers */ 151318e70e2SPali Rohár #define RES_GRP_RC 0x2 /* Reset and control */ 152318e70e2SPali Rohár #define RES_GRP_PP_RC 0x3 153318e70e2SPali Rohár #define RES_GRP_PR 0x4 /* Power references */ 154318e70e2SPali Rohár #define RES_GRP_PP_PR 0x5 155318e70e2SPali Rohár #define RES_GRP_RC_PR 0x6 156318e70e2SPali Rohár #define RES_GRP_ALL 0x7 /* All resource groups */ 157318e70e2SPali Rohár 158318e70e2SPali Rohár #define RES_TYPE2_R0 0x0 159318e70e2SPali Rohár 160318e70e2SPali Rohár #define RES_TYPE_ALL 0x7 161318e70e2SPali Rohár 162318e70e2SPali Rohár /* Resource states */ 163318e70e2SPali Rohár #define RES_STATE_WRST 0xF 164318e70e2SPali Rohár #define RES_STATE_ACTIVE 0xE 165318e70e2SPali Rohár #define RES_STATE_SLEEP 0x8 166318e70e2SPali Rohár #define RES_STATE_OFF 0x0 167318e70e2SPali Rohár 168318e70e2SPali Rohár /* Power resources */ 169318e70e2SPali Rohár 170318e70e2SPali Rohár /* Power providers */ 171318e70e2SPali Rohár #define RES_VAUX1 1 172318e70e2SPali Rohár #define RES_VAUX2 2 173318e70e2SPali Rohár #define RES_VAUX3 3 174318e70e2SPali Rohár #define RES_VAUX4 4 175318e70e2SPali Rohár #define RES_VMMC1 5 176318e70e2SPali Rohár #define RES_VMMC2 6 177318e70e2SPali Rohár #define RES_VPLL1 7 178318e70e2SPali Rohár #define RES_VPLL2 8 179318e70e2SPali Rohár #define RES_VSIM 9 180318e70e2SPali Rohár #define RES_VDAC 10 181318e70e2SPali Rohár #define RES_VINTANA1 11 182318e70e2SPali Rohár #define RES_VINTANA2 12 183318e70e2SPali Rohár #define RES_VINTDIG 13 184318e70e2SPali Rohár #define RES_VIO 14 185318e70e2SPali Rohár #define RES_VDD1 15 186318e70e2SPali Rohár #define RES_VDD2 16 187318e70e2SPali Rohár #define RES_VUSB_1V5 17 188318e70e2SPali Rohár #define RES_VUSB_1V8 18 189318e70e2SPali Rohár #define RES_VUSB_3V1 19 190318e70e2SPali Rohár #define RES_VUSBCP 20 191318e70e2SPali Rohár #define RES_REGEN 21 192318e70e2SPali Rohár /* Reset and control */ 193318e70e2SPali Rohár #define RES_NRES_PWRON 22 194318e70e2SPali Rohár #define RES_CLKEN 23 195318e70e2SPali Rohár #define RES_SYSEN 24 196318e70e2SPali Rohár #define RES_HFCLKOUT 25 197318e70e2SPali Rohár #define RES_32KCLKOUT 26 198318e70e2SPali Rohár #define RES_RESET 27 199318e70e2SPali Rohár /* Power Reference */ 200318e70e2SPali Rohár #define RES_Main_Ref 28 201318e70e2SPali Rohár 2026dc443e6SPaul Kocialkowski /* P[1-3]_SW_EVENTS */ 2036dc443e6SPaul Kocialkowski #define TWL4030_PM_MASTER_SW_EVENTS_STOPON_PWRON (1 << 6) 2046dc443e6SPaul Kocialkowski #define TWL4030_PM_MASTER_SW_EVENTS_STOPON_SYSEN (1 << 5) 2056dc443e6SPaul Kocialkowski #define TWL4030_PM_MASTER_SW_EVENTS_ENABLE_WARMRESET (1 << 4) 2066dc443e6SPaul Kocialkowski #define TWL4030_PM_MASTER_SW_EVENTS_LVL_WAKEUP (1 << 3) 2076dc443e6SPaul Kocialkowski #define TWL4030_PM_MASTER_SW_EVENTS_DEVACT (1 << 2) 2086dc443e6SPaul Kocialkowski #define TWL4030_PM_MASTER_SW_EVENTS_DEVSLP (1 << 1) 2096dc443e6SPaul Kocialkowski #define TWL4030_PM_MASTER_SW_EVENTS_DEVOFF (1 << 0) 2106dc443e6SPaul Kocialkowski 211*7d5ac918SPaul Kocialkowski /* HW conditions */ 212*7d5ac918SPaul Kocialkowski #define TWL4030_PM_MASTER_STS_HW_CONDITIONS_PWON (1 << 0) 213*7d5ac918SPaul Kocialkowski #define TWL4030_PM_MASTER_STS_HW_CONDITIONS_CHG (1 << 1) 214*7d5ac918SPaul Kocialkowski #define TWL4030_PM_MASTER_STS_HW_CONDITIONS_USB (1 << 2) 215*7d5ac918SPaul Kocialkowski #define TWL4030_PM_MASTER_STS_HW_CONDITIONS_VBUS (1 << 7) 216*7d5ac918SPaul Kocialkowski 2176dc443e6SPaul Kocialkowski /* Power transition */ 2186dc443e6SPaul Kocialkowski #define TWL4030_PM_MASTER_CFG_TRANSITION_STARTON_PWON (1 << 0) 2196dc443e6SPaul Kocialkowski #define TWL4030_PM_MASTER_CFG_TRANSITION_STARTON_CHG (1 << 1) 2206dc443e6SPaul Kocialkowski #define TWL4030_PM_MASTER_CFG_TRANSITION_STARTON_USB (1 << 2) 2216dc443e6SPaul Kocialkowski #define TWL4030_PM_MASTER_CFG_TRANSITION_STARTON_RTC (1 << 3) 2226dc443e6SPaul Kocialkowski #define TWL4030_PM_MASTER_CFG_TRANSITION_STARTON_VBAT (1 << 4) 2236dc443e6SPaul Kocialkowski #define TWL4030_PM_MASTER_CFG_TRANSITION_STARTON_VBUS (1 << 5) 2246dc443e6SPaul Kocialkowski #define TWL4030_PM_MASTER_CFG_TRANSITION_STARTON_SWBUG (1 << 7) 2256dc443e6SPaul Kocialkowski 2266dc443e6SPaul Kocialkowski /* PWRANA2 */ 2276dc443e6SPaul Kocialkowski #define TWL4030_PM_MASTER_CFG_PWRANA2_LOJIT0_LOWV (1 << 1) 2286dc443e6SPaul Kocialkowski #define TWL4030_PM_MASTER_CFG_PWRANA2_LOJIT1_LOWV (1 << 2) 2296dc443e6SPaul Kocialkowski 230318e70e2SPali Rohár #define TOTAL_RESOURCES 28 231318e70e2SPali Rohár /* 232318e70e2SPali Rohár * Power Bus Message Format ... these can be sent individually by Linux, 233318e70e2SPali Rohár * but are usually part of downloaded scripts that are run when various 234318e70e2SPali Rohár * power events are triggered. 235318e70e2SPali Rohár * 236318e70e2SPali Rohár * Broadcast Message (16 Bits): 237318e70e2SPali Rohár * DEV_GRP[15:13] MT[12] RES_GRP[11:9] RES_TYPE2[8:7] RES_TYPE[6:4] 238318e70e2SPali Rohár * RES_STATE[3:0] 239318e70e2SPali Rohár * 240318e70e2SPali Rohár * Singular Message (16 Bits): 241318e70e2SPali Rohár * DEV_GRP[15:13] MT[12] RES_ID[11:4] RES_STATE[3:0] 242318e70e2SPali Rohár */ 243318e70e2SPali Rohár 244318e70e2SPali Rohár #define MSG_BROADCAST(devgrp, grp, type, type2, state) \ 245318e70e2SPali Rohár ((devgrp) << 13 | 1 << 12 | (grp) << 9 | (type2) << 7 \ 246318e70e2SPali Rohár | (type) << 4 | (state)) 247318e70e2SPali Rohár 248318e70e2SPali Rohár #define MSG_SINGULAR(devgrp, id, state) \ 249318e70e2SPali Rohár ((devgrp) << 13 | 0 << 12 | (id) << 4 | (state)) 250318e70e2SPali Rohár 251318e70e2SPali Rohár #define MSG_BROADCAST_ALL(devgrp, state) \ 252318e70e2SPali Rohár ((devgrp) << 5 | (state)) 253318e70e2SPali Rohár 254318e70e2SPali Rohár #define MSG_BROADCAST_REF MSG_BROADCAST_ALL 255318e70e2SPali Rohár #define MSG_BROADCAST_PROV MSG_BROADCAST_ALL 256318e70e2SPali Rohár #define MSG_BROADCAST__CLK_RST MSG_BROADCAST_ALL 257318e70e2SPali Rohár 2588966eb4cSTom Rix /* Power Managment Receiver */ 2592c155130STom Rix #define TWL4030_PM_RECEIVER_SC_CONFIG 0x5B 2602c155130STom Rix #define TWL4030_PM_RECEIVER_SC_DETECT1 0x5C 2612c155130STom Rix #define TWL4030_PM_RECEIVER_SC_DETECT2 0x5D 2622c155130STom Rix #define TWL4030_PM_RECEIVER_WATCHDOG_CFG 0x5E 2632c155130STom Rix #define TWL4030_PM_RECEIVER_IT_CHECK_CFG 0x5F 2642c155130STom Rix #define TWL4030_PM_RECEIVER_VIBRATOR_CFG 0x5F 2652c155130STom Rix #define TWL4030_PM_RECEIVER_DC_TO_DC_CFG 0x61 2662c155130STom Rix #define TWL4030_PM_RECEIVER_VDD1_TRIM1 0x62 2672c155130STom Rix #define TWL4030_PM_RECEIVER_VDD1_TRIM2 0x63 2682c155130STom Rix #define TWL4030_PM_RECEIVER_VDD2_TRIM1 0x64 2692c155130STom Rix #define TWL4030_PM_RECEIVER_VDD2_TRIM2 0x65 2702c155130STom Rix #define TWL4030_PM_RECEIVER_VIO_TRIM1 0x66 2712c155130STom Rix #define TWL4030_PM_RECEIVER_VIO_TRIM2 0x67 2722c155130STom Rix #define TWL4030_PM_RECEIVER_MISC_CFG 0x68 2732c155130STom Rix #define TWL4030_PM_RECEIVER_LS_TST_A 0x69 2742c155130STom Rix #define TWL4030_PM_RECEIVER_LS_TST_B 0x6A 2752c155130STom Rix #define TWL4030_PM_RECEIVER_LS_TST_C 0x6B 2762c155130STom Rix #define TWL4030_PM_RECEIVER_LS_TST_D 0x6C 2772c155130STom Rix #define TWL4030_PM_RECEIVER_BB_CFG 0x6D 2782c155130STom Rix #define TWL4030_PM_RECEIVER_MISC_TST 0x6E 2792c155130STom Rix #define TWL4030_PM_RECEIVER_TRIM1 0x6F 2802c155130STom Rix #define TWL4030_PM_RECEIVER_TRIM2 0x70 2812c155130STom Rix #define TWL4030_PM_RECEIVER_DC_DC_TIMEOUT 0x71 2822c155130STom Rix #define TWL4030_PM_RECEIVER_VAUX1_DEV_GRP 0x72 2832c155130STom Rix #define TWL4030_PM_RECEIVER_VAUX1_TYPE 0x73 2842c155130STom Rix #define TWL4030_PM_RECEIVER_VAUX1_REMAP 0x74 2852c155130STom Rix #define TWL4030_PM_RECEIVER_VAUX1_DEDICATED 0x75 2862c155130STom Rix #define TWL4030_PM_RECEIVER_VAUX2_DEV_GRP 0x76 2872c155130STom Rix #define TWL4030_PM_RECEIVER_VAUX2_TYPE 0x77 2882c155130STom Rix #define TWL4030_PM_RECEIVER_VAUX2_REMAP 0x78 2892c155130STom Rix #define TWL4030_PM_RECEIVER_VAUX2_DEDICATED 0x79 2902c155130STom Rix #define TWL4030_PM_RECEIVER_VAUX3_DEV_GRP 0x7A 2912c155130STom Rix #define TWL4030_PM_RECEIVER_VAUX3_TYPE 0x7B 2922c155130STom Rix #define TWL4030_PM_RECEIVER_VAUX3_REMAP 0x7C 2932c155130STom Rix #define TWL4030_PM_RECEIVER_VAUX3_DEDICATED 0x7D 2942c155130STom Rix #define TWL4030_PM_RECEIVER_VAUX4_DEV_GRP 0x7E 2952c155130STom Rix #define TWL4030_PM_RECEIVER_VAUX4_TYPE 0x7F 2962c155130STom Rix #define TWL4030_PM_RECEIVER_VAUX4_REMAP 0x80 2972c155130STom Rix #define TWL4030_PM_RECEIVER_VAUX4_DEDICATED 0x81 2982c155130STom Rix #define TWL4030_PM_RECEIVER_VMMC1_DEV_GRP 0x82 2992c155130STom Rix #define TWL4030_PM_RECEIVER_VMMC1_TYPE 0x83 3002c155130STom Rix #define TWL4030_PM_RECEIVER_VMMC1_REMAP 0x84 3012c155130STom Rix #define TWL4030_PM_RECEIVER_VMMC1_DEDICATED 0x85 3022c155130STom Rix #define TWL4030_PM_RECEIVER_VMMC2_DEV_GRP 0x86 3032c155130STom Rix #define TWL4030_PM_RECEIVER_VMMC2_TYPE 0x87 3042c155130STom Rix #define TWL4030_PM_RECEIVER_VMMC2_REMAP 0x88 3052c155130STom Rix #define TWL4030_PM_RECEIVER_VMMC2_DEDICATED 0x89 3062c155130STom Rix #define TWL4030_PM_RECEIVER_VPLL1_DEV_GRP 0x8A 3072c155130STom Rix #define TWL4030_PM_RECEIVER_VPLL1_TYPE 0x8B 3082c155130STom Rix #define TWL4030_PM_RECEIVER_VPLL1_REMAP 0x8C 3092c155130STom Rix #define TWL4030_PM_RECEIVER_VPLL1_DEDICATED 0x8D 3102c155130STom Rix #define TWL4030_PM_RECEIVER_VPLL2_DEV_GRP 0x8E 3112c155130STom Rix #define TWL4030_PM_RECEIVER_VPLL2_TYPE 0x8F 3122c155130STom Rix #define TWL4030_PM_RECEIVER_VPLL2_REMAP 0x90 3132c155130STom Rix #define TWL4030_PM_RECEIVER_VPLL2_DEDICATED 0x91 3142c155130STom Rix #define TWL4030_PM_RECEIVER_VSIM_DEV_GRP 0x92 3152c155130STom Rix #define TWL4030_PM_RECEIVER_VSIM_TYPE 0x93 3162c155130STom Rix #define TWL4030_PM_RECEIVER_VSIM_REMAP 0x94 3172c155130STom Rix #define TWL4030_PM_RECEIVER_VSIM_DEDICATED 0x95 3182c155130STom Rix #define TWL4030_PM_RECEIVER_VDAC_DEV_GRP 0x96 3192c155130STom Rix #define TWL4030_PM_RECEIVER_VDAC_TYPE 0x97 3202c155130STom Rix #define TWL4030_PM_RECEIVER_VDAC_REMAP 0x98 3212c155130STom Rix #define TWL4030_PM_RECEIVER_VDAC_DEDICATED 0x99 3222c155130STom Rix #define TWL4030_PM_RECEIVER_VINTANA1_DEV_GRP 0x9A 3232c155130STom Rix #define TWL4030_PM_RECEIVER_VINTANA1_TYP 0x9B 3242c155130STom Rix #define TWL4030_PM_RECEIVER_VINTANA1_REMAP 0x9C 3252c155130STom Rix #define TWL4030_PM_RECEIVER_VINTANA1_DEDICATED 0x9D 3262c155130STom Rix #define TWL4030_PM_RECEIVER_VINTANA2_DEV_GRP 0x9E 3272c155130STom Rix #define TWL4030_PM_RECEIVER_VINTANA2_TYPE 0x9F 3282c155130STom Rix #define TWL4030_PM_RECEIVER_VINTANA2_REMAP 0xA0 3292c155130STom Rix #define TWL4030_PM_RECEIVER_VINTANA2_DEDICATED 0xA1 3302c155130STom Rix #define TWL4030_PM_RECEIVER_VINTDIG_DEV_GRP 0xA2 3312c155130STom Rix #define TWL4030_PM_RECEIVER_VINTDIG_TYPE 0xA3 3322c155130STom Rix #define TWL4030_PM_RECEIVER_VINTDIG_REMAP 0xA4 3332c155130STom Rix #define TWL4030_PM_RECEIVER_VINTDIG_DEDICATED 0xA5 3342c155130STom Rix #define TWL4030_PM_RECEIVER_VIO_DEV_GRP 0xA6 3352c155130STom Rix #define TWL4030_PM_RECEIVER_VIO_TYPE 0xA7 3362c155130STom Rix #define TWL4030_PM_RECEIVER_VIO_REMAP 0xA8 3372c155130STom Rix #define TWL4030_PM_RECEIVER_VIO_CFG 0xA9 3382c155130STom Rix #define TWL4030_PM_RECEIVER_VIO_MISC_CFG 0xAA 3392c155130STom Rix #define TWL4030_PM_RECEIVER_VIO_TEST1 0xAB 3402c155130STom Rix #define TWL4030_PM_RECEIVER_VIO_TEST2 0xAC 3412c155130STom Rix #define TWL4030_PM_RECEIVER_VIO_OSC 0xAD 3422c155130STom Rix #define TWL4030_PM_RECEIVER_VIO_RESERVED 0xAE 3432c155130STom Rix #define TWL4030_PM_RECEIVER_VIO_VSEL 0xAF 3442c155130STom Rix #define TWL4030_PM_RECEIVER_VDD1_DEV_GRP 0xB0 3452c155130STom Rix #define TWL4030_PM_RECEIVER_VDD1_TYPE 0xB1 3462c155130STom Rix #define TWL4030_PM_RECEIVER_VDD1_REMAP 0xB2 3472c155130STom Rix #define TWL4030_PM_RECEIVER_VDD1_CFG 0xB3 3482c155130STom Rix #define TWL4030_PM_RECEIVER_VDD1_MISC_CFG 0xB4 3492c155130STom Rix #define TWL4030_PM_RECEIVER_VDD1_TEST1 0xB5 3502c155130STom Rix #define TWL4030_PM_RECEIVER_VDD1_TEST2 0xB6 3512c155130STom Rix #define TWL4030_PM_RECEIVER_VDD1_OSC 0xB7 3522c155130STom Rix #define TWL4030_PM_RECEIVER_VDD1_RESERVED 0xB8 3532c155130STom Rix #define TWL4030_PM_RECEIVER_VDD1_VSEL 0xB9 3542c155130STom Rix #define TWL4030_PM_RECEIVER_VDD1_VMODE_CFG 0xBA 3552c155130STom Rix #define TWL4030_PM_RECEIVER_VDD1_VFLOOR 0xBB 3562c155130STom Rix #define TWL4030_PM_RECEIVER_VDD1_VROOF 0xBC 3572c155130STom Rix #define TWL4030_PM_RECEIVER_VDD1_STEP 0xBD 3582c155130STom Rix #define TWL4030_PM_RECEIVER_VDD2_DEV_GRP 0xBE 3592c155130STom Rix #define TWL4030_PM_RECEIVER_VDD2_TYPE 0xBF 3602c155130STom Rix #define TWL4030_PM_RECEIVER_VDD2_REMAP 0xC0 3612c155130STom Rix #define TWL4030_PM_RECEIVER_VDD2_CFG 0xC1 3622c155130STom Rix #define TWL4030_PM_RECEIVER_VDD2_MISC_CFG 0xC2 3632c155130STom Rix #define TWL4030_PM_RECEIVER_VDD2_TEST1 0xC3 3642c155130STom Rix #define TWL4030_PM_RECEIVER_VDD2_TEST2 0xC4 3652c155130STom Rix #define TWL4030_PM_RECEIVER_VDD2_OSC 0xC5 3662c155130STom Rix #define TWL4030_PM_RECEIVER_VDD2_RESERVED 0xC6 3672c155130STom Rix #define TWL4030_PM_RECEIVER_VDD2_VSEL 0xC7 3682c155130STom Rix #define TWL4030_PM_RECEIVER_VDD2_VMODE_CFG 0xC8 3692c155130STom Rix #define TWL4030_PM_RECEIVER_VDD2_VFLOOR 0xC9 3702c155130STom Rix #define TWL4030_PM_RECEIVER_VDD2_VROOF 0xCA 3712c155130STom Rix #define TWL4030_PM_RECEIVER_VDD2_STEP 0xCB 3728966eb4cSTom Rix #define TWL4030_PM_RECEIVER_VUSB1V5_DEV_GRP 0xCC 3738966eb4cSTom Rix #define TWL4030_PM_RECEIVER_VUSB1V5_TYPE 0xCD 3748966eb4cSTom Rix #define TWL4030_PM_RECEIVER_VUSB1V5_REMAP 0xCE 3758966eb4cSTom Rix #define TWL4030_PM_RECEIVER_VUSB1V8_DEV_GRP 0xCF 3768966eb4cSTom Rix #define TWL4030_PM_RECEIVER_VUSB1V8_TYPE 0xD0 3778966eb4cSTom Rix #define TWL4030_PM_RECEIVER_VUSB1V8_REMAP 0xD1 3788966eb4cSTom Rix #define TWL4030_PM_RECEIVER_VUSB3V1_DEV_GRP 0xD2 3798966eb4cSTom Rix #define TWL4030_PM_RECEIVER_VUSB3V1_TYPE 0xD3 3808966eb4cSTom Rix #define TWL4030_PM_RECEIVER_VUSB3V1_REMAP 0xD4 3818966eb4cSTom Rix #define TWL4030_PM_RECEIVER_VUSBCP_DEV_GRP 0xD5 3822c155130STom Rix #define TWL4030_PM_RECEIVER_VUSBCP_TYPE 0xD6 3832c155130STom Rix #define TWL4030_PM_RECEIVER_VUSBCP_REMAP 0xD7 3848966eb4cSTom Rix #define TWL4030_PM_RECEIVER_VUSB_DEDICATED1 0xD8 3858966eb4cSTom Rix #define TWL4030_PM_RECEIVER_VUSB_DEDICATED2 0xD9 3862c155130STom Rix #define TWL4030_PM_RECEIVER_REGEN_DEV_GRP 0xDA 3872c155130STom Rix #define TWL4030_PM_RECEIVER_REGEN_TYPE 0xDB 3882c155130STom Rix #define TWL4030_PM_RECEIVER_REGEN_REMAP 0xDC 3892c155130STom Rix #define TWL4030_PM_RECEIVER_NRESPWRON_DEV_GRP 0xDD 3902c155130STom Rix #define TWL4030_PM_RECEIVER_NRESPWRON_TYPE 0xDE 3912c155130STom Rix #define TWL4030_PM_RECEIVER_NRESPWRON_REMAP 0xDF 3922c155130STom Rix #define TWL4030_PM_RECEIVER_CLKEN_DEV_GRP 0xE0 3932c155130STom Rix #define TWL4030_PM_RECEIVER_CLKEN_TYPE 0xE1 3942c155130STom Rix #define TWL4030_PM_RECEIVER_CLKEN_REMAP 0xE2 3952c155130STom Rix #define TWL4030_PM_RECEIVER_SYSEN_DEV_GRP 0xE3 3962c155130STom Rix #define TWL4030_PM_RECEIVER_SYSEN_TYPE 0xE4 3972c155130STom Rix #define TWL4030_PM_RECEIVER_SYSEN_REMAP 0xE5 3982c155130STom Rix #define TWL4030_PM_RECEIVER_HFCLKOUT_DEV_GRP 0xE6 3992c155130STom Rix #define TWL4030_PM_RECEIVER_HFCLKOUT_TYPE 0xE7 4002c155130STom Rix #define TWL4030_PM_RECEIVER_HFCLKOUT_REMAP 0xE8 4012c155130STom Rix #define TWL4030_PM_RECEIVER_32KCLKOUT_DEV_GRP 0xE9 4022c155130STom Rix #define TWL4030_PM_RECEIVER_32KCLKOUT_TYPE 0xEA 4032c155130STom Rix #define TWL4030_PM_RECEIVER_32KCLKOUT_REMAP 0xEB 4042c155130STom Rix #define TWL4030_PM_RECEIVER_TRITON_RESET_DEV_GRP 0xEC 4052c155130STom Rix #define TWL4030_PM_RECEIVER_TRITON_RESET_TYPE 0xED 4062c155130STom Rix #define TWL4030_PM_RECEIVER_TRITON_RESET_REMAP 0xEE 4072c155130STom Rix #define TWL4030_PM_RECEIVER_MAINREF_DEV_GRP 0xEF 4082c155130STom Rix #define TWL4030_PM_RECEIVER_MAINREF_TYPE 0xF0 4092c155130STom Rix #define TWL4030_PM_RECEIVER_MAINREF_REMAP 0xF1 4102c155130STom Rix 4115a0a82f4SSteve Sakoman /* Voltage Selection in PM Receiver Module */ 4125a0a82f4SSteve Sakoman #define TWL4030_PM_RECEIVER_VAUX2_VSEL_18 0x05 41371bfb0f2SPaul Kocialkowski #define TWL4030_PM_RECEIVER_VAUX2_VSEL_28 0x09 41471bfb0f2SPaul Kocialkowski #define TWL4030_PM_RECEIVER_VAUX3_VSEL_18 0x01 4155a0a82f4SSteve Sakoman #define TWL4030_PM_RECEIVER_VAUX3_VSEL_28 0x03 4165a0a82f4SSteve Sakoman #define TWL4030_PM_RECEIVER_VPLL2_VSEL_18 0x05 4175a0a82f4SSteve Sakoman #define TWL4030_PM_RECEIVER_VDAC_VSEL_18 0x03 4185a0a82f4SSteve Sakoman #define TWL4030_PM_RECEIVER_VMMC1_VSEL_30 0x02 419528cdcaaSAsh Charles #define TWL4030_PM_RECEIVER_VMMC1_VSEL_32 0x03 4202ed8c878SPaul Kocialkowski #define TWL4030_PM_RECEIVER_VMMC2_VSEL_30 0x0B 4212ed8c878SPaul Kocialkowski #define TWL4030_PM_RECEIVER_VMMC2_VSEL_32 0x0C 422318e70e2SPali Rohár #define TWL4030_PM_RECEIVER_VSIM_VSEL_18 0x03 4235a0a82f4SSteve Sakoman 4245a0a82f4SSteve Sakoman /* Device Selection in PM Receiver Module */ 4255a0a82f4SSteve Sakoman #define TWL4030_PM_RECEIVER_DEV_GRP_P1 0x20 4265a0a82f4SSteve Sakoman #define TWL4030_PM_RECEIVER_DEV_GRP_ALL 0xE0 4275a0a82f4SSteve Sakoman 4282c155130STom Rix /* LED */ 4292c155130STom Rix #define TWL4030_LED_LEDEN 0xEE 430ead39d7aSGrazvydas Ignotas #define TWL4030_LED_LEDEN_LEDAON (1 << 0) 431ead39d7aSGrazvydas Ignotas #define TWL4030_LED_LEDEN_LEDBON (1 << 1) 432ead39d7aSGrazvydas Ignotas #define TWL4030_LED_LEDEN_LEDAPWM (1 << 4) 433ead39d7aSGrazvydas Ignotas #define TWL4030_LED_LEDEN_LEDBPWM (1 << 5) 4348966eb4cSTom Rix 4358966eb4cSTom Rix /* Keypad */ 4368966eb4cSTom Rix #define TWL4030_KEYPAD_KEYP_CTRL_REG 0xD2 4378966eb4cSTom Rix #define TWL4030_KEYPAD_KEY_DEB_REG 0xD3 4388966eb4cSTom Rix #define TWL4030_KEYPAD_LONG_KEY_REG1 0xD4 4398966eb4cSTom Rix #define TWL4030_KEYPAD_LK_PTV_REG 0xD5 4408966eb4cSTom Rix #define TWL4030_KEYPAD_TIME_OUT_REG1 0xD6 4418966eb4cSTom Rix #define TWL4030_KEYPAD_TIME_OUT_REG2 0xD7 4428966eb4cSTom Rix #define TWL4030_KEYPAD_KBC_REG 0xD8 4438966eb4cSTom Rix #define TWL4030_KEYPAD_KBR_REG 0xD9 4448966eb4cSTom Rix #define TWL4030_KEYPAD_KEYP_SMS 0xDA 4458966eb4cSTom Rix #define TWL4030_KEYPAD_FULL_CODE_7_0 0xDB 4468966eb4cSTom Rix #define TWL4030_KEYPAD_FULL_CODE_15_8 0xDC 4478966eb4cSTom Rix #define TWL4030_KEYPAD_FULL_CODE_23_16 0xDD 4488966eb4cSTom Rix #define TWL4030_KEYPAD_FULL_CODE_31_24 0xDE 4498966eb4cSTom Rix #define TWL4030_KEYPAD_FULL_CODE_39_32 0xDF 4508966eb4cSTom Rix #define TWL4030_KEYPAD_FULL_CODE_47_40 0xE0 4518966eb4cSTom Rix #define TWL4030_KEYPAD_FULL_CODE_55_48 0xE1 4528966eb4cSTom Rix #define TWL4030_KEYPAD_FULL_CODE_63_56 0xE2 4538966eb4cSTom Rix #define TWL4030_KEYPAD_KEYP_ISR1 0xE3 4548966eb4cSTom Rix #define TWL4030_KEYPAD_KEYP_IMR1 0xE4 4558966eb4cSTom Rix #define TWL4030_KEYPAD_KEYP_ISR2 0xE5 4568966eb4cSTom Rix #define TWL4030_KEYPAD_KEYP_IMR2 0xE6 4578966eb4cSTom Rix #define TWL4030_KEYPAD_KEYP_SIR 0xE7 4588966eb4cSTom Rix #define TWL4030_KEYPAD_KEYP_EDR 0xE8 4598966eb4cSTom Rix #define TWL4030_KEYPAD_KEYP_SIH_CTRL 0xE9 4608966eb4cSTom Rix 4618966eb4cSTom Rix #define TWL4030_KEYPAD_CTRL_KBD_ON (1 << 6) 4628966eb4cSTom Rix #define TWL4030_KEYPAD_CTRL_RP_EN (1 << 5) 4638966eb4cSTom Rix #define TWL4030_KEYPAD_CTRL_TOLE_EN (1 << 4) 4648966eb4cSTom Rix #define TWL4030_KEYPAD_CTRL_TOE_EN (1 << 3) 4658966eb4cSTom Rix #define TWL4030_KEYPAD_CTRL_LK_EN (1 << 2) 4668966eb4cSTom Rix #define TWL4030_KEYPAD_CTRL_SOFTMODEN (1 << 1) 4678966eb4cSTom Rix #define TWL4030_KEYPAD_CTRL_SOFT_NRST (1 << 0) 4688966eb4cSTom Rix 4698966eb4cSTom Rix /* USB */ 470bffbb2a8STom Rix #define TWL4030_USB_VENDOR_ID_LO 0x00 471bffbb2a8STom Rix #define TWL4030_USB_VENDOR_ID_HI 0x01 472bffbb2a8STom Rix #define TWL4030_USB_PRODUCT_ID_LO 0x02 473bffbb2a8STom Rix #define TWL4030_USB_PRODUCT_ID_HI 0x03 474bffbb2a8STom Rix #define TWL4030_USB_FUNC_CTRL 0x04 475bffbb2a8STom Rix #define TWL4030_USB_FUNC_CTRL_SET 0x05 476bffbb2a8STom Rix #define TWL4030_USB_FUNC_CTRL_CLR 0x06 477bffbb2a8STom Rix #define TWL4030_USB_IFC_CTRL 0x07 478bffbb2a8STom Rix #define TWL4030_USB_IFC_CTRL_SET 0x08 479bffbb2a8STom Rix #define TWL4030_USB_IFC_CTRL_CLR 0x09 480bffbb2a8STom Rix #define TWL4030_USB_OTG_CTRL 0x0A 481bffbb2a8STom Rix #define TWL4030_USB_OTG_CTRL_SET 0x0B 482bffbb2a8STom Rix #define TWL4030_USB_OTG_CTRL_CLR 0x0C 483bffbb2a8STom Rix #define TWL4030_USB_USB_INT_EN_RISE 0x0D 484bffbb2a8STom Rix #define TWL4030_USB_USB_INT_EN_RISE_SET 0x0E 485bffbb2a8STom Rix #define TWL4030_USB_USB_INT_EN_RISE_CLR 0x0F 486bffbb2a8STom Rix #define TWL4030_USB_USB_INT_EN_FALL 0x10 487bffbb2a8STom Rix #define TWL4030_USB_USB_INT_EN_FALL_SET 0x11 488bffbb2a8STom Rix #define TWL4030_USB_USB_INT_EN_FALL_CLR 0x12 489bffbb2a8STom Rix #define TWL4030_USB_USB_INT_STS 0x13 490bffbb2a8STom Rix #define TWL4030_USB_USB_INT_LATCH 0x14 491bffbb2a8STom Rix #define TWL4030_USB_DEBUG 0x15 492bffbb2a8STom Rix #define TWL4030_USB_SCRATCH_REG 0x16 493bffbb2a8STom Rix #define TWL4030_USB_SCRATCH_REG_SET 0x17 494bffbb2a8STom Rix #define TWL4030_USB_SCRATCH_REG_CLR 0x18 495bffbb2a8STom Rix #define TWL4030_USB_CARKIT_CTRL 0x19 496bffbb2a8STom Rix #define TWL4030_USB_CARKIT_CTRL_SET 0x1A 497bffbb2a8STom Rix #define TWL4030_USB_CARKIT_CTRL_CLR 0x1B 498bffbb2a8STom Rix #define TWL4030_USB_CARKIT_INT_DELAY 0x1C 499bffbb2a8STom Rix #define TWL4030_USB_CARKIT_INT_EN 0x1D 500bffbb2a8STom Rix #define TWL4030_USB_CARKIT_INT_EN_SET 0x1E 501bffbb2a8STom Rix #define TWL4030_USB_CARKIT_INT_EN_CLR 0x1F 502bffbb2a8STom Rix #define TWL4030_USB_CARKIT_INT_STS 0x20 503bffbb2a8STom Rix #define TWL4030_USB_CARKIT_INT_LATCH 0x21 504bffbb2a8STom Rix #define TWL4030_USB_CARKIT_PLS_CTRL 0x22 505bffbb2a8STom Rix #define TWL4030_USB_CARKIT_PLS_CTRL_SET 0x23 506bffbb2a8STom Rix #define TWL4030_USB_CARKIT_PLS_CTRL_CLR 0x24 507bffbb2a8STom Rix #define TWL4030_USB_TRANS_POS_WIDTH 0x25 508bffbb2a8STom Rix #define TWL4030_USB_TRANS_NEG_WIDTH 0x26 509bffbb2a8STom Rix #define TWL4030_USB_RCV_PLTY_RECOVERY 0x27 510bffbb2a8STom Rix #define TWL4030_USB_MCPC_CTRL 0x30 511bffbb2a8STom Rix #define TWL4030_USB_MCPC_CTRL_SET 0x31 512bffbb2a8STom Rix #define TWL4030_USB_MCPC_CTRL_CLR 0x32 513bffbb2a8STom Rix #define TWL4030_USB_MCPC_IO_CTRL 0x33 514bffbb2a8STom Rix #define TWL4030_USB_MCPC_IO_CTRL_SET 0x34 515bffbb2a8STom Rix #define TWL4030_USB_MCPC_IO_CTRL_CLR 0x35 516bffbb2a8STom Rix #define TWL4030_USB_MCPC_CTRL2 0x36 517bffbb2a8STom Rix #define TWL4030_USB_MCPC_CTRL2_SET 0x37 518bffbb2a8STom Rix #define TWL4030_USB_MCPC_CTRL2_CLR 0x38 519bffbb2a8STom Rix #define TWL4030_USB_OTHER_FUNC_CTRL 0x80 520bffbb2a8STom Rix #define TWL4030_USB_OTHER_FUNC_CTRL_SET 0x81 521bffbb2a8STom Rix #define TWL4030_USB_OTHER_FUNC_CTRL_CLR 0x82 522bffbb2a8STom Rix #define TWL4030_USB_OTHER_IFC_CTRL 0x83 523bffbb2a8STom Rix #define TWL4030_USB_OTHER_IFC_CTRL_SET 0x84 524bffbb2a8STom Rix #define TWL4030_USB_OTHER_IFC_CTRL_CLR 0x85 525bffbb2a8STom Rix #define TWL4030_USB_OTHER_INT_EN_RISE_SET 0x87 526bffbb2a8STom Rix #define TWL4030_USB_OTHER_INT_EN_RISE_CLR 0x88 527bffbb2a8STom Rix #define TWL4030_USB_OTHER_INT_EN_FALL 0x89 528bffbb2a8STom Rix #define TWL4030_USB_OTHER_INT_EN_FALL_SET 0x8A 529bffbb2a8STom Rix #define TWL4030_USB_OTHER_INT_EN_FALL_CLR 0x8B 530bffbb2a8STom Rix #define TWL4030_USB_OTHER_INT_STS 0x8C 531bffbb2a8STom Rix #define TWL4030_USB_OTHER_INT_LATCH 0x8D 532bffbb2a8STom Rix #define TWL4030_USB_ID_STATUS 0x96 533bffbb2a8STom Rix #define TWL4030_USB_CARKIT_SM_1_INT_EN 0x97 534bffbb2a8STom Rix #define TWL4030_USB_CARKIT_SM_1_INT_EN_SET 0x98 535bffbb2a8STom Rix #define TWL4030_USB_CARKIT_SM_1_INT_EN_CLR 0x99 536bffbb2a8STom Rix #define TWL4030_USB_CARKIT_SM_1_INT_STS 0x9A 537bffbb2a8STom Rix #define TWL4030_USB_CARKIT_SM_1_INT_LATCH 0x9B 538bffbb2a8STom Rix #define TWL4030_USB_CARKIT_SM_2_INT_EN 0x9C 539bffbb2a8STom Rix #define TWL4030_USB_CARKIT_SM_2_INT_EN_SET 0x9D 540bffbb2a8STom Rix #define TWL4030_USB_CARKIT_SM_2_INT_EN_CLR 0x9E 541bffbb2a8STom Rix #define TWL4030_USB_CARKIT_SM_2_INT_STS 0x9F 542bffbb2a8STom Rix #define TWL4030_USB_CARKIT_SM_2_INT_LATCH 0xA0 543bffbb2a8STom Rix #define TWL4030_USB_CARKIT_SM_CTRL 0xA1 544bffbb2a8STom Rix #define TWL4030_USB_CARKIT_SM_CTRL_SET 0xA2 545bffbb2a8STom Rix #define TWL4030_USB_CARKIT_SM_CTRL_CLR 0xA3 546bffbb2a8STom Rix #define TWL4030_USB_CARKIT_SM_CMD 0xA4 547bffbb2a8STom Rix #define TWL4030_USB_CARKIT_SM_CMD_SET 0xA5 548bffbb2a8STom Rix #define TWL4030_USB_CARKIT_SM_CMD_CLR 0xA6 549bffbb2a8STom Rix #define TWL4030_USB_CARKIT_SM_CMD_STS 0xA7 550bffbb2a8STom Rix #define TWL4030_USB_CARKIT_SM_STATUS 0xA8 551bffbb2a8STom Rix #define TWL4030_USB_CARKIT_SM_ERR_STATUS 0xAA 552bffbb2a8STom Rix #define TWL4030_USB_CARKIT_SM_CTRL_STATE 0xAB 553bffbb2a8STom Rix #define TWL4030_USB_POWER_CTRL 0xAC 554bffbb2a8STom Rix #define TWL4030_USB_POWER_CTRL_SET 0xAD 555bffbb2a8STom Rix #define TWL4030_USB_POWER_CTRL_CLR 0xAE 556bffbb2a8STom Rix #define TWL4030_USB_OTHER_IFC_CTRL2 0xAF 557bffbb2a8STom Rix #define TWL4030_USB_OTHER_IFC_CTRL2_SET 0xB0 558bffbb2a8STom Rix #define TWL4030_USB_OTHER_IFC_CTRL2_CLR 0xB1 559bffbb2a8STom Rix #define TWL4030_USB_REG_CTRL_EN 0xB2 560bffbb2a8STom Rix #define TWL4030_USB_REG_CTRL_EN_SET 0xB3 561bffbb2a8STom Rix #define TWL4030_USB_REG_CTRL_EN_CLR 0xB4 562bffbb2a8STom Rix #define TWL4030_USB_REG_CTRL_ERROR 0xB5 563bffbb2a8STom Rix #define TWL4030_USB_OTHER_FUNC_CTRL2 0xB8 564bffbb2a8STom Rix #define TWL4030_USB_OTHER_FUNC_CTRL2_SET 0xB9 565bffbb2a8STom Rix #define TWL4030_USB_OTHER_FUNC_CTRL2_CLR 0xBA 566bffbb2a8STom Rix #define TWL4030_USB_CARKIT_ANA_CTRL 0xBB 567bffbb2a8STom Rix #define TWL4030_USB_CARKIT_ANA_CTRL_SET 0xBC 568bffbb2a8STom Rix #define TWL4030_USB_CARKIT_ANA_CTRL_CLR 0xBD 569bffbb2a8STom Rix #define TWL4030_USB_VBUS_DEBOUNCE 0xC0 570bffbb2a8STom Rix #define TWL4030_USB_ID_DEBOUNCE 0xC1 571bffbb2a8STom Rix #define TWL4030_USB_TPH_DP_CON_MIN 0xC2 572bffbb2a8STom Rix #define TWL4030_USB_TPH_DP_CON_MAX 0xC3 573bffbb2a8STom Rix #define TWL4030_USB_TCR_DP_CON_MIN 0xC4 574bffbb2a8STom Rix #define TWL4030_USB_TCR_DP_CON_MAX 0xC5 575bffbb2a8STom Rix #define TWL4030_USB_TPH_DP_PD_SHORT 0xC6 576bffbb2a8STom Rix #define TWL4030_USB_TPH_CMD_DLY 0xC7 577bffbb2a8STom Rix #define TWL4030_USB_TPH_DET_RST 0xC8 578bffbb2a8STom Rix #define TWL4030_USB_TPH_AUD_BIAS 0xC9 579bffbb2a8STom Rix #define TWL4030_USB_TCR_UART_DET_MIN 0xCA 580bffbb2a8STom Rix #define TWL4030_USB_TCR_UART_DET_MAX 0xCB 581bffbb2a8STom Rix #define TWL4030_USB_TPH_ID_INT_PW 0xCD 582bffbb2a8STom Rix #define TWL4030_USB_TACC_ID_INT_WAIT 0xCE 583bffbb2a8STom Rix #define TWL4030_USB_TACC_ID_INT_PW 0xCF 584bffbb2a8STom Rix #define TWL4030_USB_TPH_CMD_WAIT 0xD0 585bffbb2a8STom Rix #define TWL4030_USB_TPH_ACK_WAIT 0xD1 586bffbb2a8STom Rix #define TWL4030_USB_TPH_DP_DISC_DET 0xD2 587bffbb2a8STom Rix #define TWL4030_USB_VBAT_TIMER 0xD3 588bffbb2a8STom Rix #define TWL4030_USB_CARKIT_4W_DEBUG 0xE0 589bffbb2a8STom Rix #define TWL4030_USB_CARKIT_5W_DEBUG 0xE1 590bffbb2a8STom Rix #define TWL4030_USB_PHY_PWR_CTRL 0xFD 591bffbb2a8STom Rix #define TWL4030_USB_PHY_CLK_CTRL 0xFE 592bffbb2a8STom Rix #define TWL4030_USB_PHY_CLK_CTRL_STS 0xFF 5938966eb4cSTom Rix 59441b13bc7SNikita Kiryanov /* GPIO */ 59541b13bc7SNikita Kiryanov #define TWL4030_GPIO_GPIODATAIN1 0x00 59641b13bc7SNikita Kiryanov #define TWL4030_GPIO_GPIODATAIN2 0x01 59741b13bc7SNikita Kiryanov #define TWL4030_GPIO_GPIODATAIN3 0x02 59841b13bc7SNikita Kiryanov #define TWL4030_GPIO_GPIODATADIR1 0x03 59941b13bc7SNikita Kiryanov #define TWL4030_GPIO_GPIODATADIR2 0x04 60041b13bc7SNikita Kiryanov #define TWL4030_GPIO_GPIODATADIR3 0x05 60141b13bc7SNikita Kiryanov #define TWL4030_GPIO_GPIODATAOUT1 0x06 60241b13bc7SNikita Kiryanov #define TWL4030_GPIO_GPIODATAOUT2 0x07 60341b13bc7SNikita Kiryanov #define TWL4030_GPIO_GPIODATAOUT3 0x08 60441b13bc7SNikita Kiryanov #define TWL4030_GPIO_CLEARGPIODATAOUT1 0x09 60541b13bc7SNikita Kiryanov #define TWL4030_GPIO_CLEARGPIODATAOUT2 0x0A 60641b13bc7SNikita Kiryanov #define TWL4030_GPIO_CLEARGPIODATAOUT3 0x0B 60741b13bc7SNikita Kiryanov #define TWL4030_GPIO_SETGPIODATAOUT1 0x0C 60841b13bc7SNikita Kiryanov #define TWL4030_GPIO_SETGPIODATAOUT2 0x0D 60941b13bc7SNikita Kiryanov #define TWL4030_GPIO_SETGPIODATAOUT3 0x0E 61041b13bc7SNikita Kiryanov #define TWL4030_GPIO_GPIO_DEBEN1 0x0F 61141b13bc7SNikita Kiryanov #define TWL4030_GPIO_GPIO_DEBEN2 0x10 61241b13bc7SNikita Kiryanov #define TWL4030_GPIO_GPIO_DEBEN3 0x11 61341b13bc7SNikita Kiryanov #define TWL4030_GPIO_GPIO_CTRL 0x12 61441b13bc7SNikita Kiryanov #define TWL4030_GPIO_GPIOPUPDCTR1 0x13 61541b13bc7SNikita Kiryanov #define TWL4030_GPIO_GPIOPUPDCTR2 0x14 61641b13bc7SNikita Kiryanov #define TWL4030_GPIO_GPIOPUPDCTR3 0x15 61741b13bc7SNikita Kiryanov #define TWL4030_GPIO_GPIOPUPDCTR4 0x16 61841b13bc7SNikita Kiryanov #define TWL4030_GPIO_GPIOPUPDCTR5 0x17 61941b13bc7SNikita Kiryanov #define TWL4030_GPIO_GPIO_ISR1A 0x19 62041b13bc7SNikita Kiryanov #define TWL4030_GPIO_GPIO_ISR2A 0x1A 62141b13bc7SNikita Kiryanov #define TWL4030_GPIO_GPIO_ISR3A 0x1B 62241b13bc7SNikita Kiryanov #define TWL4030_GPIO_GPIO_IMR1A 0x1C 62341b13bc7SNikita Kiryanov #define TWL4030_GPIO_GPIO_IMR2A 0x1D 62441b13bc7SNikita Kiryanov #define TWL4030_GPIO_GPIO_IMR3A 0x1E 62541b13bc7SNikita Kiryanov #define TWL4030_GPIO_GPIO_ISR1B 0x1F 62641b13bc7SNikita Kiryanov #define TWL4030_GPIO_GPIO_ISR2B 0x20 62741b13bc7SNikita Kiryanov #define TWL4030_GPIO_GPIO_ISR3B 0x21 62841b13bc7SNikita Kiryanov #define TWL4030_GPIO_GPIO_IMR1B 0x22 62941b13bc7SNikita Kiryanov #define TWL4030_GPIO_GPIO_IMR2B 0x23 63041b13bc7SNikita Kiryanov #define TWL4030_GPIO_GPIO_IMR3B 0x24 63141b13bc7SNikita Kiryanov #define TWL4030_GPIO_GPIO_EDR1 0x28 63241b13bc7SNikita Kiryanov #define TWL4030_GPIO_GPIO_EDR2 0x29 63341b13bc7SNikita Kiryanov #define TWL4030_GPIO_GPIO_EDR3 0x2A 63441b13bc7SNikita Kiryanov #define TWL4030_GPIO_GPIO_EDR4 0x2B 63541b13bc7SNikita Kiryanov #define TWL4030_GPIO_GPIO_EDR5 0x2C 63641b13bc7SNikita Kiryanov #define TWL4030_GPIO_GPIO_SIH_CTRL 0x2D 63741b13bc7SNikita Kiryanov 6388966eb4cSTom Rix /* 6398966eb4cSTom Rix * Convience functions to read and write from TWL4030 6408966eb4cSTom Rix * 6418966eb4cSTom Rix * chip_no is the i2c address, it must be one of the chip addresses 6428966eb4cSTom Rix * defined at the top of this file with the prefix TWL4030_CHIP_ 6438966eb4cSTom Rix * examples are TWL4030_CHIP_PM_RECEIVER and TWL4030_CHIP_KEYPAD 6448966eb4cSTom Rix * 6458966eb4cSTom Rix * val is the data either written to or read from the twl4030 6468966eb4cSTom Rix * 6478966eb4cSTom Rix * reg is the register to act on, it must be one of the defines 6488966eb4cSTom Rix * above and with the format TWL4030_<chip suffix>_<register name> 6498966eb4cSTom Rix * examples are TWL4030_PM_RECEIVER_VMMC1_DEV_GRP and 6508966eb4cSTom Rix * TWL4030_LED_LEDEN. 6518966eb4cSTom Rix */ 6520208aaf6SNishanth Menon static inline int twl4030_i2c_write_u8(u8 chip_no, u8 reg, u8 val) 6538966eb4cSTom Rix { 6548966eb4cSTom Rix return i2c_write(chip_no, reg, 1, &val, 1); 6558966eb4cSTom Rix } 6568966eb4cSTom Rix 657b29c2f0cSNishanth Menon static inline int twl4030_i2c_read_u8(u8 chip_no, u8 reg, u8 *val) 6588966eb4cSTom Rix { 6598966eb4cSTom Rix return i2c_read(chip_no, reg, 1, val, 1); 6608966eb4cSTom Rix } 6618966eb4cSTom Rix 6622c155130STom Rix /* 6632c155130STom Rix * Power 6642c155130STom Rix */ 6652c155130STom Rix 666cd782635STom Rix /* For hardware resetting */ 667cd782635STom Rix void twl4030_power_reset_init(void); 6686dc443e6SPaul Kocialkowski /* For power off */ 6696dc443e6SPaul Kocialkowski void twl4030_power_off(void); 6705a0a82f4SSteve Sakoman /* For setting device group and voltage */ 6715a0a82f4SSteve Sakoman void twl4030_pmrecv_vsel_cfg(u8 vsel_reg, u8 vsel_val, 6725a0a82f4SSteve Sakoman u8 dev_grp, u8 dev_grp_sel); 6732c155130STom Rix /* For initializing power device */ 6742c155130STom Rix void twl4030_power_init(void); 675fccc0fcaSTom Rix /* For initializing mmc power */ 676f3e85e48SPaul Kocialkowski void twl4030_power_mmc_init(int dev_index); 677fccc0fcaSTom Rix 6782c155130STom Rix /* 679*7d5ac918SPaul Kocialkowski * Input 680*7d5ac918SPaul Kocialkowski */ 681*7d5ac918SPaul Kocialkowski 682*7d5ac918SPaul Kocialkowski int twl4030_input_power_button(void); 683*7d5ac918SPaul Kocialkowski int twl4030_input_charger(void); 684*7d5ac918SPaul Kocialkowski int twl4030_input_usb(void); 685*7d5ac918SPaul Kocialkowski 686*7d5ac918SPaul Kocialkowski /* 6872c155130STom Rix * LED 6882c155130STom Rix */ 689ead39d7aSGrazvydas Ignotas void twl4030_led_init(unsigned char ledon_mask); 690cd782635STom Rix 691bffbb2a8STom Rix /* 692bffbb2a8STom Rix * USB 693bffbb2a8STom Rix */ 694bffbb2a8STom Rix int twl4030_usb_ulpi_init(void); 695bffbb2a8STom Rix 6968966eb4cSTom Rix #endif /* TWL4030_H */ 697