1 /* 2 * tsec.h 3 * 4 * Driver for the Motorola Triple Speed Ethernet Controller 5 * 6 * This software may be used and distributed according to the 7 * terms of the GNU Public License, Version 2, incorporated 8 * herein by reference. 9 * 10 * Copyright 2004, 2007, 2009, 2011, 2013 Freescale Semiconductor, Inc. 11 * (C) Copyright 2003, Motorola, Inc. 12 * maintained by Xianghua Xiao (x.xiao@motorola.com) 13 * author Andy Fleming 14 * 15 */ 16 17 #ifndef __TSEC_H 18 #define __TSEC_H 19 20 #include <net.h> 21 #include <config.h> 22 #include <phy.h> 23 #include <asm/fsl_enet.h> 24 25 #define TSEC_SIZE 0x01000 26 #define TSEC_MDIO_OFFSET 0x01000 27 28 #define CONFIG_SYS_MDIO_BASE_ADDR (MDIO_BASE_ADDR + 0x520) 29 30 #define TSEC_GET_REGS(num, offset) \ 31 (struct tsec __iomem *)\ 32 (TSEC_BASE_ADDR + (((num) - 1) * (offset))) 33 34 #define TSEC_GET_REGS_BASE(num) \ 35 TSEC_GET_REGS((num), TSEC_SIZE) 36 37 #define TSEC_GET_MDIO_REGS(num, offset) \ 38 (struct tsec_mii_mng __iomem *)\ 39 (CONFIG_SYS_MDIO_BASE_ADDR + ((num) - 1) * (offset)) 40 41 #define TSEC_GET_MDIO_REGS_BASE(num) \ 42 TSEC_GET_MDIO_REGS((num), TSEC_MDIO_OFFSET) 43 44 #define DEFAULT_MII_NAME "FSL_MDIO" 45 46 #define STD_TSEC_INFO(num) \ 47 { \ 48 .regs = TSEC_GET_REGS_BASE(num), \ 49 .miiregs_sgmii = TSEC_GET_MDIO_REGS_BASE(num), \ 50 .devname = CONFIG_TSEC##num##_NAME, \ 51 .phyaddr = TSEC##num##_PHY_ADDR, \ 52 .flags = TSEC##num##_FLAGS, \ 53 .mii_devname = DEFAULT_MII_NAME \ 54 } 55 56 #define SET_STD_TSEC_INFO(x, num) \ 57 { \ 58 x.regs = TSEC_GET_REGS_BASE(num); \ 59 x.miiregs_sgmii = TSEC_GET_MDIO_REGS_BASE(num); \ 60 x.devname = CONFIG_TSEC##num##_NAME; \ 61 x.phyaddr = TSEC##num##_PHY_ADDR; \ 62 x.flags = TSEC##num##_FLAGS;\ 63 x.mii_devname = DEFAULT_MII_NAME;\ 64 } 65 66 #define MAC_ADDR_LEN 6 67 68 /* #define TSEC_TIMEOUT 1000000 */ 69 #define TSEC_TIMEOUT 1000 70 #define TOUT_LOOP 1000000 71 72 /* TBI register addresses */ 73 #define TBI_CR 0x00 74 #define TBI_SR 0x01 75 #define TBI_ANA 0x04 76 #define TBI_ANLPBPA 0x05 77 #define TBI_ANEX 0x06 78 #define TBI_TBICON 0x11 79 80 /* TBI MDIO register bit fields*/ 81 #define TBICON_CLK_SELECT 0x0020 82 #define TBIANA_ASYMMETRIC_PAUSE 0x0100 83 #define TBIANA_SYMMETRIC_PAUSE 0x0080 84 #define TBIANA_HALF_DUPLEX 0x0040 85 #define TBIANA_FULL_DUPLEX 0x0020 86 #define TBICR_PHY_RESET 0x8000 87 #define TBICR_ANEG_ENABLE 0x1000 88 #define TBICR_RESTART_ANEG 0x0200 89 #define TBICR_FULL_DUPLEX 0x0100 90 #define TBICR_SPEED1_SET 0x0040 91 92 93 /* MAC register bits */ 94 #define MACCFG1_SOFT_RESET 0x80000000 95 #define MACCFG1_RESET_RX_MC 0x00080000 96 #define MACCFG1_RESET_TX_MC 0x00040000 97 #define MACCFG1_RESET_RX_FUN 0x00020000 98 #define MACCFG1_RESET_TX_FUN 0x00010000 99 #define MACCFG1_LOOPBACK 0x00000100 100 #define MACCFG1_RX_FLOW 0x00000020 101 #define MACCFG1_TX_FLOW 0x00000010 102 #define MACCFG1_SYNCD_RX_EN 0x00000008 103 #define MACCFG1_RX_EN 0x00000004 104 #define MACCFG1_SYNCD_TX_EN 0x00000002 105 #define MACCFG1_TX_EN 0x00000001 106 107 #define MACCFG2_INIT_SETTINGS 0x00007205 108 #define MACCFG2_FULL_DUPLEX 0x00000001 109 #define MACCFG2_IF 0x00000300 110 #define MACCFG2_GMII 0x00000200 111 #define MACCFG2_MII 0x00000100 112 113 #define ECNTRL_INIT_SETTINGS 0x00001000 114 #define ECNTRL_TBI_MODE 0x00000020 115 #define ECNTRL_REDUCED_MODE 0x00000010 116 #define ECNTRL_R100 0x00000008 117 #define ECNTRL_REDUCED_MII_MODE 0x00000004 118 #define ECNTRL_SGMII_MODE 0x00000002 119 120 #ifndef CONFIG_SYS_TBIPA_VALUE 121 #define CONFIG_SYS_TBIPA_VALUE 0x1f 122 #endif 123 124 #define MRBLR_INIT_SETTINGS PKTSIZE_ALIGN 125 126 #define MINFLR_INIT_SETTINGS 0x00000040 127 128 #define DMACTRL_INIT_SETTINGS 0x000000c3 129 #define DMACTRL_GRS 0x00000010 130 #define DMACTRL_GTS 0x00000008 131 132 #define TSTAT_CLEAR_THALT 0x80000000 133 #define RSTAT_CLEAR_RHALT 0x00800000 134 135 136 #define IEVENT_INIT_CLEAR 0xffffffff 137 #define IEVENT_BABR 0x80000000 138 #define IEVENT_RXC 0x40000000 139 #define IEVENT_BSY 0x20000000 140 #define IEVENT_EBERR 0x10000000 141 #define IEVENT_MSRO 0x04000000 142 #define IEVENT_GTSC 0x02000000 143 #define IEVENT_BABT 0x01000000 144 #define IEVENT_TXC 0x00800000 145 #define IEVENT_TXE 0x00400000 146 #define IEVENT_TXB 0x00200000 147 #define IEVENT_TXF 0x00100000 148 #define IEVENT_IE 0x00080000 149 #define IEVENT_LC 0x00040000 150 #define IEVENT_CRL 0x00020000 151 #define IEVENT_XFUN 0x00010000 152 #define IEVENT_RXB0 0x00008000 153 #define IEVENT_GRSC 0x00000100 154 #define IEVENT_RXF0 0x00000080 155 156 #define IMASK_INIT_CLEAR 0x00000000 157 #define IMASK_TXEEN 0x00400000 158 #define IMASK_TXBEN 0x00200000 159 #define IMASK_TXFEN 0x00100000 160 #define IMASK_RXFEN0 0x00000080 161 162 163 /* Default Attribute fields */ 164 #define ATTR_INIT_SETTINGS 0x000000c0 165 #define ATTRELI_INIT_SETTINGS 0x00000000 166 167 168 /* TxBD status field bits */ 169 #define TXBD_READY 0x8000 170 #define TXBD_PADCRC 0x4000 171 #define TXBD_WRAP 0x2000 172 #define TXBD_INTERRUPT 0x1000 173 #define TXBD_LAST 0x0800 174 #define TXBD_CRC 0x0400 175 #define TXBD_DEF 0x0200 176 #define TXBD_HUGEFRAME 0x0080 177 #define TXBD_LATECOLLISION 0x0080 178 #define TXBD_RETRYLIMIT 0x0040 179 #define TXBD_RETRYCOUNTMASK 0x003c 180 #define TXBD_UNDERRUN 0x0002 181 #define TXBD_STATS 0x03ff 182 183 /* RxBD status field bits */ 184 #define RXBD_EMPTY 0x8000 185 #define RXBD_RO1 0x4000 186 #define RXBD_WRAP 0x2000 187 #define RXBD_INTERRUPT 0x1000 188 #define RXBD_LAST 0x0800 189 #define RXBD_FIRST 0x0400 190 #define RXBD_MISS 0x0100 191 #define RXBD_BROADCAST 0x0080 192 #define RXBD_MULTICAST 0x0040 193 #define RXBD_LARGE 0x0020 194 #define RXBD_NONOCTET 0x0010 195 #define RXBD_SHORT 0x0008 196 #define RXBD_CRCERR 0x0004 197 #define RXBD_OVERRUN 0x0002 198 #define RXBD_TRUNCATED 0x0001 199 #define RXBD_STATS 0x003f 200 201 typedef struct txbd8 202 { 203 ushort status; /* Status Fields */ 204 ushort length; /* Buffer length */ 205 uint bufPtr; /* Buffer Pointer */ 206 } txbd8_t; 207 208 typedef struct rxbd8 209 { 210 ushort status; /* Status Fields */ 211 ushort length; /* Buffer Length */ 212 uint bufPtr; /* Buffer Pointer */ 213 } rxbd8_t; 214 215 typedef struct rmon_mib 216 { 217 /* Transmit and Receive Counters */ 218 uint tr64; /* Transmit and Receive 64-byte Frame Counter */ 219 uint tr127; /* Transmit and Receive 65-127 byte Frame Counter */ 220 uint tr255; /* Transmit and Receive 128-255 byte Frame Counter */ 221 uint tr511; /* Transmit and Receive 256-511 byte Frame Counter */ 222 uint tr1k; /* Transmit and Receive 512-1023 byte Frame Counter */ 223 uint trmax; /* Transmit and Receive 1024-1518 byte Frame Counter */ 224 uint trmgv; /* Transmit and Receive 1519-1522 byte Good VLAN Frame */ 225 /* Receive Counters */ 226 uint rbyt; /* Receive Byte Counter */ 227 uint rpkt; /* Receive Packet Counter */ 228 uint rfcs; /* Receive FCS Error Counter */ 229 uint rmca; /* Receive Multicast Packet (Counter) */ 230 uint rbca; /* Receive Broadcast Packet */ 231 uint rxcf; /* Receive Control Frame Packet */ 232 uint rxpf; /* Receive Pause Frame Packet */ 233 uint rxuo; /* Receive Unknown OP Code */ 234 uint raln; /* Receive Alignment Error */ 235 uint rflr; /* Receive Frame Length Error */ 236 uint rcde; /* Receive Code Error */ 237 uint rcse; /* Receive Carrier Sense Error */ 238 uint rund; /* Receive Undersize Packet */ 239 uint rovr; /* Receive Oversize Packet */ 240 uint rfrg; /* Receive Fragments */ 241 uint rjbr; /* Receive Jabber */ 242 uint rdrp; /* Receive Drop */ 243 /* Transmit Counters */ 244 uint tbyt; /* Transmit Byte Counter */ 245 uint tpkt; /* Transmit Packet */ 246 uint tmca; /* Transmit Multicast Packet */ 247 uint tbca; /* Transmit Broadcast Packet */ 248 uint txpf; /* Transmit Pause Control Frame */ 249 uint tdfr; /* Transmit Deferral Packet */ 250 uint tedf; /* Transmit Excessive Deferral Packet */ 251 uint tscl; /* Transmit Single Collision Packet */ 252 /* (0x2_n700) */ 253 uint tmcl; /* Transmit Multiple Collision Packet */ 254 uint tlcl; /* Transmit Late Collision Packet */ 255 uint txcl; /* Transmit Excessive Collision Packet */ 256 uint tncl; /* Transmit Total Collision */ 257 258 uint res2; 259 260 uint tdrp; /* Transmit Drop Frame */ 261 uint tjbr; /* Transmit Jabber Frame */ 262 uint tfcs; /* Transmit FCS Error */ 263 uint txcf; /* Transmit Control Frame */ 264 uint tovr; /* Transmit Oversize Frame */ 265 uint tund; /* Transmit Undersize Frame */ 266 uint tfrg; /* Transmit Fragments Frame */ 267 /* General Registers */ 268 uint car1; /* Carry Register One */ 269 uint car2; /* Carry Register Two */ 270 uint cam1; /* Carry Register One Mask */ 271 uint cam2; /* Carry Register Two Mask */ 272 } rmon_mib_t; 273 274 typedef struct tsec_hash_regs 275 { 276 uint iaddr0; /* Individual Address Register 0 */ 277 uint iaddr1; /* Individual Address Register 1 */ 278 uint iaddr2; /* Individual Address Register 2 */ 279 uint iaddr3; /* Individual Address Register 3 */ 280 uint iaddr4; /* Individual Address Register 4 */ 281 uint iaddr5; /* Individual Address Register 5 */ 282 uint iaddr6; /* Individual Address Register 6 */ 283 uint iaddr7; /* Individual Address Register 7 */ 284 uint res1[24]; 285 uint gaddr0; /* Group Address Register 0 */ 286 uint gaddr1; /* Group Address Register 1 */ 287 uint gaddr2; /* Group Address Register 2 */ 288 uint gaddr3; /* Group Address Register 3 */ 289 uint gaddr4; /* Group Address Register 4 */ 290 uint gaddr5; /* Group Address Register 5 */ 291 uint gaddr6; /* Group Address Register 6 */ 292 uint gaddr7; /* Group Address Register 7 */ 293 uint res2[24]; 294 } tsec_hash_t; 295 296 struct tsec { 297 /* General Control and Status Registers (0x2_n000) */ 298 uint res000[4]; 299 300 uint ievent; /* Interrupt Event */ 301 uint imask; /* Interrupt Mask */ 302 uint edis; /* Error Disabled */ 303 uint res01c; 304 uint ecntrl; /* Ethernet Control */ 305 uint minflr; /* Minimum Frame Length */ 306 uint ptv; /* Pause Time Value */ 307 uint dmactrl; /* DMA Control */ 308 uint tbipa; /* TBI PHY Address */ 309 310 uint res034[3]; 311 uint res040[48]; 312 313 /* Transmit Control and Status Registers (0x2_n100) */ 314 uint tctrl; /* Transmit Control */ 315 uint tstat; /* Transmit Status */ 316 uint res108; 317 uint tbdlen; /* Tx BD Data Length */ 318 uint res110[5]; 319 uint ctbptr; /* Current TxBD Pointer */ 320 uint res128[23]; 321 uint tbptr; /* TxBD Pointer */ 322 uint res188[30]; 323 /* (0x2_n200) */ 324 uint res200; 325 uint tbase; /* TxBD Base Address */ 326 uint res208[42]; 327 uint ostbd; /* Out of Sequence TxBD */ 328 uint ostbdp; /* Out of Sequence Tx Data Buffer Pointer */ 329 uint res2b8[18]; 330 331 /* Receive Control and Status Registers (0x2_n300) */ 332 uint rctrl; /* Receive Control */ 333 uint rstat; /* Receive Status */ 334 uint res308; 335 uint rbdlen; /* RxBD Data Length */ 336 uint res310[4]; 337 uint res320; 338 uint crbptr; /* Current Receive Buffer Pointer */ 339 uint res328[6]; 340 uint mrblr; /* Maximum Receive Buffer Length */ 341 uint res344[16]; 342 uint rbptr; /* RxBD Pointer */ 343 uint res388[30]; 344 /* (0x2_n400) */ 345 uint res400; 346 uint rbase; /* RxBD Base Address */ 347 uint res408[62]; 348 349 /* MAC Registers (0x2_n500) */ 350 uint maccfg1; /* MAC Configuration #1 */ 351 uint maccfg2; /* MAC Configuration #2 */ 352 uint ipgifg; /* Inter Packet Gap/Inter Frame Gap */ 353 uint hafdup; /* Half-duplex */ 354 uint maxfrm; /* Maximum Frame */ 355 uint res514; 356 uint res518; 357 358 uint res51c; 359 360 uint resmdio[6]; 361 362 uint res538; 363 364 uint ifstat; /* Interface Status */ 365 uint macstnaddr1; /* Station Address, part 1 */ 366 uint macstnaddr2; /* Station Address, part 2 */ 367 uint res548[46]; 368 369 /* (0x2_n600) */ 370 uint res600[32]; 371 372 /* RMON MIB Registers (0x2_n680-0x2_n73c) */ 373 rmon_mib_t rmon; 374 uint res740[48]; 375 376 /* Hash Function Registers (0x2_n800) */ 377 tsec_hash_t hash; 378 379 uint res900[128]; 380 381 /* Pattern Registers (0x2_nb00) */ 382 uint resb00[62]; 383 uint attr; /* Default Attribute Register */ 384 uint attreli; /* Default Attribute Extract Length and Index */ 385 386 /* TSEC Future Expansion Space (0x2_nc00-0x2_nffc) */ 387 uint resc00[256]; 388 }; 389 390 #define TSEC_GIGABIT (1 << 0) 391 392 /* These flags currently only have meaning if we're using the eTSEC */ 393 #define TSEC_REDUCED (1 << 1) /* MAC-PHY interface uses RGMII */ 394 #define TSEC_SGMII (1 << 2) /* MAC-PHY interface uses SGMII */ 395 396 struct tsec_private { 397 struct tsec __iomem *regs; 398 struct tsec_mii_mng __iomem *phyregs_sgmii; 399 struct phy_device *phydev; 400 phy_interface_t interface; 401 struct mii_dev *bus; 402 uint phyaddr; 403 char mii_devname[16]; 404 u32 flags; 405 }; 406 407 struct tsec_info_struct { 408 struct tsec __iomem *regs; 409 struct tsec_mii_mng __iomem *miiregs_sgmii; 410 char *devname; 411 char *mii_devname; 412 phy_interface_t interface; 413 unsigned int phyaddr; 414 u32 flags; 415 }; 416 417 int tsec_standard_init(bd_t *bis); 418 int tsec_eth_init(bd_t *bis, struct tsec_info_struct *tsec_info, int num); 419 420 #endif /* __TSEC_H */ 421