1 /* 2 * tsec.h 3 * 4 * Driver for the Motorola Triple Speed Ethernet Controller 5 * 6 * This software may be used and distributed according to the 7 * terms of the GNU Public License, Version 2, incorporated 8 * herein by reference. 9 * 10 * Copyright 2004, 2007 Freescale Semiconductor, Inc. 11 * (C) Copyright 2003, Motorola, Inc. 12 * maintained by Xianghua Xiao (x.xiao@motorola.com) 13 * author Andy Fleming 14 * 15 */ 16 17 #ifndef __TSEC_H 18 #define __TSEC_H 19 20 #include <net.h> 21 #include <config.h> 22 23 #ifndef CFG_TSEC1_OFFSET 24 #define CFG_TSEC1_OFFSET (0x24000) 25 #endif 26 27 #define TSEC_SIZE 0x01000 28 29 /* FIXME: Should these be pushed back to 83xx and 85xx config files? */ 30 #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) \ 31 || defined(CONFIG_MPC83XX) 32 #define TSEC_BASE_ADDR (CFG_IMMR + CFG_TSEC1_OFFSET) 33 #endif 34 35 #define STD_TSEC_INFO(num) \ 36 { \ 37 .regs = (tsec_t *)(TSEC_BASE_ADDR + ((num - 1) * TSEC_SIZE)), \ 38 .miiregs = (tsec_t *)TSEC_BASE_ADDR, \ 39 .devname = CONFIG_TSEC##num##_NAME, \ 40 .phyaddr = TSEC##num##_PHY_ADDR, \ 41 .flags = TSEC##num##_FLAGS \ 42 } 43 44 #define SET_STD_TSEC_INFO(x, num) \ 45 { \ 46 x.regs = (tsec_t *)(TSEC_BASE_ADDR + ((num - 1) * TSEC_SIZE)); \ 47 x.miiregs = (tsec_t *)TSEC_BASE_ADDR; \ 48 x.devname = CONFIG_TSEC##num##_NAME; \ 49 x.phyaddr = TSEC##num##_PHY_ADDR; \ 50 x.flags = TSEC##num##_FLAGS;\ 51 } 52 53 54 55 #define MAC_ADDR_LEN 6 56 57 /* #define TSEC_TIMEOUT 1000000 */ 58 #define TSEC_TIMEOUT 1000 59 #define TOUT_LOOP 1000000 60 61 #define PHY_AUTONEGOTIATE_TIMEOUT 5000 /* in ms */ 62 63 /* MAC register bits */ 64 #define MACCFG1_SOFT_RESET 0x80000000 65 #define MACCFG1_RESET_RX_MC 0x00080000 66 #define MACCFG1_RESET_TX_MC 0x00040000 67 #define MACCFG1_RESET_RX_FUN 0x00020000 68 #define MACCFG1_RESET_TX_FUN 0x00010000 69 #define MACCFG1_LOOPBACK 0x00000100 70 #define MACCFG1_RX_FLOW 0x00000020 71 #define MACCFG1_TX_FLOW 0x00000010 72 #define MACCFG1_SYNCD_RX_EN 0x00000008 73 #define MACCFG1_RX_EN 0x00000004 74 #define MACCFG1_SYNCD_TX_EN 0x00000002 75 #define MACCFG1_TX_EN 0x00000001 76 77 #define MACCFG2_INIT_SETTINGS 0x00007205 78 #define MACCFG2_FULL_DUPLEX 0x00000001 79 #define MACCFG2_IF 0x00000300 80 #define MACCFG2_GMII 0x00000200 81 #define MACCFG2_MII 0x00000100 82 83 #define ECNTRL_INIT_SETTINGS 0x00001000 84 #define ECNTRL_TBI_MODE 0x00000020 85 #define ECNTRL_R100 0x00000008 86 #define ECNTRL_SGMII_MODE 0x00000002 87 88 #define miim_end -2 89 #define miim_read -1 90 91 #ifndef CFG_TBIPA_VALUE 92 #define CFG_TBIPA_VALUE 0x1f 93 #endif 94 #define MIIMCFG_INIT_VALUE 0x00000003 95 #define MIIMCFG_RESET 0x80000000 96 97 #define MIIMIND_BUSY 0x00000001 98 #define MIIMIND_NOTVALID 0x00000004 99 100 #define MIIM_CONTROL 0x00 101 #define MIIM_CONTROL_RESET 0x00009140 102 #define MIIM_CONTROL_INIT 0x00001140 103 #define MIIM_CONTROL_RESTART 0x00001340 104 #define MIIM_ANEN 0x00001000 105 106 #define MIIM_CR 0x00 107 #define MIIM_CR_RST 0x00008000 108 #define MIIM_CR_INIT 0x00001000 109 110 #define MIIM_STATUS 0x1 111 #define MIIM_STATUS_AN_DONE 0x00000020 112 #define MIIM_STATUS_LINK 0x0004 113 #define PHY_BMSR_AUTN_ABLE 0x0008 114 #define PHY_BMSR_AUTN_COMP 0x0020 115 116 #define MIIM_PHYIR1 0x2 117 #define MIIM_PHYIR2 0x3 118 119 #define MIIM_ANAR 0x4 120 #define MIIM_ANAR_INIT 0x1e1 121 122 #define MIIM_TBI_ANLPBPA 0x5 123 #define MIIM_TBI_ANLPBPA_HALF 0x00000040 124 #define MIIM_TBI_ANLPBPA_FULL 0x00000020 125 126 #define MIIM_TBI_ANEX 0x6 127 #define MIIM_TBI_ANEX_NP 0x00000004 128 #define MIIM_TBI_ANEX_PRX 0x00000002 129 130 #define MIIM_GBIT_CONTROL 0x9 131 #define MIIM_GBIT_CONTROL_INIT 0xe00 132 133 #define MIIM_EXT_PAGE_ACCESS 0x1f 134 135 /* Broadcom BCM54xx -- taken from linux sungem_phy */ 136 #define MIIM_BCM54xx_AUXSTATUS 0x19 137 #define MIIM_BCM54xx_AUXSTATUS_LINKMODE_MASK 0x0700 138 #define MIIM_BCM54xx_AUXSTATUS_LINKMODE_SHIFT 8 139 140 /* Cicada Auxiliary Control/Status Register */ 141 #define MIIM_CIS8201_AUX_CONSTAT 0x1c 142 #define MIIM_CIS8201_AUXCONSTAT_INIT 0x0004 143 #define MIIM_CIS8201_AUXCONSTAT_DUPLEX 0x0020 144 #define MIIM_CIS8201_AUXCONSTAT_SPEED 0x0018 145 #define MIIM_CIS8201_AUXCONSTAT_GBIT 0x0010 146 #define MIIM_CIS8201_AUXCONSTAT_100 0x0008 147 148 /* Cicada Extended Control Register 1 */ 149 #define MIIM_CIS8201_EXT_CON1 0x17 150 #define MIIM_CIS8201_EXTCON1_INIT 0x0000 151 152 /* Cicada 8204 Extended PHY Control Register 1 */ 153 #define MIIM_CIS8204_EPHY_CON 0x17 154 #define MIIM_CIS8204_EPHYCON_INIT 0x0006 155 #define MIIM_CIS8204_EPHYCON_RGMII 0x1100 156 157 /* Cicada 8204 Serial LED Control Register */ 158 #define MIIM_CIS8204_SLED_CON 0x1b 159 #define MIIM_CIS8204_SLEDCON_INIT 0x1115 160 161 #define MIIM_GBIT_CON 0x09 162 #define MIIM_GBIT_CON_ADVERT 0x0e00 163 164 /* Entry for Vitesse VSC8244 regs starts here */ 165 /* Vitesse VSC8244 Auxiliary Control/Status Register */ 166 #define MIIM_VSC8244_AUX_CONSTAT 0x1c 167 #define MIIM_VSC8244_AUXCONSTAT_INIT 0x0000 168 #define MIIM_VSC8244_AUXCONSTAT_DUPLEX 0x0020 169 #define MIIM_VSC8244_AUXCONSTAT_SPEED 0x0018 170 #define MIIM_VSC8244_AUXCONSTAT_GBIT 0x0010 171 #define MIIM_VSC8244_AUXCONSTAT_100 0x0008 172 #define MIIM_CONTROL_INIT_LOOPBACK 0x4000 173 174 /* Vitesse VSC8244 Extended PHY Control Register 1 */ 175 #define MIIM_VSC8244_EPHY_CON 0x17 176 #define MIIM_VSC8244_EPHYCON_INIT 0x0006 177 178 /* Vitesse VSC8244 Serial LED Control Register */ 179 #define MIIM_VSC8244_LED_CON 0x1b 180 #define MIIM_VSC8244_LEDCON_INIT 0xF011 181 182 /* Entry for Vitesse VSC8601 regs starts here (Not complete) */ 183 /* Vitesse VSC8601 Extended PHY Control Register 1 */ 184 #define MIIM_VSC8601_EPHY_CON 0x17 185 #define MIIM_VSC8601_EPHY_CON_INIT_SKEW 0x1120 186 #define MIIM_VSC8601_SKEW_CTRL 0x1c 187 188 /* 88E1011 PHY Status Register */ 189 #define MIIM_88E1011_PHY_STATUS 0x11 190 #define MIIM_88E1011_PHYSTAT_SPEED 0xc000 191 #define MIIM_88E1011_PHYSTAT_GBIT 0x8000 192 #define MIIM_88E1011_PHYSTAT_100 0x4000 193 #define MIIM_88E1011_PHYSTAT_DUPLEX 0x2000 194 #define MIIM_88E1011_PHYSTAT_SPDDONE 0x0800 195 #define MIIM_88E1011_PHYSTAT_LINK 0x0400 196 197 #define MIIM_88E1011_PHY_SCR 0x10 198 #define MIIM_88E1011_PHY_MDI_X_AUTO 0x0060 199 200 /* 88E1111 PHY LED Control Register */ 201 #define MIIM_88E1111_PHY_LED_CONTROL 24 202 #define MIIM_88E1111_PHY_LED_DIRECT 0x4100 203 #define MIIM_88E1111_PHY_LED_COMBINE 0x411C 204 205 /* 88E1121 PHY LED Control Register */ 206 #define MIIM_88E1121_PHY_LED_CTRL 16 207 #define MIIM_88E1121_PHY_LED_PAGE 3 208 #define MIIM_88E1121_PHY_LED_DEF 0x0030 209 210 #define MIIM_88E1121_PHY_PAGE 22 211 212 /* 88E1145 Extended PHY Specific Control Register */ 213 #define MIIM_88E1145_PHY_EXT_CR 20 214 #define MIIM_M88E1145_RGMII_RX_DELAY 0x0080 215 #define MIIM_M88E1145_RGMII_TX_DELAY 0x0002 216 217 #define MIIM_88E1145_PHY_PAGE 29 218 #define MIIM_88E1145_PHY_CAL_OV 30 219 220 /* RTL8211B PHY Status Register */ 221 #define MIIM_RTL8211B_PHY_STATUS 0x11 222 #define MIIM_RTL8211B_PHYSTAT_SPEED 0xc000 223 #define MIIM_RTL8211B_PHYSTAT_GBIT 0x8000 224 #define MIIM_RTL8211B_PHYSTAT_100 0x4000 225 #define MIIM_RTL8211B_PHYSTAT_DUPLEX 0x2000 226 #define MIIM_RTL8211B_PHYSTAT_SPDDONE 0x0800 227 #define MIIM_RTL8211B_PHYSTAT_LINK 0x0400 228 229 /* DM9161 Control register values */ 230 #define MIIM_DM9161_CR_STOP 0x0400 231 #define MIIM_DM9161_CR_RSTAN 0x1200 232 233 #define MIIM_DM9161_SCR 0x10 234 #define MIIM_DM9161_SCR_INIT 0x0610 235 236 /* DM9161 Specified Configuration and Status Register */ 237 #define MIIM_DM9161_SCSR 0x11 238 #define MIIM_DM9161_SCSR_100F 0x8000 239 #define MIIM_DM9161_SCSR_100H 0x4000 240 #define MIIM_DM9161_SCSR_10F 0x2000 241 #define MIIM_DM9161_SCSR_10H 0x1000 242 243 /* DM9161 10BT Configuration/Status */ 244 #define MIIM_DM9161_10BTCSR 0x12 245 #define MIIM_DM9161_10BTCSR_INIT 0x7800 246 247 /* LXT971 Status 2 registers */ 248 #define MIIM_LXT971_SR2 0x11 /* Status Register 2 */ 249 #define MIIM_LXT971_SR2_SPEED_MASK 0x4200 250 #define MIIM_LXT971_SR2_10HDX 0x0000 /* 10 Mbit half duplex selected */ 251 #define MIIM_LXT971_SR2_10FDX 0x0200 /* 10 Mbit full duplex selected */ 252 #define MIIM_LXT971_SR2_100HDX 0x4000 /* 100 Mbit half duplex selected */ 253 #define MIIM_LXT971_SR2_100FDX 0x4200 /* 100 Mbit full duplex selected */ 254 255 /* DP83865 Control register values */ 256 #define MIIM_DP83865_CR_INIT 0x9200 257 258 /* DP83865 Link and Auto-Neg Status Register */ 259 #define MIIM_DP83865_LANR 0x11 260 #define MIIM_DP83865_SPD_MASK 0x0018 261 #define MIIM_DP83865_SPD_1000 0x0010 262 #define MIIM_DP83865_SPD_100 0x0008 263 #define MIIM_DP83865_DPX_FULL 0x0002 264 265 #define MIIM_READ_COMMAND 0x00000001 266 267 #define MRBLR_INIT_SETTINGS PKTSIZE_ALIGN 268 269 #define MINFLR_INIT_SETTINGS 0x00000040 270 271 #define DMACTRL_INIT_SETTINGS 0x000000c3 272 #define DMACTRL_GRS 0x00000010 273 #define DMACTRL_GTS 0x00000008 274 275 #define TSTAT_CLEAR_THALT 0x80000000 276 #define RSTAT_CLEAR_RHALT 0x00800000 277 278 279 #define IEVENT_INIT_CLEAR 0xffffffff 280 #define IEVENT_BABR 0x80000000 281 #define IEVENT_RXC 0x40000000 282 #define IEVENT_BSY 0x20000000 283 #define IEVENT_EBERR 0x10000000 284 #define IEVENT_MSRO 0x04000000 285 #define IEVENT_GTSC 0x02000000 286 #define IEVENT_BABT 0x01000000 287 #define IEVENT_TXC 0x00800000 288 #define IEVENT_TXE 0x00400000 289 #define IEVENT_TXB 0x00200000 290 #define IEVENT_TXF 0x00100000 291 #define IEVENT_IE 0x00080000 292 #define IEVENT_LC 0x00040000 293 #define IEVENT_CRL 0x00020000 294 #define IEVENT_XFUN 0x00010000 295 #define IEVENT_RXB0 0x00008000 296 #define IEVENT_GRSC 0x00000100 297 #define IEVENT_RXF0 0x00000080 298 299 #define IMASK_INIT_CLEAR 0x00000000 300 #define IMASK_TXEEN 0x00400000 301 #define IMASK_TXBEN 0x00200000 302 #define IMASK_TXFEN 0x00100000 303 #define IMASK_RXFEN0 0x00000080 304 305 306 /* Default Attribute fields */ 307 #define ATTR_INIT_SETTINGS 0x000000c0 308 #define ATTRELI_INIT_SETTINGS 0x00000000 309 310 311 /* TxBD status field bits */ 312 #define TXBD_READY 0x8000 313 #define TXBD_PADCRC 0x4000 314 #define TXBD_WRAP 0x2000 315 #define TXBD_INTERRUPT 0x1000 316 #define TXBD_LAST 0x0800 317 #define TXBD_CRC 0x0400 318 #define TXBD_DEF 0x0200 319 #define TXBD_HUGEFRAME 0x0080 320 #define TXBD_LATECOLLISION 0x0080 321 #define TXBD_RETRYLIMIT 0x0040 322 #define TXBD_RETRYCOUNTMASK 0x003c 323 #define TXBD_UNDERRUN 0x0002 324 #define TXBD_STATS 0x03ff 325 326 /* RxBD status field bits */ 327 #define RXBD_EMPTY 0x8000 328 #define RXBD_RO1 0x4000 329 #define RXBD_WRAP 0x2000 330 #define RXBD_INTERRUPT 0x1000 331 #define RXBD_LAST 0x0800 332 #define RXBD_FIRST 0x0400 333 #define RXBD_MISS 0x0100 334 #define RXBD_BROADCAST 0x0080 335 #define RXBD_MULTICAST 0x0040 336 #define RXBD_LARGE 0x0020 337 #define RXBD_NONOCTET 0x0010 338 #define RXBD_SHORT 0x0008 339 #define RXBD_CRCERR 0x0004 340 #define RXBD_OVERRUN 0x0002 341 #define RXBD_TRUNCATED 0x0001 342 #define RXBD_STATS 0x003f 343 344 typedef struct txbd8 345 { 346 ushort status; /* Status Fields */ 347 ushort length; /* Buffer length */ 348 uint bufPtr; /* Buffer Pointer */ 349 } txbd8_t; 350 351 typedef struct rxbd8 352 { 353 ushort status; /* Status Fields */ 354 ushort length; /* Buffer Length */ 355 uint bufPtr; /* Buffer Pointer */ 356 } rxbd8_t; 357 358 typedef struct rmon_mib 359 { 360 /* Transmit and Receive Counters */ 361 uint tr64; /* Transmit and Receive 64-byte Frame Counter */ 362 uint tr127; /* Transmit and Receive 65-127 byte Frame Counter */ 363 uint tr255; /* Transmit and Receive 128-255 byte Frame Counter */ 364 uint tr511; /* Transmit and Receive 256-511 byte Frame Counter */ 365 uint tr1k; /* Transmit and Receive 512-1023 byte Frame Counter */ 366 uint trmax; /* Transmit and Receive 1024-1518 byte Frame Counter */ 367 uint trmgv; /* Transmit and Receive 1519-1522 byte Good VLAN Frame */ 368 /* Receive Counters */ 369 uint rbyt; /* Receive Byte Counter */ 370 uint rpkt; /* Receive Packet Counter */ 371 uint rfcs; /* Receive FCS Error Counter */ 372 uint rmca; /* Receive Multicast Packet (Counter) */ 373 uint rbca; /* Receive Broadcast Packet */ 374 uint rxcf; /* Receive Control Frame Packet */ 375 uint rxpf; /* Receive Pause Frame Packet */ 376 uint rxuo; /* Receive Unknown OP Code */ 377 uint raln; /* Receive Alignment Error */ 378 uint rflr; /* Receive Frame Length Error */ 379 uint rcde; /* Receive Code Error */ 380 uint rcse; /* Receive Carrier Sense Error */ 381 uint rund; /* Receive Undersize Packet */ 382 uint rovr; /* Receive Oversize Packet */ 383 uint rfrg; /* Receive Fragments */ 384 uint rjbr; /* Receive Jabber */ 385 uint rdrp; /* Receive Drop */ 386 /* Transmit Counters */ 387 uint tbyt; /* Transmit Byte Counter */ 388 uint tpkt; /* Transmit Packet */ 389 uint tmca; /* Transmit Multicast Packet */ 390 uint tbca; /* Transmit Broadcast Packet */ 391 uint txpf; /* Transmit Pause Control Frame */ 392 uint tdfr; /* Transmit Deferral Packet */ 393 uint tedf; /* Transmit Excessive Deferral Packet */ 394 uint tscl; /* Transmit Single Collision Packet */ 395 /* (0x2_n700) */ 396 uint tmcl; /* Transmit Multiple Collision Packet */ 397 uint tlcl; /* Transmit Late Collision Packet */ 398 uint txcl; /* Transmit Excessive Collision Packet */ 399 uint tncl; /* Transmit Total Collision */ 400 401 uint res2; 402 403 uint tdrp; /* Transmit Drop Frame */ 404 uint tjbr; /* Transmit Jabber Frame */ 405 uint tfcs; /* Transmit FCS Error */ 406 uint txcf; /* Transmit Control Frame */ 407 uint tovr; /* Transmit Oversize Frame */ 408 uint tund; /* Transmit Undersize Frame */ 409 uint tfrg; /* Transmit Fragments Frame */ 410 /* General Registers */ 411 uint car1; /* Carry Register One */ 412 uint car2; /* Carry Register Two */ 413 uint cam1; /* Carry Register One Mask */ 414 uint cam2; /* Carry Register Two Mask */ 415 } rmon_mib_t; 416 417 typedef struct tsec_hash_regs 418 { 419 uint iaddr0; /* Individual Address Register 0 */ 420 uint iaddr1; /* Individual Address Register 1 */ 421 uint iaddr2; /* Individual Address Register 2 */ 422 uint iaddr3; /* Individual Address Register 3 */ 423 uint iaddr4; /* Individual Address Register 4 */ 424 uint iaddr5; /* Individual Address Register 5 */ 425 uint iaddr6; /* Individual Address Register 6 */ 426 uint iaddr7; /* Individual Address Register 7 */ 427 uint res1[24]; 428 uint gaddr0; /* Group Address Register 0 */ 429 uint gaddr1; /* Group Address Register 1 */ 430 uint gaddr2; /* Group Address Register 2 */ 431 uint gaddr3; /* Group Address Register 3 */ 432 uint gaddr4; /* Group Address Register 4 */ 433 uint gaddr5; /* Group Address Register 5 */ 434 uint gaddr6; /* Group Address Register 6 */ 435 uint gaddr7; /* Group Address Register 7 */ 436 uint res2[24]; 437 } tsec_hash_t; 438 439 typedef struct tsec 440 { 441 /* General Control and Status Registers (0x2_n000) */ 442 uint res000[4]; 443 444 uint ievent; /* Interrupt Event */ 445 uint imask; /* Interrupt Mask */ 446 uint edis; /* Error Disabled */ 447 uint res01c; 448 uint ecntrl; /* Ethernet Control */ 449 uint minflr; /* Minimum Frame Length */ 450 uint ptv; /* Pause Time Value */ 451 uint dmactrl; /* DMA Control */ 452 uint tbipa; /* TBI PHY Address */ 453 454 uint res034[3]; 455 uint res040[48]; 456 457 /* Transmit Control and Status Registers (0x2_n100) */ 458 uint tctrl; /* Transmit Control */ 459 uint tstat; /* Transmit Status */ 460 uint res108; 461 uint tbdlen; /* Tx BD Data Length */ 462 uint res110[5]; 463 uint ctbptr; /* Current TxBD Pointer */ 464 uint res128[23]; 465 uint tbptr; /* TxBD Pointer */ 466 uint res188[30]; 467 /* (0x2_n200) */ 468 uint res200; 469 uint tbase; /* TxBD Base Address */ 470 uint res208[42]; 471 uint ostbd; /* Out of Sequence TxBD */ 472 uint ostbdp; /* Out of Sequence Tx Data Buffer Pointer */ 473 uint res2b8[18]; 474 475 /* Receive Control and Status Registers (0x2_n300) */ 476 uint rctrl; /* Receive Control */ 477 uint rstat; /* Receive Status */ 478 uint res308; 479 uint rbdlen; /* RxBD Data Length */ 480 uint res310[4]; 481 uint res320; 482 uint crbptr; /* Current Receive Buffer Pointer */ 483 uint res328[6]; 484 uint mrblr; /* Maximum Receive Buffer Length */ 485 uint res344[16]; 486 uint rbptr; /* RxBD Pointer */ 487 uint res388[30]; 488 /* (0x2_n400) */ 489 uint res400; 490 uint rbase; /* RxBD Base Address */ 491 uint res408[62]; 492 493 /* MAC Registers (0x2_n500) */ 494 uint maccfg1; /* MAC Configuration #1 */ 495 uint maccfg2; /* MAC Configuration #2 */ 496 uint ipgifg; /* Inter Packet Gap/Inter Frame Gap */ 497 uint hafdup; /* Half-duplex */ 498 uint maxfrm; /* Maximum Frame */ 499 uint res514; 500 uint res518; 501 502 uint res51c; 503 504 uint miimcfg; /* MII Management: Configuration */ 505 uint miimcom; /* MII Management: Command */ 506 uint miimadd; /* MII Management: Address */ 507 uint miimcon; /* MII Management: Control */ 508 uint miimstat; /* MII Management: Status */ 509 uint miimind; /* MII Management: Indicators */ 510 511 uint res538; 512 513 uint ifstat; /* Interface Status */ 514 uint macstnaddr1; /* Station Address, part 1 */ 515 uint macstnaddr2; /* Station Address, part 2 */ 516 uint res548[46]; 517 518 /* (0x2_n600) */ 519 uint res600[32]; 520 521 /* RMON MIB Registers (0x2_n680-0x2_n73c) */ 522 rmon_mib_t rmon; 523 uint res740[48]; 524 525 /* Hash Function Registers (0x2_n800) */ 526 tsec_hash_t hash; 527 528 uint res900[128]; 529 530 /* Pattern Registers (0x2_nb00) */ 531 uint resb00[62]; 532 uint attr; /* Default Attribute Register */ 533 uint attreli; /* Default Attribute Extract Length and Index */ 534 535 /* TSEC Future Expansion Space (0x2_nc00-0x2_nffc) */ 536 uint resc00[256]; 537 } tsec_t; 538 539 #define TSEC_GIGABIT (1) 540 541 /* This flag currently only has 542 * meaning if we're using the eTSEC */ 543 #define TSEC_REDUCED (1 << 1) 544 545 struct tsec_private { 546 volatile tsec_t *regs; 547 volatile tsec_t *phyregs; 548 struct phy_info *phyinfo; 549 uint phyaddr; 550 u32 flags; 551 uint link; 552 uint duplexity; 553 uint speed; 554 }; 555 556 557 /* 558 * struct phy_cmd: A command for reading or writing a PHY register 559 * 560 * mii_reg: The register to read or write 561 * 562 * mii_data: For writes, the value to put in the register. 563 * A value of -1 indicates this is a read. 564 * 565 * funct: A function pointer which is invoked for each command. 566 * For reads, this function will be passed the value read 567 * from the PHY, and process it. 568 * For writes, the result of this function will be written 569 * to the PHY register 570 */ 571 struct phy_cmd { 572 uint mii_reg; 573 uint mii_data; 574 uint (*funct) (uint mii_reg, struct tsec_private * priv); 575 }; 576 577 /* struct phy_info: a structure which defines attributes for a PHY 578 * 579 * id will contain a number which represents the PHY. During 580 * startup, the driver will poll the PHY to find out what its 581 * UID--as defined by registers 2 and 3--is. The 32-bit result 582 * gotten from the PHY will be shifted right by "shift" bits to 583 * discard any bits which may change based on revision numbers 584 * unimportant to functionality 585 * 586 * The struct phy_cmd entries represent pointers to an arrays of 587 * commands which tell the driver what to do to the PHY. 588 */ 589 struct phy_info { 590 uint id; 591 char *name; 592 uint shift; 593 /* Called to configure the PHY, and modify the controller 594 * based on the results */ 595 struct phy_cmd *config; 596 597 /* Called when starting up the controller */ 598 struct phy_cmd *startup; 599 600 /* Called when bringing down the controller */ 601 struct phy_cmd *shutdown; 602 }; 603 604 struct tsec_info_struct { 605 tsec_t *regs; 606 tsec_t *miiregs; 607 char *devname; 608 unsigned int phyaddr; 609 u32 flags; 610 }; 611 612 int tsec_initialize(bd_t * bis, struct tsec_info_struct *tsec_info); 613 int tsec_standard_init(bd_t *bis); 614 int tsec_eth_init(bd_t *bis, struct tsec_info_struct *tsec_info, int num); 615 616 #endif /* __TSEC_H */ 617