1*690e9ed1SSandy Huang /* SPDX-License-Identifier: GPL-2.0+ */ 2*690e9ed1SSandy Huang /* 3*690e9ed1SSandy Huang * (C) Copyright 2023 Rockchip Electronics Co., Ltd 4*690e9ed1SSandy Huang * 5*690e9ed1SSandy Huang */ 6*690e9ed1SSandy Huang 7*690e9ed1SSandy Huang #ifndef _SPL_DISPLAY_H_ 8*690e9ed1SSandy Huang #define _SPL_DISPLAY_H_ 9*690e9ed1SSandy Huang 10*690e9ed1SSandy Huang #include <common.h> 11*690e9ed1SSandy Huang #include <drm_modes.h> 12*690e9ed1SSandy Huang #include <mp_boot.h> 13*690e9ed1SSandy Huang 14*690e9ed1SSandy Huang /* SPL display */ 15*690e9ed1SSandy Huang #define RK3528_VOP_BASE 0xff840000 16*690e9ed1SSandy Huang #define RK3528_HDMI_BASE 0xff8d0000 17*690e9ed1SSandy Huang #define RK3528_HDMIPHY_BASE 0xffe00000 18*690e9ed1SSandy Huang #define RK3528_CRU_BASE 0xff4a0000 19*690e9ed1SSandy Huang #define RK3528_GPIO0_IOC_BASE 0xff540000 20*690e9ed1SSandy Huang #define RK3528_GPIO_BASE 0xff610000 21*690e9ed1SSandy Huang 22*690e9ed1SSandy Huang struct spl_display_info { 23*690e9ed1SSandy Huang struct drm_display_mode mode; 24*690e9ed1SSandy Huang u32 bus_format; 25*690e9ed1SSandy Huang u32 enabled; 26*690e9ed1SSandy Huang }; 27*690e9ed1SSandy Huang #endif 28*690e9ed1SSandy Huang 29