1*db2f721fSwdenk /* 2*db2f721fSwdenk * Copyright (C) 2003 Arabella Software Ltd. 3*db2f721fSwdenk * Yuli Barcohen <yuli@arabellasw.com> 4*db2f721fSwdenk * 5*db2f721fSwdenk * Serial Presence Detect (SPD) EEPROM format according to the 6*db2f721fSwdenk * Intel's PC SDRAM Serial Presence Detect (SPD) Specification, 7*db2f721fSwdenk * revision 1.2B, November 1999 8*db2f721fSwdenk * 9*db2f721fSwdenk * This program is free software; you can redistribute it and/or 10*db2f721fSwdenk * modify it under the terms of the GNU General Public License as 11*db2f721fSwdenk * published by the Free Software Foundation; either version 2 of the 12*db2f721fSwdenk * License, or (at your option) any later version. 13*db2f721fSwdenk * 14*db2f721fSwdenk * This program is distributed in the hope that it will be useful, but 15*db2f721fSwdenk * WITHOUT ANY WARRANTY; without even the implied warranty of 16*db2f721fSwdenk * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 17*db2f721fSwdenk * General Public License for more details. 18*db2f721fSwdenk * 19*db2f721fSwdenk * You should have received a copy of the GNU General Public License 20*db2f721fSwdenk * along with this program; if not, write to the Free Software 21*db2f721fSwdenk * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 22*db2f721fSwdenk */ 23*db2f721fSwdenk 24*db2f721fSwdenk #ifndef _SPD_H_ 25*db2f721fSwdenk #define _SPD_H_ 26*db2f721fSwdenk 27*db2f721fSwdenk typedef struct spd_eeprom_s { 28*db2f721fSwdenk unsigned char info_size; /* # of bytes written into serial memory */ 29*db2f721fSwdenk unsigned char chip_size; /* Total # of bytes of SPD memory device */ 30*db2f721fSwdenk unsigned char mem_type; /* Fundamental memory type (FPM, EDO, SDRAM...) */ 31*db2f721fSwdenk unsigned char nrow_addr; /* # of Row Addresses on this assembly */ 32*db2f721fSwdenk unsigned char ncol_addr; /* # of Column Addresses on this assembly */ 33*db2f721fSwdenk unsigned char nrows; /* # of Module Rows on this assembly */ 34*db2f721fSwdenk unsigned char dataw_lsb; /* Data Width of this assembly */ 35*db2f721fSwdenk unsigned char dataw_msb; /* ... Data Width continuation */ 36*db2f721fSwdenk unsigned char voltage; /* Voltage interface standard of this assembly */ 37*db2f721fSwdenk unsigned char clk_cycle; /* SDRAM Cycle time at CL=X */ 38*db2f721fSwdenk unsigned char clk_access; /* SDRAM Access from Clock at CL=X */ 39*db2f721fSwdenk unsigned char config; /* DIMM Configuration type (non-parity, ECC) */ 40*db2f721fSwdenk unsigned char refresh; /* Refresh Rate/Type */ 41*db2f721fSwdenk unsigned char primw; /* Primary SDRAM Width */ 42*db2f721fSwdenk unsigned char ecw; /* Error Checking SDRAM width */ 43*db2f721fSwdenk unsigned char min_delay; /* Min Clock Delay for Back to Back Random Address */ 44*db2f721fSwdenk unsigned char burstl; /* Burst Lengths Supported */ 45*db2f721fSwdenk unsigned char nbanks; /* # of Banks on Each SDRAM Device */ 46*db2f721fSwdenk unsigned char cas_lat; /* CAS# Latencies Supported */ 47*db2f721fSwdenk unsigned char cs_lat; /* CS# Latency */ 48*db2f721fSwdenk unsigned char write_lat; /* Write Latency (also called Write Recovery time) */ 49*db2f721fSwdenk unsigned char mod_attr; /* SDRAM Module Attributes */ 50*db2f721fSwdenk unsigned char dev_attr; /* SDRAM Device Attributes */ 51*db2f721fSwdenk unsigned char clk_cycle2; /* Min SDRAM Cycle time at CL=X-1 */ 52*db2f721fSwdenk unsigned char clk_access2; /* SDRAM Access from Clock at CL=X-1 */ 53*db2f721fSwdenk unsigned char clk_cycle3; /* Min SDRAM Cycle time at CL=X-2 */ 54*db2f721fSwdenk unsigned char clk_access3; /* Max SDRAM Access from Clock at CL=X-2 */ 55*db2f721fSwdenk unsigned char trp; /* Min Row Precharge Time (tRP) */ 56*db2f721fSwdenk unsigned char trrd; /* Min Row Active to Row Active (tRRD) */ 57*db2f721fSwdenk unsigned char trcd; /* Min RAS to CAS Delay (tRCD) */ 58*db2f721fSwdenk unsigned char tras; /* Minimum RAS Pulse Width (tRAS) */ 59*db2f721fSwdenk unsigned char row_dens; /* Density of each row on module */ 60*db2f721fSwdenk unsigned char ca_setup; /* Command and Address signal input setup time */ 61*db2f721fSwdenk unsigned char ca_hold; /* Command and Address signal input hold time */ 62*db2f721fSwdenk unsigned char data_setup; /* Data signal input setup time */ 63*db2f721fSwdenk unsigned char data_hold; /* Data signal input hold time */ 64*db2f721fSwdenk unsigned char sset[26]; /* Superset Information (may be used in future) */ 65*db2f721fSwdenk unsigned char spd_rev; /* SPD Data Revision Code */ 66*db2f721fSwdenk unsigned char cksum; /* Checksum for bytes 0-62 */ 67*db2f721fSwdenk unsigned char mid[8]; /* Manufacturer's JEDEC ID code per JEP-108E */ 68*db2f721fSwdenk unsigned char mloc; /* Manufacturing Location */ 69*db2f721fSwdenk unsigned char mpart[18]; /* Manufacturer's Part Number */ 70*db2f721fSwdenk unsigned char rev[2]; /* Revision Code */ 71*db2f721fSwdenk unsigned char mdate[2]; /* Manufacturing Date */ 72*db2f721fSwdenk unsigned char sernum[4]; /* Assembly Serial Number */ 73*db2f721fSwdenk unsigned char mspec[27]; /* Manufacturer Specific Data */ 74*db2f721fSwdenk unsigned char freq; /* Intel specification frequency */ 75*db2f721fSwdenk unsigned char intel_cas; /* Intel Specification CAS# Latency support */ 76*db2f721fSwdenk } spd_eeprom_t; 77*db2f721fSwdenk 78*db2f721fSwdenk #endif /* _SPD_H_ */ 79