1*067f54c6SMatthias Fuchs /* 2*067f54c6SMatthias Fuchs * Copyright 2009, Matthias Fuchs <matthias.fuchs@esd.eu> 3*067f54c6SMatthias Fuchs * 4*067f54c6SMatthias Fuchs * SJA1000 register layout for basic CAN mode 5*067f54c6SMatthias Fuchs * 6*067f54c6SMatthias Fuchs * See file CREDITS for list of people who contributed to this 7*067f54c6SMatthias Fuchs * project. 8*067f54c6SMatthias Fuchs * 9*067f54c6SMatthias Fuchs * This program is free software; you can redistribute it and/or 10*067f54c6SMatthias Fuchs * modify it under the terms of the GNU General Public License as 11*067f54c6SMatthias Fuchs * published by the Free Software Foundation; either version 2 of 12*067f54c6SMatthias Fuchs * the License, or (at your option) any later version. 13*067f54c6SMatthias Fuchs * 14*067f54c6SMatthias Fuchs * This program is distributed in the hope that it will be useful, 15*067f54c6SMatthias Fuchs * but WITHOUT ANY WARRANTY; without even the implied warranty of 16*067f54c6SMatthias Fuchs * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17*067f54c6SMatthias Fuchs * GNU General Public License for more details. 18*067f54c6SMatthias Fuchs * 19*067f54c6SMatthias Fuchs * You should have received a copy of the GNU General Public License 20*067f54c6SMatthias Fuchs * along with this program; if not, write to the Free Software 21*067f54c6SMatthias Fuchs * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22*067f54c6SMatthias Fuchs * MA 02111-1307 USA 23*067f54c6SMatthias Fuchs */ 24*067f54c6SMatthias Fuchs 25*067f54c6SMatthias Fuchs #ifndef _SJA1000_H_ 26*067f54c6SMatthias Fuchs #define _SJA1000_H_ 27*067f54c6SMatthias Fuchs 28*067f54c6SMatthias Fuchs /* 29*067f54c6SMatthias Fuchs * SJA1000 register layout in basic can mode 30*067f54c6SMatthias Fuchs */ 31*067f54c6SMatthias Fuchs struct sja1000_basic_s { 32*067f54c6SMatthias Fuchs u8 cr; 33*067f54c6SMatthias Fuchs u8 cmr; 34*067f54c6SMatthias Fuchs u8 sr; 35*067f54c6SMatthias Fuchs u8 ir; 36*067f54c6SMatthias Fuchs u8 ac; 37*067f54c6SMatthias Fuchs u8 am; 38*067f54c6SMatthias Fuchs u8 btr0; 39*067f54c6SMatthias Fuchs u8 btr1; 40*067f54c6SMatthias Fuchs u8 oc; 41*067f54c6SMatthias Fuchs u8 txb[10]; 42*067f54c6SMatthias Fuchs u8 rxb[10]; 43*067f54c6SMatthias Fuchs u8 unused; 44*067f54c6SMatthias Fuchs u8 cdr; 45*067f54c6SMatthias Fuchs }; 46*067f54c6SMatthias Fuchs 47*067f54c6SMatthias Fuchs /* control register */ 48*067f54c6SMatthias Fuchs #define CR_RR 0x01 49*067f54c6SMatthias Fuchs 50*067f54c6SMatthias Fuchs /* output control register */ 51*067f54c6SMatthias Fuchs #define OC_MODE0 0x01 52*067f54c6SMatthias Fuchs #define OC_MODE1 0x02 53*067f54c6SMatthias Fuchs #define OC_POL0 0x04 54*067f54c6SMatthias Fuchs #define OC_TN0 0x08 55*067f54c6SMatthias Fuchs #define OC_TP0 0x10 56*067f54c6SMatthias Fuchs #define OC_POL1 0x20 57*067f54c6SMatthias Fuchs #define OC_TN1 0x40 58*067f54c6SMatthias Fuchs #define OC_TP1 0x80 59*067f54c6SMatthias Fuchs 60*067f54c6SMatthias Fuchs #endif 61