1067f54c6SMatthias Fuchs /* 2067f54c6SMatthias Fuchs * Copyright 2009, Matthias Fuchs <matthias.fuchs@esd.eu> 3067f54c6SMatthias Fuchs * 4067f54c6SMatthias Fuchs * SJA1000 register layout for basic CAN mode 5067f54c6SMatthias Fuchs * 6*1a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 7067f54c6SMatthias Fuchs */ 8067f54c6SMatthias Fuchs 9067f54c6SMatthias Fuchs #ifndef _SJA1000_H_ 10067f54c6SMatthias Fuchs #define _SJA1000_H_ 11067f54c6SMatthias Fuchs 12067f54c6SMatthias Fuchs /* 13067f54c6SMatthias Fuchs * SJA1000 register layout in basic can mode 14067f54c6SMatthias Fuchs */ 15067f54c6SMatthias Fuchs struct sja1000_basic_s { 16067f54c6SMatthias Fuchs u8 cr; 17067f54c6SMatthias Fuchs u8 cmr; 18067f54c6SMatthias Fuchs u8 sr; 19067f54c6SMatthias Fuchs u8 ir; 20067f54c6SMatthias Fuchs u8 ac; 21067f54c6SMatthias Fuchs u8 am; 22067f54c6SMatthias Fuchs u8 btr0; 23067f54c6SMatthias Fuchs u8 btr1; 24067f54c6SMatthias Fuchs u8 oc; 25067f54c6SMatthias Fuchs u8 txb[10]; 26067f54c6SMatthias Fuchs u8 rxb[10]; 27067f54c6SMatthias Fuchs u8 unused; 28067f54c6SMatthias Fuchs u8 cdr; 29067f54c6SMatthias Fuchs }; 30067f54c6SMatthias Fuchs 31067f54c6SMatthias Fuchs /* control register */ 32067f54c6SMatthias Fuchs #define CR_RR 0x01 33067f54c6SMatthias Fuchs 34067f54c6SMatthias Fuchs /* output control register */ 35067f54c6SMatthias Fuchs #define OC_MODE0 0x01 36067f54c6SMatthias Fuchs #define OC_MODE1 0x02 37067f54c6SMatthias Fuchs #define OC_POL0 0x04 38067f54c6SMatthias Fuchs #define OC_TN0 0x08 39067f54c6SMatthias Fuchs #define OC_TP0 0x10 40067f54c6SMatthias Fuchs #define OC_POL1 0x20 41067f54c6SMatthias Fuchs #define OC_TN1 0x40 42067f54c6SMatthias Fuchs #define OC_TP1 0x80 43067f54c6SMatthias Fuchs 44067f54c6SMatthias Fuchs #endif 45