xref: /rk3399_rockchip-uboot/include/sh_pfc.h (revision d764c5043d6d72e012f3e50092344ebd57a0c242)
1*d764c504SNobuhiro Iwamatsu /*
2*d764c504SNobuhiro Iwamatsu  * SuperH Pin Function Controller Support
3*d764c504SNobuhiro Iwamatsu  * Copy from Linux kernel. (include/linux/sh_pfc.h)
4*d764c504SNobuhiro Iwamatsu  *
5*d764c504SNobuhiro Iwamatsu  * Copyright (c) 2008 Magnus Damm
6*d764c504SNobuhiro Iwamatsu  *
7*d764c504SNobuhiro Iwamatsu  * This file is subject to the terms and conditions of the GNU General Public
8*d764c504SNobuhiro Iwamatsu  * License.  See the file "COPYING" in the main directory of this archive
9*d764c504SNobuhiro Iwamatsu  * for more details.
10*d764c504SNobuhiro Iwamatsu  */
11*d764c504SNobuhiro Iwamatsu 
12*d764c504SNobuhiro Iwamatsu #ifndef __SH_PFC_H
13*d764c504SNobuhiro Iwamatsu #define __SH_PFC_H
14*d764c504SNobuhiro Iwamatsu 
15*d764c504SNobuhiro Iwamatsu typedef unsigned short pinmux_enum_t;
16*d764c504SNobuhiro Iwamatsu typedef unsigned short pinmux_flag_t;
17*d764c504SNobuhiro Iwamatsu 
18*d764c504SNobuhiro Iwamatsu #define PINMUX_TYPE_NONE            0
19*d764c504SNobuhiro Iwamatsu #define PINMUX_TYPE_FUNCTION        1
20*d764c504SNobuhiro Iwamatsu #define PINMUX_TYPE_GPIO            2
21*d764c504SNobuhiro Iwamatsu #define PINMUX_TYPE_OUTPUT          3
22*d764c504SNobuhiro Iwamatsu #define PINMUX_TYPE_INPUT           4
23*d764c504SNobuhiro Iwamatsu #define PINMUX_TYPE_INPUT_PULLUP    5
24*d764c504SNobuhiro Iwamatsu #define PINMUX_TYPE_INPUT_PULLDOWN  6
25*d764c504SNobuhiro Iwamatsu 
26*d764c504SNobuhiro Iwamatsu #define PINMUX_FLAG_TYPE            (0x7)
27*d764c504SNobuhiro Iwamatsu #define PINMUX_FLAG_WANT_PULLUP     (1 << 3)
28*d764c504SNobuhiro Iwamatsu #define PINMUX_FLAG_WANT_PULLDOWN   (1 << 4)
29*d764c504SNobuhiro Iwamatsu 
30*d764c504SNobuhiro Iwamatsu #define PINMUX_FLAG_DBIT_SHIFT      5
31*d764c504SNobuhiro Iwamatsu #define PINMUX_FLAG_DBIT            (0x1f << PINMUX_FLAG_DBIT_SHIFT)
32*d764c504SNobuhiro Iwamatsu #define PINMUX_FLAG_DREG_SHIFT      10
33*d764c504SNobuhiro Iwamatsu #define PINMUX_FLAG_DREG            (0x3f << PINMUX_FLAG_DREG_SHIFT)
34*d764c504SNobuhiro Iwamatsu 
35*d764c504SNobuhiro Iwamatsu struct pinmux_gpio {
36*d764c504SNobuhiro Iwamatsu 	pinmux_enum_t enum_id;
37*d764c504SNobuhiro Iwamatsu 	pinmux_flag_t flags;
38*d764c504SNobuhiro Iwamatsu };
39*d764c504SNobuhiro Iwamatsu 
40*d764c504SNobuhiro Iwamatsu #define PINMUX_GPIO(gpio, data_or_mark)[gpio] = { data_or_mark }
41*d764c504SNobuhiro Iwamatsu #define PINMUX_DATA(data_or_mark, ids...) data_or_mark, ids, 0
42*d764c504SNobuhiro Iwamatsu 
43*d764c504SNobuhiro Iwamatsu struct pinmux_cfg_reg {
44*d764c504SNobuhiro Iwamatsu 	unsigned long reg, reg_width, field_width;
45*d764c504SNobuhiro Iwamatsu 	unsigned long *cnt;
46*d764c504SNobuhiro Iwamatsu 	pinmux_enum_t *enum_ids;
47*d764c504SNobuhiro Iwamatsu 	unsigned long *var_field_width;
48*d764c504SNobuhiro Iwamatsu };
49*d764c504SNobuhiro Iwamatsu 
50*d764c504SNobuhiro Iwamatsu #define PINMUX_CFG_REG(name, r, r_width, f_width) \
51*d764c504SNobuhiro Iwamatsu 	.reg = r, .reg_width = r_width, .field_width = f_width,		\
52*d764c504SNobuhiro Iwamatsu 	.cnt = (unsigned long [r_width / f_width]) {}, \
53*d764c504SNobuhiro Iwamatsu 	.enum_ids = (pinmux_enum_t [(r_width / f_width) * (1 << f_width)])
54*d764c504SNobuhiro Iwamatsu 
55*d764c504SNobuhiro Iwamatsu #define PINMUX_CFG_REG_VAR(name, r, r_width, var_fw0, var_fwn...) \
56*d764c504SNobuhiro Iwamatsu 	.reg = r, .reg_width = r_width,	\
57*d764c504SNobuhiro Iwamatsu 	.cnt = (unsigned long [r_width]) {}, \
58*d764c504SNobuhiro Iwamatsu 	.var_field_width = (unsigned long [r_width]) { var_fw0, var_fwn, 0 }, \
59*d764c504SNobuhiro Iwamatsu 	.enum_ids = (pinmux_enum_t [])
60*d764c504SNobuhiro Iwamatsu 
61*d764c504SNobuhiro Iwamatsu struct pinmux_data_reg {
62*d764c504SNobuhiro Iwamatsu 	unsigned long reg, reg_width, reg_shadow;
63*d764c504SNobuhiro Iwamatsu 	pinmux_enum_t *enum_ids;
64*d764c504SNobuhiro Iwamatsu 	void *mapped_reg;
65*d764c504SNobuhiro Iwamatsu };
66*d764c504SNobuhiro Iwamatsu 
67*d764c504SNobuhiro Iwamatsu #define PINMUX_DATA_REG(name, r, r_width) \
68*d764c504SNobuhiro Iwamatsu 	.reg = r, .reg_width = r_width,	\
69*d764c504SNobuhiro Iwamatsu 	.enum_ids = (pinmux_enum_t [r_width]) \
70*d764c504SNobuhiro Iwamatsu 
71*d764c504SNobuhiro Iwamatsu struct pinmux_irq {
72*d764c504SNobuhiro Iwamatsu 	int irq;
73*d764c504SNobuhiro Iwamatsu 	pinmux_enum_t *enum_ids;
74*d764c504SNobuhiro Iwamatsu };
75*d764c504SNobuhiro Iwamatsu 
76*d764c504SNobuhiro Iwamatsu #define PINMUX_IRQ(irq_nr, ids...)			   \
77*d764c504SNobuhiro Iwamatsu 	{ .irq = irq_nr, .enum_ids = (pinmux_enum_t []) { ids, 0 } }	\
78*d764c504SNobuhiro Iwamatsu 
79*d764c504SNobuhiro Iwamatsu struct pinmux_range {
80*d764c504SNobuhiro Iwamatsu 	pinmux_enum_t begin;
81*d764c504SNobuhiro Iwamatsu 	pinmux_enum_t end;
82*d764c504SNobuhiro Iwamatsu 	pinmux_enum_t force;
83*d764c504SNobuhiro Iwamatsu };
84*d764c504SNobuhiro Iwamatsu 
85*d764c504SNobuhiro Iwamatsu struct pinmux_info {
86*d764c504SNobuhiro Iwamatsu 	char *name;
87*d764c504SNobuhiro Iwamatsu 	pinmux_enum_t reserved_id;
88*d764c504SNobuhiro Iwamatsu 	struct pinmux_range data;
89*d764c504SNobuhiro Iwamatsu 	struct pinmux_range input;
90*d764c504SNobuhiro Iwamatsu 	struct pinmux_range input_pd;
91*d764c504SNobuhiro Iwamatsu 	struct pinmux_range input_pu;
92*d764c504SNobuhiro Iwamatsu 	struct pinmux_range output;
93*d764c504SNobuhiro Iwamatsu 	struct pinmux_range mark;
94*d764c504SNobuhiro Iwamatsu 	struct pinmux_range function;
95*d764c504SNobuhiro Iwamatsu 
96*d764c504SNobuhiro Iwamatsu 	unsigned first_gpio, last_gpio;
97*d764c504SNobuhiro Iwamatsu 
98*d764c504SNobuhiro Iwamatsu 	struct pinmux_gpio *gpios;
99*d764c504SNobuhiro Iwamatsu 	struct pinmux_cfg_reg *cfg_regs;
100*d764c504SNobuhiro Iwamatsu 	struct pinmux_data_reg *data_regs;
101*d764c504SNobuhiro Iwamatsu 
102*d764c504SNobuhiro Iwamatsu 	pinmux_enum_t *gpio_data;
103*d764c504SNobuhiro Iwamatsu 	unsigned int gpio_data_size;
104*d764c504SNobuhiro Iwamatsu 
105*d764c504SNobuhiro Iwamatsu 	struct pinmux_irq *gpio_irq;
106*d764c504SNobuhiro Iwamatsu 	unsigned int gpio_irq_size;
107*d764c504SNobuhiro Iwamatsu 
108*d764c504SNobuhiro Iwamatsu 	struct resource *resource;
109*d764c504SNobuhiro Iwamatsu 	unsigned int num_resources;
110*d764c504SNobuhiro Iwamatsu 	unsigned long unlock_reg;
111*d764c504SNobuhiro Iwamatsu };
112*d764c504SNobuhiro Iwamatsu 
113*d764c504SNobuhiro Iwamatsu int register_pinmux(struct pinmux_info *pip);
114*d764c504SNobuhiro Iwamatsu int unregister_pinmux(struct pinmux_info *pip);
115*d764c504SNobuhiro Iwamatsu 
116*d764c504SNobuhiro Iwamatsu /* helper macro for port */
117*d764c504SNobuhiro Iwamatsu #define PORT_1(fn, pfx, sfx) fn(pfx, sfx)
118*d764c504SNobuhiro Iwamatsu 
119*d764c504SNobuhiro Iwamatsu #define PORT_10(fn, pfx, sfx) \
120*d764c504SNobuhiro Iwamatsu 	PORT_1(fn, pfx##0, sfx), PORT_1(fn, pfx##1, sfx),	\
121*d764c504SNobuhiro Iwamatsu 	PORT_1(fn, pfx##2, sfx), PORT_1(fn, pfx##3, sfx),	\
122*d764c504SNobuhiro Iwamatsu 	PORT_1(fn, pfx##4, sfx), PORT_1(fn, pfx##5, sfx),	\
123*d764c504SNobuhiro Iwamatsu 	PORT_1(fn, pfx##6, sfx), PORT_1(fn, pfx##7, sfx),	\
124*d764c504SNobuhiro Iwamatsu 	PORT_1(fn, pfx##8, sfx), PORT_1(fn, pfx##9, sfx)
125*d764c504SNobuhiro Iwamatsu 
126*d764c504SNobuhiro Iwamatsu #define PORT_90(fn, pfx, sfx) \
127*d764c504SNobuhiro Iwamatsu 	PORT_10(fn, pfx##1, sfx), PORT_10(fn, pfx##2, sfx),	\
128*d764c504SNobuhiro Iwamatsu 	PORT_10(fn, pfx##3, sfx), PORT_10(fn, pfx##4, sfx),	\
129*d764c504SNobuhiro Iwamatsu 	PORT_10(fn, pfx##5, sfx), PORT_10(fn, pfx##6, sfx),	\
130*d764c504SNobuhiro Iwamatsu 	PORT_10(fn, pfx##7, sfx), PORT_10(fn, pfx##8, sfx),	\
131*d764c504SNobuhiro Iwamatsu 	PORT_10(fn, pfx##9, sfx)
132*d764c504SNobuhiro Iwamatsu 
133*d764c504SNobuhiro Iwamatsu #define _PORT_ALL(pfx, sfx) pfx##_##sfx
134*d764c504SNobuhiro Iwamatsu #define _GPIO_PORT(pfx, sfx) PINMUX_GPIO(GPIO_PORT##pfx, PORT##pfx##_DATA)
135*d764c504SNobuhiro Iwamatsu #define PORT_ALL(str)	CPU_ALL_PORT(_PORT_ALL, PORT, str)
136*d764c504SNobuhiro Iwamatsu #define GPIO_PORT_ALL()	CPU_ALL_PORT(_GPIO_PORT, , unused)
137*d764c504SNobuhiro Iwamatsu #define GPIO_FN(str) PINMUX_GPIO(GPIO_FN_##str, str##_MARK)
138*d764c504SNobuhiro Iwamatsu 
139*d764c504SNobuhiro Iwamatsu /* helper macro for pinmux_enum_t */
140*d764c504SNobuhiro Iwamatsu #define PORT_DATA_I(nr)	\
141*d764c504SNobuhiro Iwamatsu 	PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_IN)
142*d764c504SNobuhiro Iwamatsu 
143*d764c504SNobuhiro Iwamatsu #define PORT_DATA_I_PD(nr)	\
144*d764c504SNobuhiro Iwamatsu 	PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0,	\
145*d764c504SNobuhiro Iwamatsu 		    PORT##nr##_IN, PORT##nr##_IN_PD)
146*d764c504SNobuhiro Iwamatsu 
147*d764c504SNobuhiro Iwamatsu #define PORT_DATA_I_PU(nr)	\
148*d764c504SNobuhiro Iwamatsu 	PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0,	\
149*d764c504SNobuhiro Iwamatsu 		    PORT##nr##_IN, PORT##nr##_IN_PU)
150*d764c504SNobuhiro Iwamatsu 
151*d764c504SNobuhiro Iwamatsu #define PORT_DATA_I_PU_PD(nr)	\
152*d764c504SNobuhiro Iwamatsu 	PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0,			\
153*d764c504SNobuhiro Iwamatsu 		    PORT##nr##_IN, PORT##nr##_IN_PD, PORT##nr##_IN_PU)
154*d764c504SNobuhiro Iwamatsu 
155*d764c504SNobuhiro Iwamatsu #define PORT_DATA_O(nr)		\
156*d764c504SNobuhiro Iwamatsu 	PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT)
157*d764c504SNobuhiro Iwamatsu 
158*d764c504SNobuhiro Iwamatsu #define PORT_DATA_IO(nr)	\
159*d764c504SNobuhiro Iwamatsu 	PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT,	\
160*d764c504SNobuhiro Iwamatsu 		    PORT##nr##_IN)
161*d764c504SNobuhiro Iwamatsu 
162*d764c504SNobuhiro Iwamatsu #define PORT_DATA_IO_PD(nr)	\
163*d764c504SNobuhiro Iwamatsu 	PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT,	\
164*d764c504SNobuhiro Iwamatsu 		    PORT##nr##_IN, PORT##nr##_IN_PD)
165*d764c504SNobuhiro Iwamatsu 
166*d764c504SNobuhiro Iwamatsu #define PORT_DATA_IO_PU(nr)	\
167*d764c504SNobuhiro Iwamatsu 	PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT,	\
168*d764c504SNobuhiro Iwamatsu 		    PORT##nr##_IN, PORT##nr##_IN_PU)
169*d764c504SNobuhiro Iwamatsu 
170*d764c504SNobuhiro Iwamatsu #define PORT_DATA_IO_PU_PD(nr)	\
171*d764c504SNobuhiro Iwamatsu 	PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT,	\
172*d764c504SNobuhiro Iwamatsu 		    PORT##nr##_IN, PORT##nr##_IN_PD, PORT##nr##_IN_PU)
173*d764c504SNobuhiro Iwamatsu 
174*d764c504SNobuhiro Iwamatsu /* helper macro for top 4 bits in PORTnCR */
175*d764c504SNobuhiro Iwamatsu #define _PCRH(in, in_pd, in_pu, out)	\
176*d764c504SNobuhiro Iwamatsu 	0, (out), (in), 0,		\
177*d764c504SNobuhiro Iwamatsu 	0, 0, 0, 0,			\
178*d764c504SNobuhiro Iwamatsu 	0, 0, (in_pd), 0,		\
179*d764c504SNobuhiro Iwamatsu 	0, 0, (in_pu), 0
180*d764c504SNobuhiro Iwamatsu 
181*d764c504SNobuhiro Iwamatsu #define PORTCR(nr, reg)							\
182*d764c504SNobuhiro Iwamatsu 	{								\
183*d764c504SNobuhiro Iwamatsu 		PINMUX_CFG_REG("PORT" nr "CR", reg, 8, 4) {		\
184*d764c504SNobuhiro Iwamatsu 			_PCRH(PORT##nr##_IN, PORT##nr##_IN_PD,		\
185*d764c504SNobuhiro Iwamatsu 			      PORT##nr##_IN_PU, PORT##nr##_OUT),	\
186*d764c504SNobuhiro Iwamatsu 				PORT##nr##_FN0, PORT##nr##_FN1,		\
187*d764c504SNobuhiro Iwamatsu 				PORT##nr##_FN2, PORT##nr##_FN3,		\
188*d764c504SNobuhiro Iwamatsu 				PORT##nr##_FN4, PORT##nr##_FN5,		\
189*d764c504SNobuhiro Iwamatsu 				PORT##nr##_FN6, PORT##nr##_FN7 }	\
190*d764c504SNobuhiro Iwamatsu 	}
191*d764c504SNobuhiro Iwamatsu 
192*d764c504SNobuhiro Iwamatsu #endif /* __SH_PFC_H */
193