1*1afcdfc6SEtienne Carriere /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2*1afcdfc6SEtienne Carriere /* 3*1afcdfc6SEtienne Carriere * Copyright (c) 2015-2019, Arm Limited and Contributors. All rights reserved. 4*1afcdfc6SEtienne Carriere * Copyright (C) 2019-2020, Linaro Limited 5*1afcdfc6SEtienne Carriere */ 6*1afcdfc6SEtienne Carriere #ifndef _SCMI_PROTOCOLS_H 7*1afcdfc6SEtienne Carriere #define _SCMI_PROTOCOLS_H 8*1afcdfc6SEtienne Carriere 9*1afcdfc6SEtienne Carriere #include <linux/bitops.h> 10*1afcdfc6SEtienne Carriere 11*1afcdfc6SEtienne Carriere /* 12*1afcdfc6SEtienne Carriere * Subset the SCMI protocols definition 13*1afcdfc6SEtienne Carriere * based on SCMI specification v2.0 (DEN0056B) 14*1afcdfc6SEtienne Carriere * https://developer.arm.com/docs/den0056/b 15*1afcdfc6SEtienne Carriere */ 16*1afcdfc6SEtienne Carriere 17*1afcdfc6SEtienne Carriere enum scmi_std_protocol { 18*1afcdfc6SEtienne Carriere SCMI_PROTOCOL_ID_BASE = 0x10, 19*1afcdfc6SEtienne Carriere SCMI_PROTOCOL_ID_POWER_DOMAIN = 0x11, 20*1afcdfc6SEtienne Carriere SCMI_PROTOCOL_ID_SYSTEM = 0x12, 21*1afcdfc6SEtienne Carriere SCMI_PROTOCOL_ID_PERF = 0x13, 22*1afcdfc6SEtienne Carriere SCMI_PROTOCOL_ID_CLOCK = 0x14, 23*1afcdfc6SEtienne Carriere SCMI_PROTOCOL_ID_SENSOR = 0x15, 24*1afcdfc6SEtienne Carriere SCMI_PROTOCOL_ID_RESET_DOMAIN = 0x16, 25*1afcdfc6SEtienne Carriere }; 26*1afcdfc6SEtienne Carriere 27*1afcdfc6SEtienne Carriere enum scmi_status_code { 28*1afcdfc6SEtienne Carriere SCMI_SUCCESS = 0, 29*1afcdfc6SEtienne Carriere SCMI_NOT_SUPPORTED = -1, 30*1afcdfc6SEtienne Carriere SCMI_INVALID_PARAMETERS = -2, 31*1afcdfc6SEtienne Carriere SCMI_DENIED = -3, 32*1afcdfc6SEtienne Carriere SCMI_NOT_FOUND = -4, 33*1afcdfc6SEtienne Carriere SCMI_OUT_OF_RANGE = -5, 34*1afcdfc6SEtienne Carriere SCMI_BUSY = -6, 35*1afcdfc6SEtienne Carriere SCMI_COMMS_ERROR = -7, 36*1afcdfc6SEtienne Carriere SCMI_GENERIC_ERROR = -8, 37*1afcdfc6SEtienne Carriere SCMI_HARDWARE_ERROR = -9, 38*1afcdfc6SEtienne Carriere SCMI_PROTOCOL_ERROR = -10, 39*1afcdfc6SEtienne Carriere }; 40*1afcdfc6SEtienne Carriere 41*1afcdfc6SEtienne Carriere #endif /* _SCMI_PROTOCOLS_H */ 42