1 /* SPDX-License-Identifier: GPL-2.0 */ 2 3 /* Copyright (c) 2025 Rockchip Electronics Co., Ltd. */ 4 5 #ifndef __RKCE_REG_H 6 #define __RKCE_REG_H 7 8 #include <linux/types.h> 9 10 /****************************************************************************************/ 11 /* */ 12 /* Module Structure Section */ 13 /* */ 14 /****************************************************************************************/ 15 /* RKCE Register Structure Define */ 16 struct RKCE_REG { 17 uint32_t CLK_CTL; /* Address Offset: 0x0000 */ 18 uint32_t RST_CTL; /* Address Offset: 0x0004 */ 19 uint32_t RESERVED0008[126]; /* Address Offset: 0x0008 */ 20 uint32_t TD_ADDR; /* Address Offset: 0x0200 */ 21 uint32_t TD_LOAD_CTRL; /* Address Offset: 0x0204 */ 22 uint32_t FIFO_ST; /* Address Offset: 0x0208 */ 23 uint32_t RESERVED020C; /* Address Offset: 0x020C */ 24 uint32_t SYMM_INT_EN; /* Address Offset: 0x0210 */ 25 uint32_t SYMM_INT_ST; /* Address Offset: 0x0214 */ 26 uint32_t SYMM_TD_ID; /* Address Offset: 0x0218 */ 27 uint32_t SYMM_TD_ST; /* Address Offset: 0x021C */ 28 uint32_t SYMM_ST_DBG; /* Address Offset: 0x0220 */ 29 uint32_t SYMM_CONTEXT_SIZE; /* Address Offset: 0x0224 */ 30 uint32_t SYMM_TD_ADDR_DBG; /* Address Offset: 0x0228 */ 31 uint32_t SYMM_TD_GRANT_DBG; /* Address Offset: 0x022C */ 32 uint32_t HASH_INT_EN; /* Address Offset: 0x0230 */ 33 uint32_t HASH_INT_ST; /* Address Offset: 0x0234 */ 34 uint32_t HASH_TD_ID; /* Address Offset: 0x0238 */ 35 uint32_t HASH_TD_ST; /* Address Offset: 0x023C */ 36 uint32_t HASH_ST_DBG; /* Address Offset: 0x0240 */ 37 uint32_t HASH_CONTEXT_SIZE; /* Address Offset: 0x0244 */ 38 uint32_t HASH_TD_ADDR_DBG; /* Address Offset: 0x0248 */ 39 uint32_t HASH_TD_GRANT_DBG; /* Address Offset: 0x024C */ 40 uint32_t SYMM_TD_POP_ADDR; /* Address Offset: 0x0250 */ 41 uint32_t HASH_TD_POP_ADDR; /* Address Offset: 0x0254 */ 42 uint32_t TD_POP_CTRL; /* Address Offset: 0x0258 */ 43 uint32_t RESERVED025C[5]; /* Address Offset: 0x025C */ 44 uint32_t KL_TO_CE_PADDR; /* Address Offset: 0x0270 */ 45 uint32_t KL_KD_ADDR; /* Address Offset: 0x0274 */ 46 uint32_t RESERVED0278[94]; /* Address Offset: 0x0278 */ 47 uint32_t ECC_CTL; /* Address Offset: 0x03F0 */ 48 uint32_t ECC_INT_EN; /* Address Offset: 0x03F4 */ 49 uint32_t ECC_INT_ST; /* Address Offset: 0x03F8 */ 50 uint32_t ECC_ABN_ST; /* Address Offset: 0x03FC */ 51 uint32_t ECC_CURVE_WIDE; /* Address Offset: 0x0400 */ 52 uint32_t ECC_MAX_CURVE_WIDE; /* Address Offset: 0x0404 */ 53 uint32_t ECC_DATA_ENDIAN; /* Address Offset: 0x0408 */ 54 uint32_t RESERVED040C[17]; /* Address Offset: 0x040C */ 55 uint32_t KL_APB_CMD; /* Address Offset: 0x0450 */ 56 uint32_t KL_APB_PADDR; /* Address Offset: 0x0454 */ 57 uint32_t KL_APB_PWDATA; /* Address Offset: 0x0458 */ 58 uint32_t RESERVED045C[2]; /* Address Offset: 0x045C */ 59 uint32_t KL_KD_VID; /* Address Offset: 0x0464 */ 60 uint32_t KL_KD_MODE; /* Address Offset: 0x0468 */ 61 uint32_t RESERVED046C[5]; /* Address Offset: 0x046C */ 62 uint32_t PKA_RAM_CTL; /* Address Offset: 0x0480 */ 63 uint32_t PKA_RAM_ST; /* Address Offset: 0x0484 */ 64 uint32_t RESERVED0488[6]; /* Address Offset: 0x0488 */ 65 uint32_t PKA_DEBUG_CTL; /* Address Offset: 0x04A0 */ 66 uint32_t PKA_DEBUG_ST; /* Address Offset: 0x04A4 */ 67 uint32_t PKA_DEBUG_MONITOR; /* Address Offset: 0x04A8 */ 68 uint32_t RESERVED04AC[85]; /* Address Offset: 0x04AC */ 69 uint32_t KT_ST; /* Address Offset: 0x0600 */ 70 uint32_t RESERVED0604; /* Address Offset: 0x0604 */ 71 uint32_t KL_INTER_COPY; /* Address Offset: 0x0608 */ 72 uint32_t RESERVED060C[4]; /* Address Offset: 0x060C */ 73 uint32_t LOCKSTEP_EN; /* Address Offset: 0x061C */ 74 uint32_t RESERVED0620[2]; /* Address Offset: 0x0620 */ 75 uint32_t LOCKSTEP_IJERR; /* Address Offset: 0x0628 */ 76 uint32_t RESERVED062C[5]; /* Address Offset: 0x062C */ 77 uint32_t KL_OTP_KEY_REQ; /* Address Offset: 0x0640 */ 78 uint32_t KL_KEY_CLEAR; /* Address Offset: 0x0644 */ 79 uint32_t KL_OTP_KEY_LEN; /* Address Offset: 0x0648 */ 80 uint32_t KL_HW_DRNG_REQ; /* Address Offset: 0x064C */ 81 uint32_t RESERVED0650[12]; /* Address Offset: 0x0650 */ 82 uint32_t AES_VER; /* Address Offset: 0x0680 */ 83 uint32_t DES_VER; /* Address Offset: 0x0684 */ 84 uint32_t SM4_VER; /* Address Offset: 0x0688 */ 85 uint32_t HASH_VER; /* Address Offset: 0x068C */ 86 uint32_t HMAC_VER; /* Address Offset: 0x0690 */ 87 uint32_t RESERVED0694; /* Address Offset: 0x0694 */ 88 uint32_t PKA_VER; /* Address Offset: 0x0698 */ 89 uint32_t EXTRA_FEATURE; /* Address Offset: 0x069C */ 90 uint32_t RESERVED06A0[20]; /* Address Offset: 0x06A0 */ 91 uint32_t CE_VER; /* Address Offset: 0x06F0 */ 92 uint32_t RESERVED06F4[67]; /* Address Offset: 0x06F4 */ 93 uint32_t PKA_MEM_MAP0; /* Address Offset: 0x0800 */ 94 uint32_t PKA_MEM_MAP1; /* Address Offset: 0x0804 */ 95 uint32_t PKA_MEM_MAP2; /* Address Offset: 0x0808 */ 96 uint32_t PKA_MEM_MAP3; /* Address Offset: 0x080C */ 97 uint32_t PKA_MEM_MAP4; /* Address Offset: 0x0810 */ 98 uint32_t PKA_MEM_MAP5; /* Address Offset: 0x0814 */ 99 uint32_t PKA_MEM_MAP6; /* Address Offset: 0x0818 */ 100 uint32_t PKA_MEM_MAP7; /* Address Offset: 0x081C */ 101 uint32_t PKA_MEM_MAP8; /* Address Offset: 0x0820 */ 102 uint32_t PKA_MEM_MAP9; /* Address Offset: 0x0824 */ 103 uint32_t PKA_MEM_MAP10; /* Address Offset: 0x0828 */ 104 uint32_t PKA_MEM_MAP11; /* Address Offset: 0x082C */ 105 uint32_t PKA_MEM_MAP12; /* Address Offset: 0x0830 */ 106 uint32_t PKA_MEM_MAP13; /* Address Offset: 0x0834 */ 107 uint32_t PKA_MEM_MAP14; /* Address Offset: 0x0838 */ 108 uint32_t PKA_MEM_MAP15; /* Address Offset: 0x083C */ 109 uint32_t PKA_MEM_MAP16; /* Address Offset: 0x0840 */ 110 uint32_t PKA_MEM_MAP17; /* Address Offset: 0x0844 */ 111 uint32_t PKA_MEM_MAP18; /* Address Offset: 0x0848 */ 112 uint32_t PKA_MEM_MAP19; /* Address Offset: 0x084C */ 113 uint32_t PKA_MEM_MAP20; /* Address Offset: 0x0850 */ 114 uint32_t PKA_MEM_MAP21; /* Address Offset: 0x0854 */ 115 uint32_t PKA_MEM_MAP22; /* Address Offset: 0x0858 */ 116 uint32_t PKA_MEM_MAP23; /* Address Offset: 0x085C */ 117 uint32_t PKA_MEM_MAP24; /* Address Offset: 0x0860 */ 118 uint32_t PKA_MEM_MAP25; /* Address Offset: 0x0864 */ 119 uint32_t PKA_MEM_MAP26; /* Address Offset: 0x0868 */ 120 uint32_t PKA_MEM_MAP27; /* Address Offset: 0x086C */ 121 uint32_t PKA_MEM_MAP28; /* Address Offset: 0x0870 */ 122 uint32_t PKA_MEM_MAP29; /* Address Offset: 0x0874 */ 123 uint32_t PKA_MEM_MAP30; /* Address Offset: 0x0878 */ 124 uint32_t PKA_MEM_MAP31; /* Address Offset: 0x087C */ 125 uint32_t PKA_OPCODE; /* Address Offset: 0x0880 */ 126 uint32_t N_NP_T0_T1_ADDR; /* Address Offset: 0x0884 */ 127 uint32_t PKA_STATUS; /* Address Offset: 0x0888 */ 128 uint32_t RESERVED088C; /* Address Offset: 0x088C */ 129 uint32_t PKA_L0; /* Address Offset: 0x0890 */ 130 uint32_t PKA_L1; /* Address Offset: 0x0894 */ 131 uint32_t PKA_L2; /* Address Offset: 0x0898 */ 132 uint32_t PKA_L3; /* Address Offset: 0x089C */ 133 uint32_t PKA_L4; /* Address Offset: 0x08A0 */ 134 uint32_t PKA_L5; /* Address Offset: 0x08A4 */ 135 uint32_t PKA_L6; /* Address Offset: 0x08A8 */ 136 uint32_t PKA_L7; /* Address Offset: 0x08AC */ 137 uint32_t PKA_PIPE_RDY; /* Address Offset: 0x08B0 */ 138 uint32_t PKA_DONE; /* Address Offset: 0x08B4 */ 139 uint32_t PKA_MON_SELECT; /* Address Offset: 0x08B8 */ 140 uint32_t PKA_DEBUG_REG_EN; /* Address Offset: 0x08BC */ 141 uint32_t DEBUG_CNT_ADDR; /* Address Offset: 0x08C0 */ 142 uint32_t DEBUG_EXT_ADDR; /* Address Offset: 0x08C4 */ 143 uint32_t PKA_DEBUG_HALT; /* Address Offset: 0x08C8 */ 144 uint32_t RESERVED08CC; /* Address Offset: 0x08CC */ 145 uint32_t PKA_MON_READ; /* Address Offset: 0x08D0 */ 146 uint32_t PKA_INT_ENA; /* Address Offset: 0x08D4 */ 147 uint32_t PKA_INT_ST; /* Address Offset: 0x08D8 */ 148 uint32_t TD0_TD1_TX_ADDR; /* Address Offset: 0x08DC */ 149 uint32_t RESERVED08E0[456]; /* Address Offset: 0x08E0 */ 150 uint32_t SRAM_ADDR; /* Address Offset: 0x1000 */ 151 }; 152 153 /****************************************************************************************/ 154 /* */ 155 /* Register Bitmap Section */ 156 /* */ 157 /****************************************************************************************/ 158 /******************************************RKCE******************************************/ 159 /* CLK_CTL */ 160 #define RKCE_CLK_CTL_OFFSET (0x0U) 161 #define RKCE_CLK_CTL_AUTO_CLKGATE_EN_SHIFT (0U) 162 #define RKCE_CLK_CTL_AUTO_CLKGATE_EN_MASK (0x1U << RKCE_CLK_CTL_AUTO_CLKGATE_EN_SHIFT) 163 /* RST_CTL */ 164 #define RKCE_RST_CTL_OFFSET (0x4U) 165 #define RKCE_RST_CTL_SW_SYMM_RESET_SHIFT (0U) 166 #define RKCE_RST_CTL_SW_SYMM_RESET_MASK (0x1U << RKCE_RST_CTL_SW_SYMM_RESET_SHIFT) 167 #define RKCE_RST_CTL_SW_HASH_RESET_SHIFT (1U) 168 #define RKCE_RST_CTL_SW_HASH_RESET_MASK (0x1U << RKCE_RST_CTL_SW_HASH_RESET_SHIFT) 169 #define RKCE_RST_CTL_SW_PKA_RESET_SHIFT (2U) 170 #define RKCE_RST_CTL_SW_PKA_RESET_MASK (0x1U << RKCE_RST_CTL_SW_PKA_RESET_SHIFT) 171 #define CRYPTO_CH0_KEY_0 0x0180 172 /* TD_ADDR */ 173 #define RKCE_TD_ADDR_OFFSET (0x200U) 174 #define RKCE_TD_ADDR_TD_ADDR_SHIFT (0U) 175 #define RKCE_TD_ADDR_TD_ADDR_MASK (0xFFFFFFFFU << RKCE_TD_ADDR_TD_ADDR_SHIFT) 176 /* TD_LOAD_CTRL */ 177 #define RKCE_TD_LOAD_CTRL_OFFSET (0x204U) 178 #define RKCE_TD_LOAD_CTRL_SYMM_TLR_SHIFT (0U) 179 #define RKCE_TD_LOAD_CTRL_SYMM_TLR_MASK (0x1U << RKCE_TD_LOAD_CTRL_SYMM_TLR_SHIFT) 180 #define RKCE_TD_LOAD_CTRL_HASH_TLR_SHIFT (1U) 181 #define RKCE_TD_LOAD_CTRL_HASH_TLR_MASK (0x1U << RKCE_TD_LOAD_CTRL_HASH_TLR_SHIFT) 182 /* SYMM_INT_ST */ 183 #define RKCE_SYMM_INT_ST_OFFSET (0x214U) 184 #define RKCE_SYMM_INT_ST_TD_DONE_SHIFT (0U) 185 #define RKCE_SYMM_INT_ST_TD_DONE_MASK (0x1U << RKCE_SYMM_INT_ST_TD_DONE_SHIFT) 186 #define RKCE_SYMM_INT_ST_DST_ERROR_SHIFT (1U) 187 #define RKCE_SYMM_INT_ST_DST_ERROR_MASK (0x1U << RKCE_SYMM_INT_ST_DST_ERROR_SHIFT) 188 #define RKCE_SYMM_INT_ST_SRC_ERROR_SHIFT (2U) 189 #define RKCE_SYMM_INT_ST_SRC_ERROR_MASK (0x1U << RKCE_SYMM_INT_ST_SRC_ERROR_SHIFT) 190 #define RKCE_SYMM_INT_ST_TD_ERROR_SHIFT (3U) 191 #define RKCE_SYMM_INT_ST_TD_ERROR_MASK (0x1U << RKCE_SYMM_INT_ST_TD_ERROR_SHIFT) 192 #define RKCE_SYMM_INT_ST_NE_LEN_SHIFT (4U) 193 #define RKCE_SYMM_INT_ST_NE_LEN_MASK (0x1U << RKCE_SYMM_INT_ST_NE_LEN_SHIFT) 194 #define RKCE_SYMM_INT_ST_LOCKSTEP_ERROR_SHIFT (5U) 195 #define RKCE_SYMM_INT_ST_LOCKSTEP_ERROR_MASK (0x1U << RKCE_SYMM_INT_ST_LOCKSTEP_ERROR_SHIFT) 196 /* SYMM_TD_ID */ 197 #define RKCE_SYMM_TD_ID_OFFSET (0x218U) 198 #define RKCE_SYMM_TD_ID (0x0U) 199 #define RKCE_SYMM_TD_ID_STDID_SHIFT (0U) 200 #define RKCE_SYMM_TD_ID_STDID_MASK (0xFFFFFFFFU << RKCE_SYMM_TD_ID_STDID_SHIFT) 201 /* SYMM_TD_ST */ 202 #define RKCE_SYMM_TD_ST_OFFSET (0x21CU) 203 #define RKCE_SYMM_TD_ST (0x0U) 204 #define RKCE_SYMM_TD_ST_FIRST_PKG_FLAG_SHIFT (0U) 205 #define RKCE_SYMM_TD_ST_FIRST_PKG_FLAG_MASK (0x1U << RKCE_SYMM_TD_ST_FIRST_PKG_FLAG_SHIFT) 206 #define RKCE_SYMM_TD_ST_LAST_PKG_FLAG_SHIFT (1U) 207 #define RKCE_SYMM_TD_ST_LAST_PKG_FLAG_MASK (0x1U << RKCE_SYMM_TD_ST_LAST_PKG_FLAG_SHIFT) 208 #define RKCE_SYMM_TD_ST_DMA_START_FLAG_SHIFT (2U) 209 #define RKCE_SYMM_TD_ST_DMA_START_FLAG_MASK (0x1U << RKCE_SYMM_TD_ST_DMA_START_FLAG_SHIFT) 210 #define RKCE_SYMM_TD_ST_PRMPT_PKG_FLGA_SHIFT (3U) 211 #define RKCE_SYMM_TD_ST_PRMPT_PKG_FLGA_MASK (0x1U << RKCE_SYMM_TD_ST_PRMPT_PKG_FLGA_SHIFT) 212 /* SYMM_CONTEXT_SIZE */ 213 #define RKCE_SYMM_CONTEXT_SIZE_OFFSET (0x224U) 214 #define RKCE_SYMM_CONTEXT_SIZE (0x20U) 215 /* HASH_INT_ST */ 216 #define RKCE_HASH_INT_ST_OFFSET (0x234U) 217 #define RKCE_HASH_INT_ST_TD_DONE_SHIFT (0U) 218 #define RKCE_HASH_INT_ST_TD_DONE_MASK (0x1U << RKCE_HASH_INT_ST_TD_DONE_SHIFT) 219 #define RKCE_HASH_INT_ST_DST_ERROR_SHIFT (1U) 220 #define RKCE_HASH_INT_ST_DST_ERROR_MASK (0x1U << RKCE_HASH_INT_ST_DST_ERROR_SHIFT) 221 #define RKCE_HASH_INT_ST_SRC_ERROR_SHIFT (2U) 222 #define RKCE_HASH_INT_ST_SRC_ERROR_MASK (0x1U << RKCE_HASH_INT_ST_SRC_ERROR_SHIFT) 223 #define RKCE_HASH_INT_ST_TD_ERROR_SHIFT (3U) 224 #define RKCE_HASH_INT_ST_TD_ERROR_MASK (0x1U << RKCE_HASH_INT_ST_TD_ERROR_SHIFT) 225 #define RKCE_HASH_INT_ST_NE_LEN_SHIFT (4U) 226 #define RKCE_HASH_INT_ST_NE_LEN_MASK (0x1U << RKCE_HASH_INT_ST_NE_LEN_SHIFT) 227 #define RKCE_HASH_INT_ST_LOCKSTEP_ERROR_SHIFT (5U) 228 #define RKCE_HASH_INT_ST_LOCKSTEP_ERROR_MASK (0x1U << RKCE_HASH_INT_ST_LOCKSTEP_ERROR_SHIFT) 229 /* HASH_TD_ID */ 230 #define RKCE_HASH_TD_ID_OFFSET (0x238U) 231 #define RKCE_HASH_TD_ID (0x0U) 232 #define RKCE_HASH_TD_ID_HTDID_SHIFT (0U) 233 #define RKCE_HASH_TD_ID_HTDID_MASK (0xFFFFFFFFU << RKCE_HASH_TD_ID_HTDID_SHIFT) 234 /* HASH_TD_ST */ 235 #define RKCE_HASH_TD_ST_OFFSET (0x23CU) 236 #define RKCE_HASH_TD_ST (0x0U) 237 #define RKCE_HASH_TD_ST_FIRST_PKG_FLAG_SHIFT (0U) 238 #define RKCE_HASH_TD_ST_FIRST_PKG_FLAG_MASK (0x1U << RKCE_HASH_TD_ST_FIRST_PKG_FLAG_SHIFT) 239 #define RKCE_HASH_TD_ST_LAST_PKG_FLAG_SHIFT (1U) 240 #define RKCE_HASH_TD_ST_LAST_PKG_FLAG_MASK (0x1U << RKCE_HASH_TD_ST_LAST_PKG_FLAG_SHIFT) 241 #define RKCE_HASH_TD_ST_DMA_START_FLAG_SHIFT (2U) 242 #define RKCE_HASH_TD_ST_DMA_START_FLAG_MASK (0x1U << RKCE_HASH_TD_ST_DMA_START_FLAG_SHIFT) 243 #define RKCE_HASH_TD_ST_PRMPT_PKG_FLGA_SHIFT (3U) 244 #define RKCE_HASH_TD_ST_PRMPT_PKG_FLGA_MASK (0x1U << RKCE_HASH_TD_ST_PRMPT_PKG_FLGA_SHIFT) 245 /* HASH_CONTEXT_SIZE */ 246 #define RKCE_HASH_CONTEXT_SIZE_OFFSET (0x244U) 247 #define RKCE_HASH_CONTEXT_SIZE (0xD0U) 248 /* TD_POP_CTRL */ 249 #define RKCE_TD_POP_CTRL_OFFSET (0x258U) 250 #define RKCE_TD_POP_CTRL (0x0U) 251 #define RKCE_TD_POP_CTRL_SYMM_TPR_SHIFT (0U) 252 #define RKCE_TD_POP_CTRL_SYMM_TPR_MASK (0x1U << RKCE_TD_POP_CTRL_SYMM_TPR_SHIFT) 253 #define RKCE_TD_POP_CTRL_HASH_TPR_SHIFT (1U) 254 #define RKCE_TD_POP_CTRL_HASH_TPR_MASK (0x1U << RKCE_TD_POP_CTRL_HASH_TPR_SHIFT) 255 /* ECC_CTL */ 256 #define RKCE_ECC_CTL_OFFSET (0x3F0U) 257 #define RKCE_ECC_CTL_ECC_REQ_SHIFT (0U) 258 #define RKCE_ECC_CTL_ECC_REQ_MASK (0x1U << RKCE_ECC_CTL_ECC_REQ_SHIFT) 259 #define RKCE_ECC_CTL_FUNC_SEL_SHIFT (4U) 260 #define RKCE_ECC_CTL_FUNC_SEL_MASK (0xFU << RKCE_ECC_CTL_FUNC_SEL_SHIFT) 261 #define RKCE_ECC_CTL_CURVE_MODE_SEL_SHIFT (8U) 262 #define RKCE_ECC_CTL_CURVE_MODE_SEL_MASK (0x1U << RKCE_ECC_CTL_CURVE_MODE_SEL_SHIFT) 263 #define RKCE_ECC_CTL_RAND_K_SRC_SHIFT (12U) 264 #define RKCE_ECC_CTL_RAND_K_SRC_MASK (0x1U << RKCE_ECC_CTL_RAND_K_SRC_SHIFT) 265 /* ECC_INT_EN */ 266 #define RKCE_ECC_INT_EN_OFFSET (0x3F4U) 267 #define RKCE_ECC_INT_EN_DONE_INT_EN_SHIFT (0U) 268 #define RKCE_ECC_INT_EN_DONE_INT_EN_MASK (0x1U << RKCE_ECC_INT_EN_DONE_INT_EN_SHIFT) 269 /* ECC_INT_ST */ 270 #define RKCE_ECC_INT_ST_OFFSET (0x3F8U) 271 #define RKCE_ECC_INT_ST_DONE_INT_ST_SHIFT (0U) 272 #define RKCE_ECC_INT_ST_DONE_INT_ST_MASK (0x1U << RKCE_ECC_INT_ST_DONE_INT_ST_SHIFT) 273 /* ECC_ABN_ST */ 274 #define RKCE_ECC_ABN_ST_OFFSET (0x3FCU) 275 #define RKCE_ECC_ABN_ST (0x0U) 276 #define RKCE_ECC_ABN_ST_BAD_POINT_OUT_SHIFT (0U) 277 #define RKCE_ECC_ABN_ST_BAD_POINT_OUT_MASK (0x1U << RKCE_ECC_ABN_ST_BAD_POINT_OUT_SHIFT) 278 #define RKCE_ECC_ABN_ST_BAD_T_OUT_SHIFT (1U) 279 #define RKCE_ECC_ABN_ST_BAD_T_OUT_MASK (0x1U << RKCE_ECC_ABN_ST_BAD_T_OUT_SHIFT) 280 #define RKCE_ECC_ABN_ST_BAD_S_OUT_SHIFT (2U) 281 #define RKCE_ECC_ABN_ST_BAD_S_OUT_MASK (0x1U << RKCE_ECC_ABN_ST_BAD_S_OUT_SHIFT) 282 #define RKCE_ECC_ABN_ST_BAD_R_OUT_SHIFT (3U) 283 #define RKCE_ECC_ABN_ST_BAD_R_OUT_MASK (0x1U << RKCE_ECC_ABN_ST_BAD_R_OUT_SHIFT) 284 #define RKCE_ECC_ABN_ST_BAD_R_K_MID_SHIFT (4U) 285 #define RKCE_ECC_ABN_ST_BAD_R_K_MID_MASK (0x1U << RKCE_ECC_ABN_ST_BAD_R_K_MID_SHIFT) 286 #define RKCE_ECC_ABN_ST_BAD_S_IN_SHIFT (5U) 287 #define RKCE_ECC_ABN_ST_BAD_S_IN_MASK (0x1U << RKCE_ECC_ABN_ST_BAD_S_IN_SHIFT) 288 #define RKCE_ECC_ABN_ST_BAD_R_IN_SHIFT (6U) 289 #define RKCE_ECC_ABN_ST_BAD_R_IN_MASK (0x1U << RKCE_ECC_ABN_ST_BAD_R_IN_SHIFT) 290 #define RKCE_ECC_ABN_ST_BAD_K_IN_SHIFT (7U) 291 #define RKCE_ECC_ABN_ST_BAD_K_IN_MASK (0x1U << RKCE_ECC_ABN_ST_BAD_K_IN_SHIFT) 292 #define RKCE_ECC_ABN_ST_BAD_INV_OT_SHIFT (8U) 293 #define RKCE_ECC_ABN_ST_BAD_INV_OT_MASK (0x1U << RKCE_ECC_ABN_ST_BAD_INV_OT_SHIFT) 294 /* ECC_CURVE_WIDE */ 295 #define RKCE_ECC_CURVE_WIDE_OFFSET (0x400U) 296 #define RKCE_ECC_CURVE_WIDE_CURVE_WIDE_SHIFT (0U) 297 #define RKCE_ECC_CURVE_WIDE_CURVE_WIDE_MASK (0x3FFU << RKCE_ECC_CURVE_WIDE_CURVE_WIDE_SHIFT) 298 /* ECC_MAX_CURVE_WIDE */ 299 #define RKCE_ECC_MAX_CURVE_WIDE_OFFSET (0x404U) 300 #define RKCE_ECC_MAX_CURVE_WIDE (0x100U) 301 /* ECC_DATA_ENDIAN */ 302 #define RKCE_ECC_DATA_ENDIAN_OFFSET (0x408U) 303 /* PKA_RAM_CTL */ 304 #define RKCE_PKA_RAM_CTL_OFFSET (0x480U) 305 #define RKCE_PKA_RAM_CTL_PKA_RDY BIT(0) 306 #define RKCE_PKA_RAM_CTL_RAM_PKA_RDY_SHIFT (0U) 307 #define RKCE_PKA_RAM_CTL_RAM_PKA_RDY_MASK (0x3U << RKCE_PKA_RAM_CTL_RAM_PKA_RDY_SHIFT) 308 /* PKA_RAM_ST */ 309 #define RKCE_PKA_RAM_ST_OFFSET (0x484U) 310 #define RKCE_PKA_RAM_ST (0x1U) 311 #define RKCE_PKA_RAM_ST_CLK_RAM_RDY_SHIFT (0U) 312 #define RKCE_PKA_RAM_ST_CLK_RAM_RDY_MASK (0x1U << RKCE_PKA_RAM_ST_CLK_RAM_RDY_SHIFT) 313 /* AES_VER */ 314 #define RKCE_AES_VER_OFFSET (0x680U) 315 #define RKCE_AES_VER_ECB_FLAG_SHIFT (0U) 316 #define RKCE_AES_VER_ECB_FLAG_MASK (0x1U << RKCE_AES_VER_ECB_FLAG_SHIFT) 317 #define RKCE_AES_VER_CBC_FLAG_SHIFT (1U) 318 #define RKCE_AES_VER_CBC_FLAG_MASK (0x1U << RKCE_AES_VER_CBC_FLAG_SHIFT) 319 #define RKCE_AES_VER_CTS_FLAG_SHIFT (2U) 320 #define RKCE_AES_VER_CTS_FLAG_MASK (0x1U << RKCE_AES_VER_CTS_FLAG_SHIFT) 321 #define RKCE_AES_VER_CTR_FLAG_SHIFT (3U) 322 #define RKCE_AES_VER_CTR_FLAG_MASK (0x1U << RKCE_AES_VER_CTR_FLAG_SHIFT) 323 #define RKCE_AES_VER_CFB_FLAG_SHIFT (4U) 324 #define RKCE_AES_VER_CFB_FLAG_MASK (0x1U << RKCE_AES_VER_CFB_FLAG_SHIFT) 325 #define RKCE_AES_VER_OFB_FLAG_SHIFT (5U) 326 #define RKCE_AES_VER_OFB_FLAG_MASK (0x1U << RKCE_AES_VER_OFB_FLAG_SHIFT) 327 #define RKCE_AES_VER_XTS_FLAG_SHIFT (6U) 328 #define RKCE_AES_VER_XTS_FLAG_MASK (0x1U << RKCE_AES_VER_XTS_FLAG_SHIFT) 329 #define RKCE_AES_VER_CCM_FLAG_SHIFT (7U) 330 #define RKCE_AES_VER_CCM_FLAG_MASK (0x1U << RKCE_AES_VER_CCM_FLAG_SHIFT) 331 #define RKCE_AES_VER_GCM_FLAG_SHIFT (8U) 332 #define RKCE_AES_VER_GCM_FLAG_MASK (0x1U << RKCE_AES_VER_GCM_FLAG_SHIFT) 333 #define RKCE_AES_VER_CMAC_FLAG_SHIFT (9U) 334 #define RKCE_AES_VER_CMAC_FLAG_MASK (0x1U << RKCE_AES_VER_CMAC_FLAG_SHIFT) 335 #define RKCE_AES_VER_CBC_MAC_FLAG_SHIFT (10U) 336 #define RKCE_AES_VER_CBC_MAC_FLAG_MASK (0x1U << RKCE_AES_VER_CBC_MAC_FLAG_SHIFT) 337 #define RKCE_AES_VER_BYPASS_SHIFT (12U) 338 #define RKCE_AES_VER_BYPASS_MASK (0x1U << RKCE_AES_VER_BYPASS_SHIFT) 339 #define RKCE_AES_VER_AES128_FLAG_SHIFT (16U) 340 #define RKCE_AES_VER_AES128_FLAG_MASK (0x1U << RKCE_AES_VER_AES128_FLAG_SHIFT) 341 #define RKCE_AES_VER_AES192_FLAG_SHIFT (17U) 342 #define RKCE_AES_VER_AES192_FLAG_MASK (0x1U << RKCE_AES_VER_AES192_FLAG_SHIFT) 343 #define RKCE_AES_VER_AES256_FLAG_SHIFT (18U) 344 #define RKCE_AES_VER_AES256_FLAG_MASK (0x1U << RKCE_AES_VER_AES256_FLAG_SHIFT) 345 #define RKCE_AES_VER_LOCKSTEP_FLAG_SHIFT (20U) 346 #define RKCE_AES_VER_LOCKSTEP_FLAG_MASK (0x1U << RKCE_AES_VER_LOCKSTEP_FLAG_SHIFT) 347 #define RKCE_AES_VER_SECURE_FLAG_SHIFT (21U) 348 #define RKCE_AES_VER_SECURE_FLAG_MASK (0x1U << RKCE_AES_VER_SECURE_FLAG_SHIFT) 349 /* DES_VER */ 350 #define RKCE_DES_VER_OFFSET (0x684U) 351 #define RKCE_DES_VER_ECB_FLAG_SHIFT (0U) 352 #define RKCE_DES_VER_ECB_FLAG_MASK (0x1U << RKCE_DES_VER_ECB_FLAG_SHIFT) 353 #define RKCE_DES_VER_CBC_FLAG_SHIFT (1U) 354 #define RKCE_DES_VER_CBC_FLAG_MASK (0x1U << RKCE_DES_VER_CBC_FLAG_SHIFT) 355 #define RKCE_DES_VER_CFB_FLAG_SHIFT (4U) 356 #define RKCE_DES_VER_CFB_FLAG_MASK (0x1U << RKCE_DES_VER_CFB_FLAG_SHIFT) 357 #define RKCE_DES_VER_OFB_FLAG_SHIFT (5U) 358 #define RKCE_DES_VER_OFB_FLAG_MASK (0x1U << RKCE_DES_VER_OFB_FLAG_SHIFT) 359 #define RKCE_DES_VER_TDES_FLAG_SHIFT (16U) 360 #define RKCE_DES_VER_TDES_FLAG_MASK (0x1U << RKCE_DES_VER_TDES_FLAG_SHIFT) 361 #define RKCE_DES_VER_EEE_FLAG_SHIFT (17U) 362 #define RKCE_DES_VER_EEE_FLAG_MASK (0x1U << RKCE_DES_VER_EEE_FLAG_SHIFT) 363 #define RKCE_DES_VER_EDE_FLAG_SHIFT (18U) 364 #define RKCE_DES_VER_EDE_FLAG_MASK (0x1U << RKCE_DES_VER_EDE_FLAG_SHIFT) 365 #define RKCE_DES_VER_LOCKSTEP_FLAG_SHIFT (20U) 366 #define RKCE_DES_VER_LOCKSTEP_FLAG_MASK (0x1U << RKCE_DES_VER_LOCKSTEP_FLAG_SHIFT) 367 #define RKCE_DES_VER_SECURE_FLAG_SHIFT (21U) 368 #define RKCE_DES_VER_SECURE_FLAG_MASK (0x1U << RKCE_DES_VER_SECURE_FLAG_SHIFT) 369 /* SM4_VER */ 370 #define RKCE_SM4_VER_OFFSET (0x688U) 371 #define RKCE_SM4_VER_ECB_FLAG_SHIFT (0U) 372 #define RKCE_SM4_VER_ECB_FLAG_MASK (0x1U << RKCE_SM4_VER_ECB_FLAG_SHIFT) 373 #define RKCE_SM4_VER_CBC_FLAG_SHIFT (1U) 374 #define RKCE_SM4_VER_CBC_FLAG_MASK (0x1U << RKCE_SM4_VER_CBC_FLAG_SHIFT) 375 #define RKCE_SM4_VER_CTS_FLAG_SHIFT (2U) 376 #define RKCE_SM4_VER_CTS_FLAG_MASK (0x1U << RKCE_SM4_VER_CTS_FLAG_SHIFT) 377 #define RKCE_SM4_VER_CTR_FLAG_SHIFT (3U) 378 #define RKCE_SM4_VER_CTR_FLAG_MASK (0x1U << RKCE_SM4_VER_CTR_FLAG_SHIFT) 379 #define RKCE_SM4_VER_CFB_FLAG_SHIFT (4U) 380 #define RKCE_SM4_VER_CFB_FLAG_MASK (0x1U << RKCE_SM4_VER_CFB_FLAG_SHIFT) 381 #define RKCE_SM4_VER_OFB_FLAG_SHIFT (5U) 382 #define RKCE_SM4_VER_OFB_FLAG_MASK (0x1U << RKCE_SM4_VER_OFB_FLAG_SHIFT) 383 #define RKCE_SM4_VER_XTS_FLAG_SHIFT (6U) 384 #define RKCE_SM4_VER_XTS_FLAG_MASK (0x1U << RKCE_SM4_VER_XTS_FLAG_SHIFT) 385 #define RKCE_SM4_VER_CCM_FLAG_SHIFT (7U) 386 #define RKCE_SM4_VER_CCM_FLAG_MASK (0x1U << RKCE_SM4_VER_CCM_FLAG_SHIFT) 387 #define RKCE_SM4_VER_GCM_FLAG_SHIFT (8U) 388 #define RKCE_SM4_VER_GCM_FLAG_MASK (0x1U << RKCE_SM4_VER_GCM_FLAG_SHIFT) 389 #define RKCE_SM4_VER_CMAC_FLAG_SHIFT (9U) 390 #define RKCE_SM4_VER_CMAC_FLAG_MASK (0x1U << RKCE_SM4_VER_CMAC_FLAG_SHIFT) 391 #define RKCE_SM4_VER_CBC_MAC_FLAG_SHIFT (10U) 392 #define RKCE_SM4_VER_CBC_MAC_FLAG_MASK (0x1U << RKCE_SM4_VER_CBC_MAC_FLAG_SHIFT) 393 #define RKCE_SM4_VER_LOCKSTEP_FLAG_SHIFT (20U) 394 #define RKCE_SM4_VER_LOCKSTEP_FLAG_MASK (0x1U << RKCE_SM4_VER_LOCKSTEP_FLAG_SHIFT) 395 #define RKCE_SM4_VER_SECURE_FLAG_SHIFT (21U) 396 #define RKCE_SM4_VER_SECURE_FLAG_MASK (0x1U << RKCE_SM4_VER_SECURE_FLAG_SHIFT) 397 /* HASH_VER */ 398 #define RKCE_HASH_VER_OFFSET (0x68CU) 399 #define RKCE_HASH_VER_SHA1_FLAG_SHIFT (0U) 400 #define RKCE_HASH_VER_SHA1_FLAG_MASK (0x1U << RKCE_HASH_VER_SHA1_FLAG_SHIFT) 401 #define RKCE_HASH_VER_SHA224_FLAG_SHIFT (1U) 402 #define RKCE_HASH_VER_SHA224_FLAG_MASK (0x1U << RKCE_HASH_VER_SHA224_FLAG_SHIFT) 403 #define RKCE_HASH_VER_SHA256_FLAG_SHIFT (2U) 404 #define RKCE_HASH_VER_SHA256_FLAG_MASK (0x1U << RKCE_HASH_VER_SHA256_FLAG_SHIFT) 405 #define RKCE_HASH_VER_SHA384_FLAG_SHIFT (3U) 406 #define RKCE_HASH_VER_SHA384_FLAG_MASK (0x1U << RKCE_HASH_VER_SHA384_FLAG_SHIFT) 407 #define RKCE_HASH_VER_SHA512_FLAG_SHIFT (4U) 408 #define RKCE_HASH_VER_SHA512_FLAG_MASK (0x1U << RKCE_HASH_VER_SHA512_FLAG_SHIFT) 409 #define RKCE_HASH_VER_SHA512_224_FLAG_SHIFT (5U) 410 #define RKCE_HASH_VER_SHA512_224_FLAG_MASK (0x1U << RKCE_HASH_VER_SHA512_224_FLAG_SHIFT) 411 #define RKCE_HASH_VER_SHA512_256_FLAG_SHIFT (6U) 412 #define RKCE_HASH_VER_SHA512_256_FLAG_MASK (0x1U << RKCE_HASH_VER_SHA512_256_FLAG_SHIFT) 413 #define RKCE_HASH_VER_MD5_FLAG_SHIFT (7U) 414 #define RKCE_HASH_VER_MD5_FLAG_MASK (0x1U << RKCE_HASH_VER_MD5_FLAG_SHIFT) 415 #define RKCE_HASH_VER_SM3_FLAG_SHIFT (8U) 416 #define RKCE_HASH_VER_SM3_FLAG_MASK (0x1U << RKCE_HASH_VER_SM3_FLAG_SHIFT) 417 #define RKCE_HASH_VER_LOCKSTEP_FLAG_SHIFT (20U) 418 #define RKCE_HASH_VER_LOCKSTEP_FLAG_MASK (0x1U << RKCE_HASH_VER_LOCKSTEP_FLAG_SHIFT) 419 /* HMAC_VER */ 420 #define RKCE_HMAC_VER_OFFSET (0x690U) 421 #define RKCE_HMAC_VER_SHA1_FLAG_SHIFT (0U) 422 #define RKCE_HMAC_VER_SHA1_FLAG_MASK (0x1U << RKCE_HMAC_VER_SHA1_FLAG_SHIFT) 423 #define RKCE_HMAC_VER_SHA256_FLAG_SHIFT (1U) 424 #define RKCE_HMAC_VER_SHA256_FLAG_MASK (0x1U << RKCE_HMAC_VER_SHA256_FLAG_SHIFT) 425 #define RKCE_HMAC_VER_SHA512_FLAG_SHIFT (2U) 426 #define RKCE_HMAC_VER_SHA512_FLAG_MASK (0x1U << RKCE_HMAC_VER_SHA512_FLAG_SHIFT) 427 #define RKCE_HMAC_VER_MD5_FLAG_SHIFT (3U) 428 #define RKCE_HMAC_VER_MD5_FLAG_MASK (0x1U << RKCE_HMAC_VER_MD5_FLAG_SHIFT) 429 #define RKCE_HMAC_VER_SM3_FLAG_SHIFT (4U) 430 #define RKCE_HMAC_VER_SM3_FLAG_MASK (0x1U << RKCE_HMAC_VER_SM3_FLAG_SHIFT) 431 #define RKCE_HMAC_VER_LOCKSTEP_FLAG_SHIFT (20U) 432 #define RKCE_HMAC_VER_LOCKSTEP_FLAG_MASK (0x1U << RKCE_HMAC_VER_LOCKSTEP_FLAG_SHIFT) 433 /* PKA_VER */ 434 #define RKCE_PKA_VER_OFFSET (0x698U) 435 /* EXTRA_FEATURE */ 436 #define RKCE_EXTRA_FEATURE_OFFSET (0x69CU) 437 #define RKCE_EXTRA_FEATURE_AXI_EXPAND_BIT_SHIFT (0U) 438 #define RKCE_EXTRA_FEATURE_AXI_EXPAND_BIT_MASK (0xFU << RKCE_EXTRA_FEATURE_AXI_EXPAND_BIT_SHIFT) 439 /* CE_VER */ 440 #define RKCE_CE_VER_OFFSET (0x6F0U) 441 /* PKA_MEM_MAP0 */ 442 #define RKCE_PKA_MEM_MAP0_OFFSET (0x800U) 443 #define RKCE_MAP_REG_NUM (32) 444 /* PKA_OPCODE */ 445 #define RKCE_PKA_OPCODE_OFFSET (0x880U) 446 #define RKCE_PKA_OPCODE_TAG_SHIFT (0U) 447 #define RKCE_PKA_OPCODE_TAG_MASK (0x3FU << RKCE_PKA_OPCODE_TAG_SHIFT) 448 #define RKCE_PKA_OPCODE_REG_R_SHIFT (6U) 449 #define RKCE_PKA_OPCODE_REG_R_MASK (0x3FU << RKCE_PKA_OPCODE_REG_R_SHIFT) 450 #define RKCE_PKA_OPCODE_R_DIS_SHIFT (11U) 451 #define RKCE_PKA_OPCODE_REG_B_SHIFT (12U) 452 #define RKCE_PKA_OPCODE_REG_B_MASK (0x3FU << RKCE_PKA_OPCODE_REG_B_SHIFT) 453 #define RKCE_PKA_OPCODE_B_IMMED_SHIFT (17U) 454 #define RKCE_PKA_OPCODE_REG_A_SHIFT (18U) 455 #define RKCE_PKA_OPCODE_REG_A_MASK (0x3FU << RKCE_PKA_OPCODE_REG_A_SHIFT) 456 #define RKCE_PKA_OPCODE_A_IMMED_SHIFT (23U) 457 #define RKCE_PKA_OPCODE_LEN_SHIFT (24U) 458 #define RKCE_PKA_OPCODE_LEN_MASK (0x7U << RKCE_PKA_OPCODE_LEN_SHIFT) 459 #define RKCE_PKA_OPCODE_OPCODE_SHIFT (27U) 460 #define RKCE_PKA_OPCODE_OPCODE_MASK (0x1FU << RKCE_PKA_OPCODE_OPCODE_SHIFT) 461 /* N_NP_T0_T1_ADDR */ 462 #define RKCE_N_NP_T0_T1_ADDR_OFFSET (0x884U) 463 #define RKCE_N_NP_T0_T1_ADDR_REG_N_SHIFT (0U) 464 #define RKCE_N_NP_T0_T1_ADDR_REG_N_MASK (0x1FU << RKCE_N_NP_T0_T1_ADDR_REG_N_SHIFT) 465 #define RKCE_N_NP_T0_T1_ADDR_REG_NP_SHIFT (5U) 466 #define RKCE_N_NP_T0_T1_ADDR_REG_NP_MASK (0x1FU << RKCE_N_NP_T0_T1_ADDR_REG_NP_SHIFT) 467 #define RKCE_N_NP_T0_T1_ADDR_REG_T0_SHIFT (10U) 468 #define RKCE_N_NP_T0_T1_ADDR_REG_T0_MASK (0x1FU << RKCE_N_NP_T0_T1_ADDR_REG_T0_SHIFT) 469 #define RKCE_N_NP_T0_T1_ADDR_REG_T1_SHIFT (15U) 470 #define RKCE_N_NP_T0_T1_ADDR_REG_T1_MASK (0x1FU << RKCE_N_NP_T0_T1_ADDR_REG_T1_SHIFT) 471 /* PKA_STATUS */ 472 #define RKCE_PKA_STATUS_OFFSET (0x888U) 473 #define RKCE_PKA_STATUS (0x1U) 474 #define RKCE_PKA_STATUS_PIPE_IS_BUSY_SHIFT (0U) 475 #define RKCE_PKA_STATUS_PIPE_IS_BUSY_MASK (0x1U << RKCE_PKA_STATUS_PIPE_IS_BUSY_SHIFT) 476 #define RKCE_PKA_STATUS_PKA_BUSY_SHIFT (1U) 477 #define RKCE_PKA_STATUS_PKA_BUSY_MASK (0x1U << RKCE_PKA_STATUS_PKA_BUSY_SHIFT) 478 #define RKCE_PKA_STATUS_ALU_OUT_ZERO_SHIFT (2U) 479 #define RKCE_PKA_STATUS_ALU_OUT_ZERO_MASK (0x1U << RKCE_PKA_STATUS_ALU_OUT_ZERO_SHIFT) 480 #define RKCE_PKA_STATUS_ALU_MOD_OVFLW_SHIFT (3U) 481 #define RKCE_PKA_STATUS_ALU_MOD_OVFLW_MASK (0x1U << RKCE_PKA_STATUS_ALU_MOD_OVFLW_SHIFT) 482 #define RKCE_PKA_STATUS_DIV_BY_ZERO_SHIFT (4U) 483 #define RKCE_PKA_STATUS_DIV_BY_ZERO_MASK (0x1U << RKCE_PKA_STATUS_DIV_BY_ZERO_SHIFT) 484 #define RKCE_PKA_STATUS_ALU_CARRY_SHIFT (5U) 485 #define RKCE_PKA_STATUS_ALU_CARRY_MASK (0x1U << RKCE_PKA_STATUS_ALU_CARRY_SHIFT) 486 #define RKCE_PKA_STATUS_ALU_SIGN_OUT_SHIFT (6U) 487 #define RKCE_PKA_STATUS_ALU_SIGN_OUT_MASK (0x1U << RKCE_PKA_STATUS_ALU_SIGN_OUT_SHIFT) 488 #define RKCE_PKA_STATUS_MODINV_OF_ZERO_SHIFT (7U) 489 #define RKCE_PKA_STATUS_MODINV_OF_ZERO_MASK (0x1U << RKCE_PKA_STATUS_MODINV_OF_ZERO_SHIFT) 490 #define RKCE_PKA_STATUS_PKA_CPU_BUSY_SHIFT (8U) 491 #define RKCE_PKA_STATUS_PKA_CPU_BUSY_MASK (0x1U << RKCE_PKA_STATUS_PKA_CPU_BUSY_SHIFT) 492 #define RKCE_PKA_STATUS_OPCODE_SHIFT (9U) 493 #define RKCE_PKA_STATUS_OPCODE_MASK (0x1FU << RKCE_PKA_STATUS_OPCODE_SHIFT) 494 #define RKCE_PKA_STATUS_TAG_SHIFT (14U) 495 #define RKCE_PKA_STATUS_TAG_MASK (0x3FU << RKCE_PKA_STATUS_TAG_SHIFT) 496 /* PKA_L0 */ 497 #define RKCE_PKA_L0_OFFSET (0x890U) 498 #define RKCE_LEN_REG_NUM (8) 499 /* PKA_PIPE_RDY */ 500 #define RKCE_PKA_PIPE_RDY_OFFSET (0x8B0U) 501 #define RKCE_PKA_PIPE_RDY (0x1U) 502 #define RKCE_PKA_PIPE_RDY_PKA_PIPE_RDY_SHIFT (0U) 503 #define RKCE_PKA_PIPE_RDY_PKA_PIPE_RDY_MASK (0x1U << RKCE_PKA_PIPE_RDY_PKA_PIPE_RDY_SHIFT) 504 /* PKA_DONE */ 505 #define RKCE_PKA_DONE_OFFSET (0x8B4U) 506 #define RKCE_PKA_DONE (0x1U) 507 #define RKCE_PKA_DONE_PKA_DONE_SHIFT (0U) 508 #define RKCE_PKA_DONE_PKA_DONE_MASK (0x1U << RKCE_PKA_DONE_PKA_DONE_SHIFT) 509 /* PKA_INT_ENA */ 510 #define RKCE_PKA_INT_ENA_OFFSET (0x8D4U) 511 #define RKCE_PKA_INT_ENA_PKA_INT_ENA_SHIFT (0U) 512 #define RKCE_PKA_INT_ENA_PKA_INT_ENA_MASK (0x1U << RKCE_PKA_INT_ENA_PKA_INT_ENA_SHIFT) 513 /* PKA_INT_ST */ 514 #define RKCE_PKA_INT_ST_OFFSET (0x8D8U) 515 #define RKCE_PKA_INT_ST_PKA_INT_ST_SHIFT (0U) 516 #define RKCE_PKA_INT_ST_PKA_INT_ST_MASK (0x1U << RKCE_PKA_INT_ST_PKA_INT_ST_SHIFT) 517 /* TD0_TD1_TX_ADDR */ 518 #define RKCE_TD0_TD1_TX_ADDR_OFFSET (0x8DCU) 519 #define RKCE_TD0_TD1_TX_ADDR_REG_TD0_SHIFT (0U) 520 #define RKCE_TD0_TD1_TX_ADDR_REG_TD0_MASK (0x1FU << RKCE_TD0_TD1_TX_ADDR_REG_TD0_SHIFT) 521 #define RKCE_TD0_TD1_TX_ADDR_REG_TD1_SHIFT (5U) 522 #define RKCE_TD0_TD1_TX_ADDR_REG_TD1_MASK (0x1FU << RKCE_TD0_TD1_TX_ADDR_REG_TD1_SHIFT) 523 #define RKCE_TD0_TD1_TX_ADDR_REG_TX_SHIFT (10U) 524 #define RKCE_TD0_TD1_TX_ADDR_REG_TX_MASK (0x1FU << RKCE_TD0_TD1_TX_ADDR_REG_TX_SHIFT) 525 #define RKCE_TD0_TD1_TX_ADDR_PKA_ASCA_EN_SHIFT (31U) 526 #define RKCE_TD0_TD1_TX_ADDR_PKA_ASCA_EN_MASK (0x1U << RKCE_TD0_TD1_TX_ADDR_PKA_ASCA_EN_SHIFT) 527 /* SRAM_ADDR */ 528 #define RKCE_SRAM_ADDR_OFFSET (0x1000U) 529 #define RKCE_SRAM_ADDR_SRAM_ADDR_SHIFT (0U) 530 #define RKCE_SRAM_ADDR_SRAM_ADDR_MASK (0xFFFFFFFFU << RKCE_SRAM_ADDR_SRAM_ADDR_SHIFT) 531 532 #define RKCE_SRAM_SIZE (0x1000U) 533 534 #endif /* __RKCE_REG_H */ 535