1*a3d00835SJoseph Chen /* SPDX-License-Identifier: GPL-2.0+ */ 2*a3d00835SJoseph Chen /* 3*a3d00835SJoseph Chen * (C) Copyright 2019 Rockchip Electronics Co., Ltd 4*a3d00835SJoseph Chen */ 5*a3d00835SJoseph Chen 6*a3d00835SJoseph Chen #ifndef _ROCKCHIP_CRYPTO_V1_H_ 7*a3d00835SJoseph Chen #define _ROCKCHIP_CRYPTO_V1_H_ 8*a3d00835SJoseph Chen 9*a3d00835SJoseph Chen struct rk_crypto_reg { 10*a3d00835SJoseph Chen u32 crypto_intsts; 11*a3d00835SJoseph Chen u32 crypto_intena; 12*a3d00835SJoseph Chen u32 crypto_ctrl; 13*a3d00835SJoseph Chen u32 crypto_conf; 14*a3d00835SJoseph Chen u32 crypto_brdmas; 15*a3d00835SJoseph Chen u32 crypto_btdmas; 16*a3d00835SJoseph Chen u32 crypto_brdmal; 17*a3d00835SJoseph Chen u32 crypto_hrdmas; 18*a3d00835SJoseph Chen u32 crypto_hrdmal; 19*a3d00835SJoseph Chen u32 reserved0[(0x80 - 0x24) / 4]; 20*a3d00835SJoseph Chen 21*a3d00835SJoseph Chen u32 crypto_aes_ctrl; 22*a3d00835SJoseph Chen u32 crypto_aes_sts; 23*a3d00835SJoseph Chen u32 crypto_aes_din[4]; 24*a3d00835SJoseph Chen u32 crypto_aes_dout[4]; 25*a3d00835SJoseph Chen u32 crypto_aes_iv[4]; 26*a3d00835SJoseph Chen u32 crypto_aes_key[8]; 27*a3d00835SJoseph Chen u32 crypto_aes_cnt[4]; 28*a3d00835SJoseph Chen u32 reserved1[(0x100 - 0xe8) / 4]; 29*a3d00835SJoseph Chen 30*a3d00835SJoseph Chen u32 crypto_tdes_ctrl; 31*a3d00835SJoseph Chen u32 crypto_tdes_sts; 32*a3d00835SJoseph Chen u32 crypto_tdes_din[2]; 33*a3d00835SJoseph Chen u32 crypto_tdes_dout[2]; 34*a3d00835SJoseph Chen u32 crypto_tdes_iv[2]; 35*a3d00835SJoseph Chen u32 crypto_tdes_key1[2]; 36*a3d00835SJoseph Chen u32 crypto_tdes_key2[2]; 37*a3d00835SJoseph Chen u32 crypto_tdes_key3[2]; 38*a3d00835SJoseph Chen u32 reserved2[(0x180 - 0x138) / 4]; 39*a3d00835SJoseph Chen 40*a3d00835SJoseph Chen u32 crypto_hash_ctrl; 41*a3d00835SJoseph Chen u32 crypto_hash_sts; 42*a3d00835SJoseph Chen u32 crypto_hash_msg_len; 43*a3d00835SJoseph Chen u32 crypto_hash_dout[8]; 44*a3d00835SJoseph Chen u32 crypto_hash_seed[5]; 45*a3d00835SJoseph Chen u32 reserved3[(0x200 - 0x1c0) / 4]; 46*a3d00835SJoseph Chen 47*a3d00835SJoseph Chen u32 crypto_trng_ctrl; 48*a3d00835SJoseph Chen u32 crypto_trng_dout[8]; 49*a3d00835SJoseph Chen u32 reserved4[(0x280 - 0x224) / 4]; 50*a3d00835SJoseph Chen 51*a3d00835SJoseph Chen u32 crypto_pka_ctrl; 52*a3d00835SJoseph Chen u32 reserved5[(0x400 - 0x284) / 4]; 53*a3d00835SJoseph Chen 54*a3d00835SJoseph Chen u32 crypto_pka_m[(0x500 - 0x400) / 4]; 55*a3d00835SJoseph Chen u32 crypto_pka_c[(0x600 - 0x500) / 4]; 56*a3d00835SJoseph Chen u32 crypto_pka_n[(0x700 - 0x600) / 4]; 57*a3d00835SJoseph Chen u32 crypto_pka_e; 58*a3d00835SJoseph Chen }; 59*a3d00835SJoseph Chen 60*a3d00835SJoseph Chen check_member(rk_crypto_reg, crypto_pka_e, 0x700); 61*a3d00835SJoseph Chen 62*a3d00835SJoseph Chen /************************ Register bits definition ****************************/ 63*a3d00835SJoseph Chen /* CRYPTO_HASH_CTRL */ 64*a3d00835SJoseph Chen #define ENGINE_SELECTION_SHA1 0x0 65*a3d00835SJoseph Chen #define ENGINE_SELECTION_MD5 0x1 66*a3d00835SJoseph Chen #define ENGINE_SELECTION_SHA256 0x2 67*a3d00835SJoseph Chen #define HASH_SWAP_DO 0x8 68*a3d00835SJoseph Chen 69*a3d00835SJoseph Chen /* CRYPTO_CONF */ 70*a3d00835SJoseph Chen #define HR_ADDR_MODE BIT(8) 71*a3d00835SJoseph Chen #define BT_ADDR_MODE BIT(7) 72*a3d00835SJoseph Chen #define BR_ADDR_MODE BIT(6) 73*a3d00835SJoseph Chen #define BYTESWAP_HRFIFO BIT(5) 74*a3d00835SJoseph Chen #define BYTESWAP_BTFIFO BIT(4) 75*a3d00835SJoseph Chen #define BYTESWAP_BRFIFO BIT(3) 76*a3d00835SJoseph Chen #define DESSEL BIT(2) 77*a3d00835SJoseph Chen 78*a3d00835SJoseph Chen /* CRYPTO_CTRL */ 79*a3d00835SJoseph Chen #define TRNG_FLUSH BIT(9) 80*a3d00835SJoseph Chen #define TRNG_START BIT(8) 81*a3d00835SJoseph Chen #define PKA_FLUSH BIT(7) 82*a3d00835SJoseph Chen #define HASH_FLUSH BIT(6) 83*a3d00835SJoseph Chen #define BLOCK_FLUSH BIT(5) 84*a3d00835SJoseph Chen #define PKA_START BIT(4) 85*a3d00835SJoseph Chen #define HASH_START BIT(3) 86*a3d00835SJoseph Chen #define BLOCK_START BIT(2) 87*a3d00835SJoseph Chen #define TDES_START BIT(1) 88*a3d00835SJoseph Chen #define AES_START BIT(0) 89*a3d00835SJoseph Chen #define PKA_HASH_CTRL (PKA_FLUSH | HASH_FLUSH) 90*a3d00835SJoseph Chen #define PKA_CTRL (PKA_FLUSH | PKA_START) 91*a3d00835SJoseph Chen 92*a3d00835SJoseph Chen /* CRYPTO_INTSTS */ 93*a3d00835SJoseph Chen #define PKA_DONE_INT BIT(5) 94*a3d00835SJoseph Chen #define HASH_DONE_INT BIT(4) 95*a3d00835SJoseph Chen #define HRDMA_ERR_INT BIT(3) 96*a3d00835SJoseph Chen #define HRDMA_DONE_INT BIT(2) 97*a3d00835SJoseph Chen #define BCDMA_ERR_INT BIT(1) 98*a3d00835SJoseph Chen #define BCDMA_DONE_INT BIT(0) 99*a3d00835SJoseph Chen 100*a3d00835SJoseph Chen /* CRYPTO_PKA_CTRL */ 101*a3d00835SJoseph Chen #define PKA_BLOCK_SIZE_512 0 102*a3d00835SJoseph Chen #define PKA_BLOCK_SIZE_1024 1 103*a3d00835SJoseph Chen #define PKA_BLOCK_SIZE_2048 2 104*a3d00835SJoseph Chen 105*a3d00835SJoseph Chen #endif 106