1*c48f1acfSLin Jinhan /* SPDX-License-Identifier: GPL-2.0+ */ 2*c48f1acfSLin Jinhan /* 3*c48f1acfSLin Jinhan * (C) Copyright 2020 Rockchip Electronics Co., Ltd 4*c48f1acfSLin Jinhan */ 5*c48f1acfSLin Jinhan 6*c48f1acfSLin Jinhan #ifndef _CRYPTO_HASH_CACHE_H_ 7*c48f1acfSLin Jinhan #define _CRYPTO_HASH_CACHE_H_ 8*c48f1acfSLin Jinhan 9*c48f1acfSLin Jinhan #define HASH_CACHE_SIZE 8192 10*c48f1acfSLin Jinhan #define CIPHER_CACHE_SIZE 8192 11*c48f1acfSLin Jinhan 12*c48f1acfSLin Jinhan typedef int (*crypto_hash_calc)(void *hw_data, const u8 *data, u32 data_len, 13*c48f1acfSLin Jinhan u8 *started_flag, u8 is_last); 14*c48f1acfSLin Jinhan 15*c48f1acfSLin Jinhan struct crypto_hash_cache { 16*c48f1acfSLin Jinhan crypto_hash_calc direct_calc; /* hardware hash callback*/ 17*c48f1acfSLin Jinhan void *user_data; 18*c48f1acfSLin Jinhan void *cache; /* virt addr for hash src data*/ 19*c48f1acfSLin Jinhan u32 cache_size; /* data in cached size */ 20*c48f1acfSLin Jinhan u32 data_align; 21*c48f1acfSLin Jinhan u32 len_align; 22*c48f1acfSLin Jinhan u32 left_len; /* left data to calc */ 23*c48f1acfSLin Jinhan u8 is_started; /* start or restart */ 24*c48f1acfSLin Jinhan u8 use_cache; /* is use cache or not*/ 25*c48f1acfSLin Jinhan u8 reserved[2]; 26*c48f1acfSLin Jinhan }; 27*c48f1acfSLin Jinhan 28*c48f1acfSLin Jinhan struct crypto_hash_cache *crypto_hash_cache_alloc(crypto_hash_calc direct_calc, 29*c48f1acfSLin Jinhan void *user_data, u32 total, 30*c48f1acfSLin Jinhan u32 data_align, 31*c48f1acfSLin Jinhan u32 len_align); 32*c48f1acfSLin Jinhan void crypto_hash_cache_free(struct crypto_hash_cache *hash_cache); 33*c48f1acfSLin Jinhan int crypto_hash_update_with_cache(struct crypto_hash_cache *hash_cache, 34*c48f1acfSLin Jinhan const u8 *data, u32 data_len); 35*c48f1acfSLin Jinhan void crypto_flush_cacheline(ulong addr, ulong size); 36*c48f1acfSLin Jinhan 37*c48f1acfSLin Jinhan #endif 38