1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2019 Rockchip Electronics Co., Ltd 4 */ 5 6 #ifndef _ROCKCHIP_OTP_H_ 7 #define _ROCKCHIP_OTP_H_ 8 9 /* OTP Register Offsets */ 10 #define OTPC_SBPI_CTRL 0x0020 11 #define OTPC_SBPI_CMD_VALID_PRE 0x0024 12 #define OTPC_SBPI_CS_VALID_PRE 0x0028 13 #define OTPC_SBPI_STATUS 0x002C 14 #define OTPC_USER_CTRL 0x0100 15 #define OTPC_USER_ADDR 0x0104 16 #define OTPC_USER_ENABLE 0x0108 17 #define OTPC_USER_QP 0x0120 18 #define OTPC_USER_Q 0x0124 19 #define OTPC_INT_STATUS 0x0304 20 #define OTPC_SBPI_CMD0_OFFSET 0x1000 21 #define OTPC_SBPI_CMD1_OFFSET 0x1004 22 23 /* OTP Register bits and masks */ 24 #define OTPC_USER_ADDR_MASK GENMASK(31, 16) 25 #define OTPC_USE_USER BIT(0) 26 #define OTPC_USE_USER_MASK GENMASK(16, 16) 27 #define OTPC_USER_FSM_ENABLE BIT(0) 28 #define OTPC_USER_FSM_ENABLE_MASK GENMASK(16, 16) 29 #define OTPC_SBPI_DONE BIT(1) 30 #define OTPC_USER_DONE BIT(2) 31 32 #define SBPI_DAP_ADDR 0x02 33 #define SBPI_DAP_ADDR_SHIFT 8 34 #define SBPI_DAP_ADDR_MASK GENMASK(31, 24) 35 #define SBPI_CMD_VALID_MASK GENMASK(31, 16) 36 #define SBPI_DAP_CMD_WRF 0xC0 37 #define SBPI_DAP_REG_ECC 0x3A 38 #define SBPI_ECC_ENABLE 0x00 39 #define SBPI_ECC_DISABLE 0x09 40 #define SBPI_ENABLE BIT(0) 41 #define SBPI_ENABLE_MASK GENMASK(16, 16) 42 43 #define OTPC_TIMEOUT 10000 44 45 typedef int (*OTP_READ)(struct udevice *dev, int offset, void *buf, int size); 46 47 struct rockchip_otp_platdata { 48 void __iomem *base; 49 unsigned long secure_conf_base; 50 unsigned long otp_mask_base; 51 }; 52 53 #endif 54