1*baaa7dd7SNikita Kiryanov /* 2*baaa7dd7SNikita Kiryanov * pxa_lcd.h - PXA LCD Controller structures 3*baaa7dd7SNikita Kiryanov * 4*baaa7dd7SNikita Kiryanov * (C) Copyright 2001 5*baaa7dd7SNikita Kiryanov * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 6*baaa7dd7SNikita Kiryanov * 7*baaa7dd7SNikita Kiryanov * SPDX-License-Identifier: GPL-2.0+ 8*baaa7dd7SNikita Kiryanov */ 9*baaa7dd7SNikita Kiryanov 10*baaa7dd7SNikita Kiryanov #ifndef _PXA_LCD_H_ 11*baaa7dd7SNikita Kiryanov #define _PXA_LCD_H_ 12*baaa7dd7SNikita Kiryanov 13*baaa7dd7SNikita Kiryanov /* 14*baaa7dd7SNikita Kiryanov * PXA LCD DMA descriptor 15*baaa7dd7SNikita Kiryanov */ 16*baaa7dd7SNikita Kiryanov struct pxafb_dma_descriptor { 17*baaa7dd7SNikita Kiryanov u_long fdadr; /* Frame descriptor address register */ 18*baaa7dd7SNikita Kiryanov u_long fsadr; /* Frame source address register */ 19*baaa7dd7SNikita Kiryanov u_long fidr; /* Frame ID register */ 20*baaa7dd7SNikita Kiryanov u_long ldcmd; /* Command register */ 21*baaa7dd7SNikita Kiryanov }; 22*baaa7dd7SNikita Kiryanov 23*baaa7dd7SNikita Kiryanov /* 24*baaa7dd7SNikita Kiryanov * PXA LCD info 25*baaa7dd7SNikita Kiryanov */ 26*baaa7dd7SNikita Kiryanov struct pxafb_info { 27*baaa7dd7SNikita Kiryanov /* Misc registers */ 28*baaa7dd7SNikita Kiryanov u_long reg_lccr3; 29*baaa7dd7SNikita Kiryanov u_long reg_lccr2; 30*baaa7dd7SNikita Kiryanov u_long reg_lccr1; 31*baaa7dd7SNikita Kiryanov u_long reg_lccr0; 32*baaa7dd7SNikita Kiryanov u_long fdadr0; 33*baaa7dd7SNikita Kiryanov u_long fdadr1; 34*baaa7dd7SNikita Kiryanov 35*baaa7dd7SNikita Kiryanov /* DMA descriptors */ 36*baaa7dd7SNikita Kiryanov struct pxafb_dma_descriptor *dmadesc_fblow; 37*baaa7dd7SNikita Kiryanov struct pxafb_dma_descriptor *dmadesc_fbhigh; 38*baaa7dd7SNikita Kiryanov struct pxafb_dma_descriptor *dmadesc_palette; 39*baaa7dd7SNikita Kiryanov 40*baaa7dd7SNikita Kiryanov u_long screen; /* physical address of frame buffer */ 41*baaa7dd7SNikita Kiryanov u_long palette; /* physical address of palette memory */ 42*baaa7dd7SNikita Kiryanov u_int palette_size; 43*baaa7dd7SNikita Kiryanov }; 44*baaa7dd7SNikita Kiryanov 45*baaa7dd7SNikita Kiryanov /* 46*baaa7dd7SNikita Kiryanov * LCD controller stucture for PXA CPU 47*baaa7dd7SNikita Kiryanov */ 48*baaa7dd7SNikita Kiryanov typedef struct vidinfo { 49*baaa7dd7SNikita Kiryanov ushort vl_col; /* Number of columns (i.e. 640) */ 50*baaa7dd7SNikita Kiryanov ushort vl_row; /* Number of rows (i.e. 480) */ 51*baaa7dd7SNikita Kiryanov ushort vl_width; /* Width of display area in millimeters */ 52*baaa7dd7SNikita Kiryanov ushort vl_height; /* Height of display area in millimeters */ 53*baaa7dd7SNikita Kiryanov 54*baaa7dd7SNikita Kiryanov /* LCD configuration register */ 55*baaa7dd7SNikita Kiryanov u_char vl_clkp; /* Clock polarity */ 56*baaa7dd7SNikita Kiryanov u_char vl_oep; /* Output Enable polarity */ 57*baaa7dd7SNikita Kiryanov u_char vl_hsp; /* Horizontal Sync polarity */ 58*baaa7dd7SNikita Kiryanov u_char vl_vsp; /* Vertical Sync polarity */ 59*baaa7dd7SNikita Kiryanov u_char vl_dp; /* Data polarity */ 60*baaa7dd7SNikita Kiryanov u_char vl_bpix;/* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8, 4 = 16 */ 61*baaa7dd7SNikita Kiryanov u_char vl_lbw; /* LCD Bus width, 0 = 4, 1 = 8 */ 62*baaa7dd7SNikita Kiryanov u_char vl_splt;/* Split display, 0 = single-scan, 1 = dual-scan */ 63*baaa7dd7SNikita Kiryanov u_char vl_clor; /* Color, 0 = mono, 1 = color */ 64*baaa7dd7SNikita Kiryanov u_char vl_tft; /* 0 = passive, 1 = TFT */ 65*baaa7dd7SNikita Kiryanov 66*baaa7dd7SNikita Kiryanov /* Horizontal control register. Timing from data sheet */ 67*baaa7dd7SNikita Kiryanov ushort vl_hpw; /* Horz sync pulse width */ 68*baaa7dd7SNikita Kiryanov u_char vl_blw; /* Wait before of line */ 69*baaa7dd7SNikita Kiryanov u_char vl_elw; /* Wait end of line */ 70*baaa7dd7SNikita Kiryanov 71*baaa7dd7SNikita Kiryanov /* Vertical control register. */ 72*baaa7dd7SNikita Kiryanov u_char vl_vpw; /* Vertical sync pulse width */ 73*baaa7dd7SNikita Kiryanov u_char vl_bfw; /* Wait before of frame */ 74*baaa7dd7SNikita Kiryanov u_char vl_efw; /* Wait end of frame */ 75*baaa7dd7SNikita Kiryanov 76*baaa7dd7SNikita Kiryanov /* PXA LCD controller params */ 77*baaa7dd7SNikita Kiryanov struct pxafb_info pxa; 78*baaa7dd7SNikita Kiryanov } vidinfo_t; 79*baaa7dd7SNikita Kiryanov 80*baaa7dd7SNikita Kiryanov #endif 81