1*151b223bSSimon Glass /* 2*151b223bSSimon Glass * Copyright (c) 2015 Google, Inc 3*151b223bSSimon Glass * Written by Simon Glass <sjg@chromium.org> 4*151b223bSSimon Glass * 5*151b223bSSimon Glass * SPDX-License-Identifier: GPL-2.0+ 6*151b223bSSimon Glass */ 7*151b223bSSimon Glass 8*151b223bSSimon Glass #ifndef __TPS65090_PMIC_H_ 9*151b223bSSimon Glass #define __TPS65090_PMIC_H_ 10*151b223bSSimon Glass 11*151b223bSSimon Glass /* I2C device address for TPS65090 PMU */ 12*151b223bSSimon Glass #define TPS65090_I2C_ADDR 0x48 13*151b223bSSimon Glass 14*151b223bSSimon Glass /* TPS65090 register addresses */ 15*151b223bSSimon Glass enum { 16*151b223bSSimon Glass REG_IRQ1 = 0, 17*151b223bSSimon Glass REG_CG_CTRL0 = 4, 18*151b223bSSimon Glass REG_CG_STATUS1 = 0xa, 19*151b223bSSimon Glass REG_FET_BASE = 0xe, /* Not a real register, FETs count from here */ 20*151b223bSSimon Glass REG_FET1_CTRL, 21*151b223bSSimon Glass REG_FET2_CTRL, 22*151b223bSSimon Glass REG_FET3_CTRL, 23*151b223bSSimon Glass REG_FET4_CTRL, 24*151b223bSSimon Glass REG_FET5_CTRL, 25*151b223bSSimon Glass REG_FET6_CTRL, 26*151b223bSSimon Glass REG_FET7_CTRL, 27*151b223bSSimon Glass TPS65090_NUM_REGS, 28*151b223bSSimon Glass }; 29*151b223bSSimon Glass 30*151b223bSSimon Glass enum { 31*151b223bSSimon Glass IRQ1_VBATG = 1 << 3, 32*151b223bSSimon Glass CG_CTRL0_ENC_MASK = 0x01, 33*151b223bSSimon Glass 34*151b223bSSimon Glass MAX_FET_NUM = 7, 35*151b223bSSimon Glass MAX_CTRL_READ_TRIES = 5, 36*151b223bSSimon Glass 37*151b223bSSimon Glass /* TPS65090 FET_CTRL register values */ 38*151b223bSSimon Glass FET_CTRL_TOFET = 1 << 7, /* Timeout, startup, overload */ 39*151b223bSSimon Glass FET_CTRL_PGFET = 1 << 4, /* Power good for FET status */ 40*151b223bSSimon Glass FET_CTRL_WAIT = 3 << 2, /* Overcurrent timeout max */ 41*151b223bSSimon Glass FET_CTRL_ADENFET = 1 << 1, /* Enable output auto discharge */ 42*151b223bSSimon Glass FET_CTRL_ENFET = 1 << 0, /* Enable FET */ 43*151b223bSSimon Glass }; 44*151b223bSSimon Glass 45*151b223bSSimon Glass enum { 46*151b223bSSimon Glass /* Status register fields */ 47*151b223bSSimon Glass TPS65090_ST1_OTC = 1 << 0, 48*151b223bSSimon Glass TPS65090_ST1_OCC = 1 << 1, 49*151b223bSSimon Glass TPS65090_ST1_STATE_SHIFT = 4, 50*151b223bSSimon Glass TPS65090_ST1_STATE_MASK = 0xf << TPS65090_ST1_STATE_SHIFT, 51*151b223bSSimon Glass }; 52*151b223bSSimon Glass 53*151b223bSSimon Glass /* Drivers name */ 54*151b223bSSimon Glass #define TPS65090_FET_DRIVER "tps65090_fet" 55*151b223bSSimon Glass 56*151b223bSSimon Glass #endif /* __TPS65090_PMIC_H_ */ 57