1 /* 2 * Copyright (C) 2015 Google, Inc 3 * Written by Simon Glass <sjg@chromium.org> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #ifndef _PMIC_RK8XX_H_ 9 #define _PMIC_RK8XX_H_ 10 11 enum { 12 REG_SECONDS = 0x00, 13 REG_MINUTES, 14 REG_HOURS, 15 REG_DAYS, 16 REG_MONTHS, 17 REG_YEARS, 18 REG_WEEKS, 19 REG_ALARM_SECONDS, 20 REG_ALARM_MINUTES, 21 REG_ALARM_HOURS, 22 REG_ALARM_DAYS, 23 REG_ALARM_MONTHS, 24 REG_ALARM_YEARS, 25 26 REG_RTC_CTRL = 0x10, 27 REG_RTC_STATUS, 28 REG_RTC_INT, 29 REG_RTC_COMP_LSB, 30 REG_RTC_COMP_MSB, 31 32 ID_MSB = 0x17, 33 ID_LSB, 34 35 REG_CLK32OUT = 0x20, 36 REG_VB_MON, 37 REG_THERMAL, 38 REG_DCDC_EN, 39 REG_LDO_EN, 40 REG_SLEEP_SET_OFF1, 41 REG_SLEEP_SET_OFF2, 42 REG_DCDC_UV_STS, 43 REG_DCDC_UV_ACT, 44 REG_LDO_UV_STS, 45 REG_LDO_UV_ACT, 46 REG_DCDC_PG, 47 REG_LDO_PG, 48 REG_VOUT_MON_TDB, 49 REG_BUCK1_CONFIG, 50 REG_BUCK1_ON_VSEL, 51 REG_BUCK1_SLP_VSEL, 52 REG_BUCK1_DVS_VSEL, 53 REG_BUCK2_CONFIG, 54 REG_BUCK2_ON_VSEL, 55 REG_BUCK2_SLP_VSEL, 56 REG_BUCK2_DVS_VSEL, 57 REG_BUCK3_CONFIG, 58 REG_BUCK4_CONFIG, 59 REG_BUCK4_ON_VSEL, 60 REG_BUCK4_SLP_VSEL, 61 REG_BOOST_CONFIG_REG, 62 REG_LDO1_ON_VSEL, 63 REG_LDO1_SLP_VSEL, 64 REG_LDO2_ON_VSEL, 65 REG_LDO2_SLP_VSEL, 66 REG_LDO3_ON_VSEL, 67 REG_LDO3_SLP_VSEL, 68 REG_LDO4_ON_VSEL, 69 REG_LDO4_SLP_VSEL, 70 REG_LDO5_ON_VSEL, 71 REG_LDO5_SLP_VSEL, 72 REG_LDO6_ON_VSEL, 73 REG_LDO6_SLP_VSEL, 74 REG_LDO7_ON_VSEL, 75 REG_LDO7_SLP_VSEL, 76 REG_LDO8_ON_VSEL, 77 REG_LDO8_SLP_VSEL, 78 REG_DEVCTRL, 79 REG_INT_STS1, 80 REG_INT_STS_MSK1, 81 REG_INT_STS2, 82 REG_INT_STS_MSK2, 83 REG_IO_POL, 84 REG_OTP_VDD_EN, 85 REG_H5V_EN, 86 REG_SLEEP_SET_OFF, 87 REG_BOOST_LDO9_ON_VSEL, 88 REG_BOOST_LDO9_SLP_VSEL, 89 REG_BOOST_CTRL, 90 91 /* Not sure what this does */ 92 REG_DCDC_ILMAX = 0x90, 93 REG_CHRG_COMP = 0x9a, 94 REG_SUP_STS = 0xa0, 95 REG_USB_CTRL, 96 REG1_CHRG_CTRL, 97 REG2_CHRG_CTRL, 98 REG3_CHRG_CTRL, 99 REG_BAT_CTRL, 100 REG_BAT_HTS_TS1, 101 REG_BAT_LTS_TS1, 102 REG_BAT_HTS_TS2, 103 REG_BAT_LTS_TS2, 104 REG_TS_CTRL, 105 REG_ADC_CTRL, 106 REG_ON_SOURCE, 107 REG_OFF_SOURCE, 108 REG_GGCON, 109 REG_GGSTS, 110 REG_FRAME_SMP_INTERV, 111 REG_AUTO_SLP_CUR_THR, 112 REG3_GASCNT_CAL, 113 REG2_GASCNT_CAL, 114 REG1_GASCNT_CAL, 115 REG0_GASCNT_CAL, 116 REG3_GASCNT, 117 REG2_GASCNT, 118 REG1_GASCNT, 119 REG0_GASCNT, 120 REGH_BAT_CUR_AVG, 121 REGL_BAT_CUR_AVG, 122 REGH_TS1_ADC, 123 REGL_TS1_ADC, 124 REGH_TS2_ADC, 125 REGL_TS2_ADC, 126 REGH_BAT_OCV, 127 REGL_BAT_OCV, 128 REGH_BAT_VOL, 129 REGL_BAT_VOL, 130 REGH_RELAX_ENTRY_THRES, 131 REGL_RELAX_ENTRY_THRES, 132 REGH_RELAX_EXIT_THRES, 133 REGL_RELAX_EXIT_THRES, 134 REGH_RELAX_VOL1, 135 REGL_RELAX_VOL1, 136 REGH_RELAX_VOL2, 137 REGL_RELAX_VOL2, 138 REGH_BAT_CUR_R_CALC, 139 REGL_BAT_CUR_R_CALC, 140 REGH_BAT_VOL_R_CALC, 141 REGL_BAT_VOL_R_CALC, 142 REGH_CAL_OFFSET, 143 REGL_CAL_OFFSET, 144 REG_NON_ACT_TIMER_CNT, 145 REGH_VCALIB0, 146 REGL_VCALIB0, 147 REGH_VCALIB1, 148 REGL_VCALIB1, 149 REGH_IOFFSET, 150 REGL_IOFFSET, 151 REG_SOC, 152 REG3_REMAIN_CAP, 153 REG2_REMAIN_CAP, 154 REG1_REMAIN_CAP, 155 REG0_REMAIN_CAP, 156 REG_UPDAT_LEVE, 157 REG3_NEW_FCC, 158 REG2_NEW_FCC, 159 REG1_NEW_FCC, 160 REG0_NEW_FCC, 161 REG_NON_ACT_TIMER_CNT_SAVE, 162 REG_OCV_VOL_VALID, 163 REG_REBOOT_CNT, 164 REG_POFFSET, 165 REG_MISC_MARK, 166 REG_HALT_CNT, 167 REGH_CALC_REST, 168 REGL_CALC_REST, 169 SAVE_DATA19, 170 RK808_NUM_OF_REGS, 171 }; 172 173 enum { 174 RK817_REG_SYS_CFG3 = 0xf4, 175 }; 176 177 enum { 178 RK816_REG_DCDC_EN1 = 0x23, 179 RK816_REG_DCDC_EN2, 180 RK816_REG_DCDC_SLP_EN, 181 RK816_REG_LDO_SLP_EN, 182 RK816_REG_LDO_EN1 = 0x27, 183 RK816_REG_LDO_EN2, 184 }; 185 186 enum { 187 RK805_ID = 0x8050, 188 RK806_ID = 0x8060, 189 RK808_ID = 0x0000, 190 RK809_ID = 0x8090, 191 RK816_ID = 0x8160, 192 RK817_ID = 0x8170, 193 RK818_ID = 0x8180, 194 }; 195 196 enum { 197 RK817_POWER_EN0 = 0xb1, 198 RK817_POWER_EN1, 199 RK817_POWER_EN2, 200 RK817_POWER_EN3, 201 }; 202 #define RK817_POWER_EN_SAVE0 0x99 203 #define RK817_POWER_EN_SAVE1 0xa4 204 205 #define RK817_ID_MSB 0xed 206 #define RK817_ID_LSB 0xee 207 #define RK8XX_ID_MSK 0xfff0 208 209 #define RK817_PMIC_CHRG_TERM 0xe6 210 #define RK817_PMIC_SYS_CFG1 0xf1 211 #define RK817_PMIC_SYS_CFG3 0xf4 212 #define RK817_GPIO_INT_CFG 0xfe 213 214 #define RK8XX_ON_SOURCE 0xae 215 #define RK8XX_OFF_SOURCE 0xaf 216 #define RK817_BUCK4_CMIN 0xc6 217 #define RK817_ON_SOURCE 0xf5 218 #define RK817_OFF_SOURCE 0xf6 219 #define RK817_NUM_OF_REGS 0xff 220 221 #define RK8XX_DEVCTRL_REG 0x4b 222 #define RK817_PWRON_KEY 0xf7 223 #define RK8XX_LP_ACTION_MSK BIT(6) 224 #define RK8XX_LP_OFF (0 << 6) 225 #define RK8XX_LP_RESTART (1 << 6) 226 #define RK8XX_LP_OFF_MSK BIT(4) | BIT(5) 227 #define RK8XX_LP_TIME_6S (0 << 4) 228 #define RK8XX_LP_TIME_8S (1 << 4) 229 #define RK8XX_LP_TIME_10S (2 << 4) 230 #define RK8XX_LP_TIME_12S (3 << 4) 231 232 /* IRQ definitions */ 233 #define RK8XX_IRQ_PWRON_FALL 0 234 #define RK8XX_IRQ_PWRON_RISE 1 235 #define RK8XX_IRQ_PLUG_OUT 2 236 #define RK8XX_IRQ_PLUG_IN 3 237 #define RK8XX_IRQ_CHG_OK 4 238 239 #define RK808_INT_STS_REG1 0x4c 240 #define RK808_INT_MSK_REG1 0x4d 241 #define RK808_IRQ_PLUG_OUT_MSK BIT(1) 242 243 #define RK805_INT_STS_REG 0x4c 244 #define RK805_INT_MSK_REG 0x4d 245 #define RK805_IRQ_PWRON_FALL_MSK BIT(7) 246 #define RK805_IRQ_PWRON_RISE_MSK BIT(0) 247 248 #define RK806_CHIP_NAME 0x5A 249 #define RK806_CHIP_VER 0x5B 250 #define RK806_HW_VER 0x21 251 #define HW_DUAL_PMIC 0x28 252 #define HW_SINGLE_PMIC 0xe8 253 254 #define RK806_CMD_READ 0 255 #define RK806_CMD_WRITE BIT(7) 256 #define RK806_CMD_CRC_EN BIT(6) 257 #define RK806_CMD_CRC_DIS 0 258 #define RK806_CMD_LEN_MSK 0x0f 259 #define RK806_REG_H 0x00 260 261 #define RK806_SYS_CFG1 0x5f 262 #define RK806_PWRCTRL_CONFIG0 0x62 263 #define RK806_PWRCTRL_CONFIG1 0x63 264 #define RK806_VSEL_CTR_SEL0 0x64 265 #define RK806_DVS_CTR_SEL4 0x6e 266 #define RK806_SYS_CFG3 0x72 267 #define RK806_PWRON_KEY 0x76 268 #define RK806_INT_STS0 0x77 269 #define RK806_INT_MSK0 0x78 270 #define RK806_INT_STS1 0x79 271 #define RK806_INT_MSK1 0x7A 272 #define RK806_GPIO_INT_CONFIG 0x7B 273 #define RK806_ON_SOURCE 0x74 274 #define RK806_OFF_SOURCE 0x75 275 #define RK806_BUCK_RSERVE_REG3 0xfd 276 277 #define RK806_INT_POL_HIGH BIT(1) 278 #define RK806_IRQ_PWRON_FALL_MSK BIT(0) 279 #define RK806_IRQ_PWRON_RISE_MSK BIT(1) 280 #define RK806_DEV_OFF BIT(0) 281 #define RK806_RST_MODE1 0x01 282 #define RK806_RST_MODE2 0x02 283 #define RK806_PWRCTRL_FUN_MSK 0x88 284 #define RK806_VSEL_CTRL_MSK 0xcc 285 #define RK806_VSEL_PWRCTRL1 0x11 286 #define RK806_ENABLE_PWRCTRL 0x04 287 #define RK806_VERSION_AB 0x01 288 289 #define RK806_ABNORDET_EN 0x80 290 #define RK806_VERSION_MSK 0x0f 291 #define RK806_RESET_FUN_CLR 0x3f 292 #define RK806_BUCK5_EX_RES_EN 0x10 293 294 /* RK806 buck*/ 295 #define RK806_BUCK_ON_VSEL(n) (0x1a + n - 1) 296 #define RK806_BUCK_SLP_VSEL(n) (0x24 + n - 1) 297 #define RK806_BUCK_CONFIG(n) (0x10 + n - 1) 298 #define RK806_BUCK_VSEL_MASK 0xff 299 300 /* RK806 LDO */ 301 #define RK806_NLDO_ON_VSEL(n) (0x43 + n - 1) 302 #define RK806_NLDO_SLP_VSEL(n) (0x48 + n - 1) 303 #define RK806_NLDO_VSEL_MASK 0xff 304 #define RK806_PLDO_ON_VSEL(n) (0x4e + n - 1) 305 #define RK806_PLDO_SLP_VSEL(n) (0x54 + n - 1) 306 #define RK806_PLDO_VSEL_MASK 0xff 307 308 /* RK806 ENABLE */ 309 #define RK806_POWER_EN(n) (0x00 + n) 310 #define RK806_NLDO_EN(n) (0x03 + n) 311 #define RK806_PLDO_EN(n) (0x04 + n) 312 313 #define RK806_BUCK_SUSPEND_EN 0x06 314 #define RK806_NLDO_SUSPEND_EN 0x07 315 #define RK806_PLDO_SUSPEND_EN 0x08 316 317 #define RK806_RAMP_RATE_MASK1 0xc0 318 #define RK806_RAMP_RATE_REG1(n) (0x10 + n) 319 #define RK806_RAMP_RATE_REG1_8 0xeb 320 #define RK806_RAMP_RATE_REG9_10 0xea 321 322 #define RK806_RAMP_RATE_4LSB_PER_1CLK 0x00/* LDO 100mV/uS buck 50mV/us */ 323 #define RK806_RAMP_RATE_2LSB_PER_1CLK 0x01/* LDO 50mV/uS buck 25mV/us */ 324 #define RK806_RAMP_RATE_1LSB_PER_1CLK 0x02/* LDO 25mV/uS buck 12.5mV/us */ 325 #define RK806_RAMP_RATE_1LSB_PER_2CLK 0x03/* LDO 12.5mV/uS buck 6.25mV/us */ 326 327 #define RK806_RAMP_RATE_1LSB_PER_4CLK 0x04/* LDO 6.28/2mV/uS buck 3.125mV/us */ 328 #define RK806_RAMP_RATE_1LSB_PER_8CLK 0x05/* LDO 3.12mV/uS buck 1.56mV/us */ 329 #define RK806_RAMP_RATE_1LSB_PER_13CLK 0x06/* LDO 1.9mV/uS buck 961mV/us */ 330 #define RK806_RAMP_RATE_1LSB_PER_32CLK 0x07/* LDO 0.78mV/uS buck 0.39mV/us */ 331 332 #define RK806_PLDO0_2_MSK(pldo) (BIT(pldo + 5)) 333 #define RK806_PLDO0_2_SET(pldo) (BIT(pldo + 1) | RK806_PLDO0_2_MSK(pldo)) 334 #define RK806_PLDO0_2_CLR(pldo) RK806_PLDO0_2_MSK(pldo) 335 336 #define RK816_INT_STS_REG1 0x49 337 #define RK816_INT_MSK_REG1 0x4a 338 #define RK816_INT_STS_REG3 0x4e 339 #define RK816_INT_STS_MSK_REG3 0x4f 340 #define RK816_IRQ_PWRON_RISE_MSK BIT(6) 341 #define RK816_IRQ_PWRON_FALL_MSK BIT(5) 342 #define RK816_IRQ_PLUG_OUT_MSK BIT(1) 343 #define RK816_IRQ_CHR_OK_MSK BIT(2) 344 345 #define RK818_INT_STS_REG1 0x4c 346 #define RK818_INT_MSK_REG1 0x4d 347 #define RK818_IRQ_PLUG_OUT_MSK BIT(1) 348 #define RK818_IRQ_CHR_OK_MSK BIT(2) 349 350 #define RK817_INT_STS_REG0 0xf8 351 #define RK817_INT_MSK_REG0 0xf9 352 #define RK817_IRQ_PWRON_FALL_MSK BIT(0) 353 #define RK817_IRQ_PWRON_RISE_MSK BIT(1) 354 #define RK817_IRQ_PLUG_OUT_MSK BIT(1) 355 #define RK817_IRQ_PLUG_IN_MSK BIT(0) 356 357 struct reg_data { 358 u8 reg; 359 u8 val; 360 u8 mask; 361 }; 362 363 struct rk8xx_reg_table { 364 char *name; 365 u8 reg_ctl; 366 u8 reg_vol; 367 }; 368 369 struct rk8xx_priv { 370 struct virq_chip *irq_chip; 371 struct spi_slave *slave; 372 int variant; 373 int irq; 374 int lp_off_time; 375 int lp_action; 376 uint8_t sleep_pin; 377 uint8_t rst_fun; 378 int not_save_power_en; 379 int sys_can_sd; 380 int buck5_feedback_dis; 381 }; 382 383 int rk8xx_spl_configure_buck(struct udevice *pmic, int buck, int uvolt); 384 int rk818_spl_configure_usb_input_current(struct udevice *pmic, int current_ma); 385 int rk818_spl_configure_usb_chrg_shutdown(struct udevice *pmic, int uvolt); 386 387 #endif 388