1453c5a92SJacob Chen /* 2453c5a92SJacob Chen * Copyright (C) 2015 Google, Inc 3453c5a92SJacob Chen * Written by Simon Glass <sjg@chromium.org> 4453c5a92SJacob Chen * 5453c5a92SJacob Chen * SPDX-License-Identifier: GPL-2.0+ 6453c5a92SJacob Chen */ 7453c5a92SJacob Chen 8453c5a92SJacob Chen #ifndef _PMIC_RK8XX_H_ 9453c5a92SJacob Chen #define _PMIC_RK8XX_H_ 10453c5a92SJacob Chen 11453c5a92SJacob Chen enum { 12453c5a92SJacob Chen REG_SECONDS = 0x00, 13453c5a92SJacob Chen REG_MINUTES, 14453c5a92SJacob Chen REG_HOURS, 15453c5a92SJacob Chen REG_DAYS, 16453c5a92SJacob Chen REG_MONTHS, 17453c5a92SJacob Chen REG_YEARS, 18453c5a92SJacob Chen REG_WEEKS, 19453c5a92SJacob Chen REG_ALARM_SECONDS, 20453c5a92SJacob Chen REG_ALARM_MINUTES, 21453c5a92SJacob Chen REG_ALARM_HOURS, 22453c5a92SJacob Chen REG_ALARM_DAYS, 23453c5a92SJacob Chen REG_ALARM_MONTHS, 24453c5a92SJacob Chen REG_ALARM_YEARS, 25453c5a92SJacob Chen 26453c5a92SJacob Chen REG_RTC_CTRL = 0x10, 27453c5a92SJacob Chen REG_RTC_STATUS, 28453c5a92SJacob Chen REG_RTC_INT, 29453c5a92SJacob Chen REG_RTC_COMP_LSB, 30453c5a92SJacob Chen REG_RTC_COMP_MSB, 31453c5a92SJacob Chen 32453c5a92SJacob Chen ID_MSB = 0x17, 33453c5a92SJacob Chen ID_LSB, 34453c5a92SJacob Chen 35453c5a92SJacob Chen REG_CLK32OUT = 0x20, 36453c5a92SJacob Chen REG_VB_MON, 37453c5a92SJacob Chen REG_THERMAL, 38453c5a92SJacob Chen REG_DCDC_EN, 39453c5a92SJacob Chen REG_LDO_EN, 40453c5a92SJacob Chen REG_SLEEP_SET_OFF1, 41453c5a92SJacob Chen REG_SLEEP_SET_OFF2, 42453c5a92SJacob Chen REG_DCDC_UV_STS, 43453c5a92SJacob Chen REG_DCDC_UV_ACT, 44453c5a92SJacob Chen REG_LDO_UV_STS, 45453c5a92SJacob Chen REG_LDO_UV_ACT, 46453c5a92SJacob Chen REG_DCDC_PG, 47453c5a92SJacob Chen REG_LDO_PG, 48453c5a92SJacob Chen REG_VOUT_MON_TDB, 49453c5a92SJacob Chen REG_BUCK1_CONFIG, 50453c5a92SJacob Chen REG_BUCK1_ON_VSEL, 51453c5a92SJacob Chen REG_BUCK1_SLP_VSEL, 52453c5a92SJacob Chen REG_BUCK1_DVS_VSEL, 53453c5a92SJacob Chen REG_BUCK2_CONFIG, 54453c5a92SJacob Chen REG_BUCK2_ON_VSEL, 55453c5a92SJacob Chen REG_BUCK2_SLP_VSEL, 56453c5a92SJacob Chen REG_BUCK2_DVS_VSEL, 57453c5a92SJacob Chen REG_BUCK3_CONFIG, 58453c5a92SJacob Chen REG_BUCK4_CONFIG, 59453c5a92SJacob Chen REG_BUCK4_ON_VSEL, 60453c5a92SJacob Chen REG_BUCK4_SLP_VSEL, 61453c5a92SJacob Chen REG_BOOST_CONFIG_REG, 62453c5a92SJacob Chen REG_LDO1_ON_VSEL, 63453c5a92SJacob Chen REG_LDO1_SLP_VSEL, 64453c5a92SJacob Chen REG_LDO2_ON_VSEL, 65453c5a92SJacob Chen REG_LDO2_SLP_VSEL, 66453c5a92SJacob Chen REG_LDO3_ON_VSEL, 67453c5a92SJacob Chen REG_LDO3_SLP_VSEL, 68453c5a92SJacob Chen REG_LDO4_ON_VSEL, 69453c5a92SJacob Chen REG_LDO4_SLP_VSEL, 70453c5a92SJacob Chen REG_LDO5_ON_VSEL, 71453c5a92SJacob Chen REG_LDO5_SLP_VSEL, 72453c5a92SJacob Chen REG_LDO6_ON_VSEL, 73453c5a92SJacob Chen REG_LDO6_SLP_VSEL, 74453c5a92SJacob Chen REG_LDO7_ON_VSEL, 75453c5a92SJacob Chen REG_LDO7_SLP_VSEL, 76453c5a92SJacob Chen REG_LDO8_ON_VSEL, 77453c5a92SJacob Chen REG_LDO8_SLP_VSEL, 78453c5a92SJacob Chen REG_DEVCTRL, 79453c5a92SJacob Chen REG_INT_STS1, 80453c5a92SJacob Chen REG_INT_STS_MSK1, 81453c5a92SJacob Chen REG_INT_STS2, 82453c5a92SJacob Chen REG_INT_STS_MSK2, 83453c5a92SJacob Chen REG_IO_POL, 84453c5a92SJacob Chen REG_OTP_VDD_EN, 85453c5a92SJacob Chen REG_H5V_EN, 86453c5a92SJacob Chen REG_SLEEP_SET_OFF, 87453c5a92SJacob Chen REG_BOOST_LDO9_ON_VSEL, 88453c5a92SJacob Chen REG_BOOST_LDO9_SLP_VSEL, 89453c5a92SJacob Chen REG_BOOST_CTRL, 90453c5a92SJacob Chen 91453c5a92SJacob Chen /* Not sure what this does */ 92453c5a92SJacob Chen REG_DCDC_ILMAX = 0x90, 93453c5a92SJacob Chen REG_CHRG_COMP = 0x9a, 94453c5a92SJacob Chen REG_SUP_STS = 0xa0, 95453c5a92SJacob Chen REG_USB_CTRL, 96453c5a92SJacob Chen REG1_CHRG_CTRL, 97453c5a92SJacob Chen REG2_CHRG_CTRL, 98453c5a92SJacob Chen REG3_CHRG_CTRL, 99453c5a92SJacob Chen REG_BAT_CTRL, 100453c5a92SJacob Chen REG_BAT_HTS_TS1, 101453c5a92SJacob Chen REG_BAT_LTS_TS1, 102453c5a92SJacob Chen REG_BAT_HTS_TS2, 103453c5a92SJacob Chen REG_BAT_LTS_TS2, 104453c5a92SJacob Chen REG_TS_CTRL, 105453c5a92SJacob Chen REG_ADC_CTRL, 106453c5a92SJacob Chen REG_ON_SOURCE, 107453c5a92SJacob Chen REG_OFF_SOURCE, 108453c5a92SJacob Chen REG_GGCON, 109453c5a92SJacob Chen REG_GGSTS, 110453c5a92SJacob Chen REG_FRAME_SMP_INTERV, 111453c5a92SJacob Chen REG_AUTO_SLP_CUR_THR, 112453c5a92SJacob Chen REG3_GASCNT_CAL, 113453c5a92SJacob Chen REG2_GASCNT_CAL, 114453c5a92SJacob Chen REG1_GASCNT_CAL, 115453c5a92SJacob Chen REG0_GASCNT_CAL, 116453c5a92SJacob Chen REG3_GASCNT, 117453c5a92SJacob Chen REG2_GASCNT, 118453c5a92SJacob Chen REG1_GASCNT, 119453c5a92SJacob Chen REG0_GASCNT, 120453c5a92SJacob Chen REGH_BAT_CUR_AVG, 121453c5a92SJacob Chen REGL_BAT_CUR_AVG, 122453c5a92SJacob Chen REGH_TS1_ADC, 123453c5a92SJacob Chen REGL_TS1_ADC, 124453c5a92SJacob Chen REGH_TS2_ADC, 125453c5a92SJacob Chen REGL_TS2_ADC, 126453c5a92SJacob Chen REGH_BAT_OCV, 127453c5a92SJacob Chen REGL_BAT_OCV, 128453c5a92SJacob Chen REGH_BAT_VOL, 129453c5a92SJacob Chen REGL_BAT_VOL, 130453c5a92SJacob Chen REGH_RELAX_ENTRY_THRES, 131453c5a92SJacob Chen REGL_RELAX_ENTRY_THRES, 132453c5a92SJacob Chen REGH_RELAX_EXIT_THRES, 133453c5a92SJacob Chen REGL_RELAX_EXIT_THRES, 134453c5a92SJacob Chen REGH_RELAX_VOL1, 135453c5a92SJacob Chen REGL_RELAX_VOL1, 136453c5a92SJacob Chen REGH_RELAX_VOL2, 137453c5a92SJacob Chen REGL_RELAX_VOL2, 138453c5a92SJacob Chen REGH_BAT_CUR_R_CALC, 139453c5a92SJacob Chen REGL_BAT_CUR_R_CALC, 140453c5a92SJacob Chen REGH_BAT_VOL_R_CALC, 141453c5a92SJacob Chen REGL_BAT_VOL_R_CALC, 142453c5a92SJacob Chen REGH_CAL_OFFSET, 143453c5a92SJacob Chen REGL_CAL_OFFSET, 144453c5a92SJacob Chen REG_NON_ACT_TIMER_CNT, 145453c5a92SJacob Chen REGH_VCALIB0, 146453c5a92SJacob Chen REGL_VCALIB0, 147453c5a92SJacob Chen REGH_VCALIB1, 148453c5a92SJacob Chen REGL_VCALIB1, 149453c5a92SJacob Chen REGH_IOFFSET, 150453c5a92SJacob Chen REGL_IOFFSET, 151453c5a92SJacob Chen REG_SOC, 152453c5a92SJacob Chen REG3_REMAIN_CAP, 153453c5a92SJacob Chen REG2_REMAIN_CAP, 154453c5a92SJacob Chen REG1_REMAIN_CAP, 155453c5a92SJacob Chen REG0_REMAIN_CAP, 156453c5a92SJacob Chen REG_UPDAT_LEVE, 157453c5a92SJacob Chen REG3_NEW_FCC, 158453c5a92SJacob Chen REG2_NEW_FCC, 159453c5a92SJacob Chen REG1_NEW_FCC, 160453c5a92SJacob Chen REG0_NEW_FCC, 161453c5a92SJacob Chen REG_NON_ACT_TIMER_CNT_SAVE, 162453c5a92SJacob Chen REG_OCV_VOL_VALID, 163453c5a92SJacob Chen REG_REBOOT_CNT, 164453c5a92SJacob Chen REG_POFFSET, 165453c5a92SJacob Chen REG_MISC_MARK, 166453c5a92SJacob Chen REG_HALT_CNT, 167453c5a92SJacob Chen REGH_CALC_REST, 168453c5a92SJacob Chen REGL_CALC_REST, 169453c5a92SJacob Chen SAVE_DATA19, 170453c5a92SJacob Chen RK808_NUM_OF_REGS, 171453c5a92SJacob Chen }; 172453c5a92SJacob Chen 173453c5a92SJacob Chen enum { 1745e1bceeaSElaine Zhang RK816_REG_DCDC_EN1 = 0x23, 1755e1bceeaSElaine Zhang RK816_REG_DCDC_EN2, 1765e1bceeaSElaine Zhang RK816_REG_LDO_EN1 = 0x27, 1775e1bceeaSElaine Zhang RK816_REG_LDO_EN2, 1785e1bceeaSElaine Zhang }; 1795e1bceeaSElaine Zhang 1805e1bceeaSElaine Zhang enum { 181*4b6f5dc9SElaine Zhang RK805_ID = 0x8050, 182453c5a92SJacob Chen RK808_ID = 0x0000, 1835e1bceeaSElaine Zhang RK816_ID = 0x8160, 184453c5a92SJacob Chen RK818_ID = 0x8180, 185453c5a92SJacob Chen }; 186453c5a92SJacob Chen 187453c5a92SJacob Chen #define RK8XX_ID_MSK 0xfff0 188453c5a92SJacob Chen 189453c5a92SJacob Chen struct rk8xx_reg_table { 190453c5a92SJacob Chen char *name; 191453c5a92SJacob Chen u8 reg_ctl; 192453c5a92SJacob Chen u8 reg_vol; 193453c5a92SJacob Chen }; 194453c5a92SJacob Chen 195453c5a92SJacob Chen struct rk8xx_priv { 196453c5a92SJacob Chen int variant; 197453c5a92SJacob Chen }; 198453c5a92SJacob Chen 199453c5a92SJacob Chen int rk8xx_spl_configure_buck(struct udevice *pmic, int buck, int uvolt); 200ad98f882SWadim Egorov int rk818_spl_configure_usb_input_current(struct udevice *pmic, int current_ma); 201ad98f882SWadim Egorov int rk818_spl_configure_usb_chrg_shutdown(struct udevice *pmic, int uvolt); 202453c5a92SJacob Chen 203453c5a92SJacob Chen #endif 204