xref: /rk3399_rockchip-uboot/include/power/max77686_pmic.h (revision 857765e9aaeb9b80ae29e4d4e4916979d07040ba) 
1*857765e9SRajeshwari Shinde /*
2*857765e9SRajeshwari Shinde  *  Copyright (C) 2012 Samsung Electronics
3*857765e9SRajeshwari Shinde  *  Rajeshwari Shinde <rajeshwari.s@samsung.com>
4*857765e9SRajeshwari Shinde  *
5*857765e9SRajeshwari Shinde  * See file CREDITS for list of people who contributed to this
6*857765e9SRajeshwari Shinde  * project.
7*857765e9SRajeshwari Shinde  *
8*857765e9SRajeshwari Shinde  * This program is free software; you can redistribute it and/or
9*857765e9SRajeshwari Shinde  * modify it under the terms of the GNU General Public License as
10*857765e9SRajeshwari Shinde  * published by the Free Software Foundation; either version 2 of
11*857765e9SRajeshwari Shinde  * the License, or (at your option) any later version.
12*857765e9SRajeshwari Shinde  *
13*857765e9SRajeshwari Shinde  * This program is distributed in the hope that it will be useful,
14*857765e9SRajeshwari Shinde  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15*857765e9SRajeshwari Shinde  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16*857765e9SRajeshwari Shinde  * GNU General Public License for more details.
17*857765e9SRajeshwari Shinde  *
18*857765e9SRajeshwari Shinde  * You should have received a copy of the GNU General Public License
19*857765e9SRajeshwari Shinde  * along with this program; if not, write to the Free Software
20*857765e9SRajeshwari Shinde  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21*857765e9SRajeshwari Shinde  * MA 02111-1307 USA
22*857765e9SRajeshwari Shinde  */
23*857765e9SRajeshwari Shinde 
24*857765e9SRajeshwari Shinde #ifndef __MAX77686_H_
25*857765e9SRajeshwari Shinde #define __MAX77686_H_
26*857765e9SRajeshwari Shinde 
27*857765e9SRajeshwari Shinde enum {
28*857765e9SRajeshwari Shinde 	MAX77686_REG_PMIC_ID		= 0x0,
29*857765e9SRajeshwari Shinde 	MAX77686_REG_PMIC_INTSRC,
30*857765e9SRajeshwari Shinde 	MAX77686_REG_PMIC_INT1,
31*857765e9SRajeshwari Shinde 	MAX77686_REG_PMIC_INT2,
32*857765e9SRajeshwari Shinde 	MAX77686_REG_PMIC_INT1MSK,
33*857765e9SRajeshwari Shinde 	MAX77686_REG_PMIC_INT2MSK,
34*857765e9SRajeshwari Shinde 
35*857765e9SRajeshwari Shinde 	MAX77686_REG_PMIC_STATUS1,
36*857765e9SRajeshwari Shinde 	MAX77686_REG_PMIC_STATUS2,
37*857765e9SRajeshwari Shinde 
38*857765e9SRajeshwari Shinde 	MAX77686_REG_PMIC_PWRON,
39*857765e9SRajeshwari Shinde 	MAX77686_REG_PMIC_ONOFFDELAY,
40*857765e9SRajeshwari Shinde 	MAX77686_REG_PMIC_MRSTB,
41*857765e9SRajeshwari Shinde 
42*857765e9SRajeshwari Shinde 	MAX77686_REG_PMIC_BUCK1CRTL	= 0x10,
43*857765e9SRajeshwari Shinde 	MAX77686_REG_PMIC_BUCK1OUT,
44*857765e9SRajeshwari Shinde 	MAX77686_REG_PMIC_BUCK2CTRL1,
45*857765e9SRajeshwari Shinde 	MAX77686_REG_PMIC_BUCK234FREQ,
46*857765e9SRajeshwari Shinde 	MAX77686_REG_PMIC_BUCK2DVS1,
47*857765e9SRajeshwari Shinde 	MAX77686_REG_PMIC_BUCK2DVS2,
48*857765e9SRajeshwari Shinde 	MAX77686_REG_PMIC_BUCK2DVS3,
49*857765e9SRajeshwari Shinde 	MAX77686_REG_PMIC_BUCK2DVS4,
50*857765e9SRajeshwari Shinde 	MAX77686_REG_PMIC_BUCK2DVS5,
51*857765e9SRajeshwari Shinde 	MAX77686_REG_PMIC_BUCK2DVS6,
52*857765e9SRajeshwari Shinde 	MAX77686_REG_PMIC_BUCK2DVS7,
53*857765e9SRajeshwari Shinde 	MAX77686_REG_PMIC_BUCK2DVS8,
54*857765e9SRajeshwari Shinde 	MAX77686_REG_PMIC_BUCK3CTRL,
55*857765e9SRajeshwari Shinde 	MAX77686_REG_PMIC_BUCK3DVS1,
56*857765e9SRajeshwari Shinde 	MAX77686_REG_PMIC_BUCK3DVS2,
57*857765e9SRajeshwari Shinde 	MAX77686_REG_PMIC_BUCK3DVS3,
58*857765e9SRajeshwari Shinde 	MAX77686_REG_PMIC_BUCK3DVS4,
59*857765e9SRajeshwari Shinde 	MAX77686_REG_PMIC_BUCK3DVS5,
60*857765e9SRajeshwari Shinde 	MAX77686_REG_PMIC_BUCK3DVS6,
61*857765e9SRajeshwari Shinde 	MAX77686_REG_PMIC_BUCK3DVS7,
62*857765e9SRajeshwari Shinde 	MAX77686_REG_PMIC_BUCK3DVS8,
63*857765e9SRajeshwari Shinde 	MAX77686_REG_PMIC_BUCK4CTRL1,
64*857765e9SRajeshwari Shinde 	MAX77686_REG_PMIC_BUCK4DVS1	= 0x28,
65*857765e9SRajeshwari Shinde 	MAX77686_REG_PMIC_BUCK4DVS2,
66*857765e9SRajeshwari Shinde 	MAX77686_REG_PMIC_BUCK4DVS3,
67*857765e9SRajeshwari Shinde 	MAX77686_REG_PMIC_BUCK4DVS4,
68*857765e9SRajeshwari Shinde 	MAX77686_REG_PMIC_BUCK4DVS5,
69*857765e9SRajeshwari Shinde 	MAX77686_REG_PMIC_BUCK4DVS6,
70*857765e9SRajeshwari Shinde 	MAX77686_REG_PMIC_BUCK4DVS7,
71*857765e9SRajeshwari Shinde 	MAX77686_REG_PMIC_BUCK4DVS8,
72*857765e9SRajeshwari Shinde 	MAX77686_REG_PMIC_BUCK5CTRL,
73*857765e9SRajeshwari Shinde 	MAX77686_REG_PMIC_BUCK5OUT,
74*857765e9SRajeshwari Shinde 	MAX77686_REG_PMIC_BUCK6CRTL,
75*857765e9SRajeshwari Shinde 	MAX77686_REG_PMIC_BUCK6OUT,
76*857765e9SRajeshwari Shinde 	MAX77686_REG_PMIC_BUCK7CRTL,
77*857765e9SRajeshwari Shinde 	MAX77686_REG_PMIC_BUCK7OUT,
78*857765e9SRajeshwari Shinde 	MAX77686_REG_PMIC_BUCK8CRTL,
79*857765e9SRajeshwari Shinde 	MAX77686_REG_PMIC_BUCK8OUT,
80*857765e9SRajeshwari Shinde 	MAX77686_REG_PMIC_BUCK9CRTL,
81*857765e9SRajeshwari Shinde 	MAX77686_REG_PMIC_BUCK9OUT,
82*857765e9SRajeshwari Shinde 
83*857765e9SRajeshwari Shinde 	MAX77686_REG_PMIC_LDO1CTRL1	= 0x40,
84*857765e9SRajeshwari Shinde 	MAX77686_REG_PMIC_LDO2CTRL1,
85*857765e9SRajeshwari Shinde 	MAX77686_REG_PMIC_LDO3CTRL1,
86*857765e9SRajeshwari Shinde 	MAX77686_REG_PMIC_LDO4CTRL1,
87*857765e9SRajeshwari Shinde 	MAX77686_REG_PMIC_LDO5CTRL1,
88*857765e9SRajeshwari Shinde 	MAX77686_REG_PMIC_LDO6CTRL1,
89*857765e9SRajeshwari Shinde 	MAX77686_REG_PMIC_LDO7CTRL1,
90*857765e9SRajeshwari Shinde 	MAX77686_REG_PMIC_LDO8CTRL1,
91*857765e9SRajeshwari Shinde 	MAX77686_REG_PMIC_LDO9CTRL1,
92*857765e9SRajeshwari Shinde 	MAX77686_REG_PMIC_LDO10CTRL1,
93*857765e9SRajeshwari Shinde 	MAX77686_REG_PMIC_LDO11CTRL1,
94*857765e9SRajeshwari Shinde 	MAX77686_REG_PMIC_LDO12CTRL1,
95*857765e9SRajeshwari Shinde 	MAX77686_REG_PMIC_LDO13CTRL1,
96*857765e9SRajeshwari Shinde 	MAX77686_REG_PMIC_LDO14CTRL1,
97*857765e9SRajeshwari Shinde 	MAX77686_REG_PMIC_LDO15CTRL1,
98*857765e9SRajeshwari Shinde 	MAX77686_REG_PMIC_LDO16CTRL1,
99*857765e9SRajeshwari Shinde 	MAX77686_REG_PMIC_LDO17CTRL1,
100*857765e9SRajeshwari Shinde 	MAX77686_REG_PMIC_LDO18CTRL1,
101*857765e9SRajeshwari Shinde 	MAX77686_REG_PMIC_LDO19CTRL1,
102*857765e9SRajeshwari Shinde 	MAX77686_REG_PMIC_LDO20CTRL1,
103*857765e9SRajeshwari Shinde 	MAX77686_REG_PMIC_LDO21CTRL1,
104*857765e9SRajeshwari Shinde 	MAX77686_REG_PMIC_LDO22CTRL1,
105*857765e9SRajeshwari Shinde 	MAX77686_REG_PMIC_LDO23CTRL1,
106*857765e9SRajeshwari Shinde 	MAX77686_REG_PMIC_LDO24CTRL1,
107*857765e9SRajeshwari Shinde 	MAX77686_REG_PMIC_LDO25CTRL1,
108*857765e9SRajeshwari Shinde 	MAX77686_REG_PMIC_LDO26CTRL1,
109*857765e9SRajeshwari Shinde 	MAX77686_REG_PMIC_LDO1CTRL2,
110*857765e9SRajeshwari Shinde 	MAX77686_REG_PMIC_LDO2CTRL2,
111*857765e9SRajeshwari Shinde 	MAX77686_REG_PMIC_LDO3CTRL2,
112*857765e9SRajeshwari Shinde 	MAX77686_REG_PMIC_LDO4CTRL2,
113*857765e9SRajeshwari Shinde 	MAX77686_REG_PMIC_LDO5CTRL2,
114*857765e9SRajeshwari Shinde 	MAX77686_REG_PMIC_LDO6CTRL2,
115*857765e9SRajeshwari Shinde 	MAX77686_REG_PMIC_LDO7CTRL2,
116*857765e9SRajeshwari Shinde 	MAX77686_REG_PMIC_LDO8CTRL2,
117*857765e9SRajeshwari Shinde 	MAX77686_REG_PMIC_LDO9CTRL2,
118*857765e9SRajeshwari Shinde 	MAX77686_REG_PMIC_LDO10CTRL2,
119*857765e9SRajeshwari Shinde 	MAX77686_REG_PMIC_LDO11CTRL2,
120*857765e9SRajeshwari Shinde 	MAX77686_REG_PMIC_LDO12CTRL2,
121*857765e9SRajeshwari Shinde 	MAX77686_REG_PMIC_LDO13CTRL2,
122*857765e9SRajeshwari Shinde 	MAX77686_REG_PMIC_LDO14CTRL2,
123*857765e9SRajeshwari Shinde 	MAX77686_REG_PMIC_LDO15CTRL2,
124*857765e9SRajeshwari Shinde 	MAX77686_REG_PMIC_LDO16CTRL2,
125*857765e9SRajeshwari Shinde 	MAX77686_REG_PMIC_LDO17CTRL2,
126*857765e9SRajeshwari Shinde 	MAX77686_REG_PMIC_LDO18CTRL2,
127*857765e9SRajeshwari Shinde 	MAX77686_REG_PMIC_LDO19CTRL2,
128*857765e9SRajeshwari Shinde 	MAX77686_REG_PMIC_LDO20CTRL2,
129*857765e9SRajeshwari Shinde 	MAX77686_REG_PMIC_LDO21CTRL2,
130*857765e9SRajeshwari Shinde 	MAX77686_REG_PMIC_LDO22CTRL2,
131*857765e9SRajeshwari Shinde 	MAX77686_REG_PMIC_LDO23CTRL2,
132*857765e9SRajeshwari Shinde 	MAX77686_REG_PMIC_LDO24CTRL2,
133*857765e9SRajeshwari Shinde 	MAX77686_REG_PMIC_LDO25CTRL2,
134*857765e9SRajeshwari Shinde 	MAX77686_REG_PMIC_LDO26CTRL2,
135*857765e9SRajeshwari Shinde 
136*857765e9SRajeshwari Shinde 	MAX77686_REG_PMIC_BBAT		= 0x7e,
137*857765e9SRajeshwari Shinde 	MAX77686_REG_PMIC_32KHZ,
138*857765e9SRajeshwari Shinde 
139*857765e9SRajeshwari Shinde 	PMIC_NUM_OF_REGS,
140*857765e9SRajeshwari Shinde };
141*857765e9SRajeshwari Shinde 
142*857765e9SRajeshwari Shinde /* I2C device address for pmic max77686 */
143*857765e9SRajeshwari Shinde #define MAX77686_I2C_ADDR (0x12 >> 1)
144*857765e9SRajeshwari Shinde 
145*857765e9SRajeshwari Shinde enum {
146*857765e9SRajeshwari Shinde 	REG_DISABLE = 0,
147*857765e9SRajeshwari Shinde 	REG_ENABLE
148*857765e9SRajeshwari Shinde };
149*857765e9SRajeshwari Shinde 
150*857765e9SRajeshwari Shinde enum {
151*857765e9SRajeshwari Shinde 	LDO_OFF = 0,
152*857765e9SRajeshwari Shinde 	LDO_ON,
153*857765e9SRajeshwari Shinde 
154*857765e9SRajeshwari Shinde 	DIS_LDO = (0x00 << 6),
155*857765e9SRajeshwari Shinde 	EN_LDO = (0x3 << 6),
156*857765e9SRajeshwari Shinde };
157*857765e9SRajeshwari Shinde 
158*857765e9SRajeshwari Shinde #endif /* __MAX77686_PMIC_H_ */
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