1 /* 2 * (C) Copyright 2000-2004 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #ifndef _PCMCIA_H 9 #define _PCMCIA_H 10 11 #include <common.h> 12 #include <config.h> 13 14 /* 15 * Allow configuration to select PCMCIA slot, 16 * or try to generate a useful default 17 */ 18 #if defined(CONFIG_CMD_PCMCIA) || \ 19 (defined(CONFIG_CMD_IDE) && \ 20 (defined(CONFIG_IDE_8xx_PCCARD) || defined(CONFIG_IDE_8xx_DIRECT) ) ) 21 22 #if !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B) 23 24 #if defined(CONFIG_TQM8xxL) 25 # define CONFIG_PCMCIA_SLOT_B /* The TQM8xxL use SLOT_B */ 26 #elif defined(CONFIG_SPD823TS) /* The SPD8xx use SLOT_B */ 27 # define CONFIG_PCMCIA_SLOT_B 28 #elif defined(CONFIG_IVMS8) || defined(CONFIG_IVML24) /* The IVM* use SLOT_A */ 29 # define CONFIG_PCMCIA_SLOT_A 30 #elif defined(CONFIG_LWMON) /* The LWMON use SLOT_B */ 31 # define CONFIG_PCMCIA_SLOT_B 32 #elif defined(CONFIG_R360MPI) /* The R360MPI use SLOT_B */ 33 # define CONFIG_PCMCIA_SLOT_B 34 #elif defined(CONFIG_ATC) /* The ATC use SLOT_A */ 35 # define CONFIG_PCMCIA_SLOT_A 36 #else 37 # error "PCMCIA Slot not configured" 38 #endif 39 40 #endif /* !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B) */ 41 42 /* Make sure exactly one slot is defined - we support only one for now */ 43 #if !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B) 44 #error Neither CONFIG_PCMCIA_SLOT_A nor CONFIG_PCMCIA_SLOT_B configured 45 #endif 46 #if defined(CONFIG_PCMCIA_SLOT_A) && defined(CONFIG_PCMCIA_SLOT_B) 47 #error Both CONFIG_PCMCIA_SLOT_A and CONFIG_PCMCIA_SLOT_B configured 48 #endif 49 50 #ifndef PCMCIA_SOCKETS_NO 51 #define PCMCIA_SOCKETS_NO 1 52 #endif 53 #ifndef PCMCIA_MEM_WIN_NO 54 #define PCMCIA_MEM_WIN_NO 4 55 #endif 56 #define PCMCIA_IO_WIN_NO 2 57 58 /* define _slot_ to be able to optimize macros */ 59 #ifdef CONFIG_PCMCIA_SLOT_A 60 # define _slot_ 0 61 # define PCMCIA_SLOT_MSG "slot A" 62 # define PCMCIA_SLOT_x PCMCIA_PSLOT_A 63 #else 64 # define _slot_ 1 65 # define PCMCIA_SLOT_MSG "slot B" 66 # define PCMCIA_SLOT_x PCMCIA_PSLOT_B 67 #endif 68 69 /* 70 * The TQM850L hardware has two pins swapped! Grrrrgh! 71 */ 72 #ifdef CONFIG_TQM850L 73 #define __MY_PCMCIA_GCRX_CXRESET PCMCIA_GCRX_CXOE 74 #define __MY_PCMCIA_GCRX_CXOE PCMCIA_GCRX_CXRESET 75 #else 76 #define __MY_PCMCIA_GCRX_CXRESET PCMCIA_GCRX_CXRESET 77 #define __MY_PCMCIA_GCRX_CXOE PCMCIA_GCRX_CXOE 78 #endif 79 80 /* 81 * This structure is used to address each window in the PCMCIA controller. 82 * 83 * Keep in mind that we assume that pcmcia_win_t[n+1] is mapped directly 84 * after pcmcia_win_t[n]... 85 */ 86 87 typedef struct { 88 ulong br; 89 ulong or; 90 } pcmcia_win_t; 91 92 /* 93 * Definitions for PCMCIA control registers to operate in IDE mode 94 * 95 * All timing related setup (PCMCIA_SHT, PCMCIA_SST, PCMCIA_SL) 96 * to be done later (depending on CPU clock) 97 */ 98 99 /* Window 0: 100 * Base: 0xFE100000 CS1 101 * Port Size: 2 Bytes 102 * Port Size: 16 Bit 103 * Common Memory Space 104 */ 105 106 #define CONFIG_SYS_PCMCIA_PBR0 0xFE100000 107 #define CONFIG_SYS_PCMCIA_POR0 ( PCMCIA_BSIZE_2 \ 108 | PCMCIA_PPS_16 \ 109 | PCMCIA_PRS_MEM \ 110 | PCMCIA_SLOT_x \ 111 | PCMCIA_PV \ 112 ) 113 114 /* Window 1: 115 * Base: 0xFE100080 CS1 116 * Port Size: 8 Bytes 117 * Port Size: 8 Bit 118 * Common Memory Space 119 */ 120 121 #define CONFIG_SYS_PCMCIA_PBR1 0xFE100080 122 #define CONFIG_SYS_PCMCIA_POR1 ( PCMCIA_BSIZE_8 \ 123 | PCMCIA_PPS_8 \ 124 | PCMCIA_PRS_MEM \ 125 | PCMCIA_SLOT_x \ 126 | PCMCIA_PV \ 127 ) 128 129 /* Window 2: 130 * Base: 0xFE100100 CS2 131 * Port Size: 8 Bytes 132 * Port Size: 8 Bit 133 * Common Memory Space 134 */ 135 136 #define CONFIG_SYS_PCMCIA_PBR2 0xFE100100 137 #define CONFIG_SYS_PCMCIA_POR2 ( PCMCIA_BSIZE_8 \ 138 | PCMCIA_PPS_8 \ 139 | PCMCIA_PRS_MEM \ 140 | PCMCIA_SLOT_x \ 141 | PCMCIA_PV \ 142 ) 143 144 /* Window 3: 145 * not used 146 */ 147 #define CONFIG_SYS_PCMCIA_PBR3 0 148 #define CONFIG_SYS_PCMCIA_POR3 0 149 150 /* Window 4: 151 * Base: 0xFE100C00 CS1 152 * Port Size: 2 Bytes 153 * Port Size: 16 Bit 154 * Common Memory Space 155 */ 156 157 #define CONFIG_SYS_PCMCIA_PBR4 0xFE100C00 158 #define CONFIG_SYS_PCMCIA_POR4 ( PCMCIA_BSIZE_2 \ 159 | PCMCIA_PPS_16 \ 160 | PCMCIA_PRS_MEM \ 161 | PCMCIA_SLOT_x \ 162 | PCMCIA_PV \ 163 ) 164 165 /* Window 5: 166 * Base: 0xFE100C80 CS1 167 * Port Size: 8 Bytes 168 * Port Size: 8 Bit 169 * Common Memory Space 170 */ 171 172 #define CONFIG_SYS_PCMCIA_PBR5 0xFE100C80 173 #define CONFIG_SYS_PCMCIA_POR5 ( PCMCIA_BSIZE_8 \ 174 | PCMCIA_PPS_8 \ 175 | PCMCIA_PRS_MEM \ 176 | PCMCIA_SLOT_x \ 177 | PCMCIA_PV \ 178 ) 179 180 /* Window 6: 181 * Base: 0xFE100D00 CS2 182 * Port Size: 8 Bytes 183 * Port Size: 8 Bit 184 * Common Memory Space 185 */ 186 187 #define CONFIG_SYS_PCMCIA_PBR6 0xFE100D00 188 #define CONFIG_SYS_PCMCIA_POR6 ( PCMCIA_BSIZE_8 \ 189 | PCMCIA_PPS_8 \ 190 | PCMCIA_PRS_MEM \ 191 | PCMCIA_SLOT_x \ 192 | PCMCIA_PV \ 193 ) 194 195 /* Window 7: 196 * not used 197 */ 198 #define CONFIG_SYS_PCMCIA_PBR7 0 199 #define CONFIG_SYS_PCMCIA_POR7 0 200 201 /**********************************************************************/ 202 203 /* 204 * CIS Tupel codes 205 */ 206 #define CISTPL_NULL 0x00 207 #define CISTPL_DEVICE 0x01 208 #define CISTPL_LONGLINK_CB 0x02 209 #define CISTPL_INDIRECT 0x03 210 #define CISTPL_CONFIG_CB 0x04 211 #define CISTPL_CFTABLE_ENTRY_CB 0x05 212 #define CISTPL_LONGLINK_MFC 0x06 213 #define CISTPL_BAR 0x07 214 #define CISTPL_PWR_MGMNT 0x08 215 #define CISTPL_EXTDEVICE 0x09 216 #define CISTPL_CHECKSUM 0x10 217 #define CISTPL_LONGLINK_A 0x11 218 #define CISTPL_LONGLINK_C 0x12 219 #define CISTPL_LINKTARGET 0x13 220 #define CISTPL_NO_LINK 0x14 221 #define CISTPL_VERS_1 0x15 222 #define CISTPL_ALTSTR 0x16 223 #define CISTPL_DEVICE_A 0x17 224 #define CISTPL_JEDEC_C 0x18 225 #define CISTPL_JEDEC_A 0x19 226 #define CISTPL_CONFIG 0x1a 227 #define CISTPL_CFTABLE_ENTRY 0x1b 228 #define CISTPL_DEVICE_OC 0x1c 229 #define CISTPL_DEVICE_OA 0x1d 230 #define CISTPL_DEVICE_GEO 0x1e 231 #define CISTPL_DEVICE_GEO_A 0x1f 232 #define CISTPL_MANFID 0x20 233 #define CISTPL_FUNCID 0x21 234 #define CISTPL_FUNCE 0x22 235 #define CISTPL_SWIL 0x23 236 #define CISTPL_END 0xff 237 238 /* 239 * CIS Function ID codes 240 */ 241 #define CISTPL_FUNCID_MULTI 0x00 242 #define CISTPL_FUNCID_MEMORY 0x01 243 #define CISTPL_FUNCID_SERIAL 0x02 244 #define CISTPL_FUNCID_PARALLEL 0x03 245 #define CISTPL_FUNCID_FIXED 0x04 246 #define CISTPL_FUNCID_VIDEO 0x05 247 #define CISTPL_FUNCID_NETWORK 0x06 248 #define CISTPL_FUNCID_AIMS 0x07 249 #define CISTPL_FUNCID_SCSI 0x08 250 251 /* 252 * Fixed Disk FUNCE codes 253 */ 254 #define CISTPL_IDE_INTERFACE 0x01 255 256 #define CISTPL_FUNCE_IDE_IFACE 0x01 257 #define CISTPL_FUNCE_IDE_MASTER 0x02 258 #define CISTPL_FUNCE_IDE_SLAVE 0x03 259 260 /* First feature byte */ 261 #define CISTPL_IDE_SILICON 0x04 262 #define CISTPL_IDE_UNIQUE 0x08 263 #define CISTPL_IDE_DUAL 0x10 264 265 /* Second feature byte */ 266 #define CISTPL_IDE_HAS_SLEEP 0x01 267 #define CISTPL_IDE_HAS_STANDBY 0x02 268 #define CISTPL_IDE_HAS_IDLE 0x04 269 #define CISTPL_IDE_LOW_POWER 0x08 270 #define CISTPL_IDE_REG_INHIBIT 0x10 271 #define CISTPL_IDE_HAS_INDEX 0x20 272 #define CISTPL_IDE_IOIS16 0x40 273 274 #endif 275 276 #ifdef CONFIG_8xx 277 extern u_int *pcmcia_pgcrx[]; 278 #define PCMCIA_PGCRX(slot) (*pcmcia_pgcrx[slot]) 279 #endif 280 281 #if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD) 282 extern int check_ide_device(int slot); 283 #endif 284 285 #endif /* _PCMCIA_H */ 286