1 /* 2 * (C) Copyright 2000-2004 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #ifndef _PCMCIA_H 9 #define _PCMCIA_H 10 11 #include <common.h> 12 #include <config.h> 13 14 /* 15 * Allow configuration to select PCMCIA slot, 16 * or try to generate a useful default 17 */ 18 #if defined(CONFIG_CMD_PCMCIA) || \ 19 (defined(CONFIG_CMD_IDE) && \ 20 (defined(CONFIG_IDE_8xx_PCCARD) || defined(CONFIG_IDE_8xx_DIRECT) ) ) 21 22 #if !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B) 23 24 #if defined(CONFIG_TQM8xxL) 25 # define CONFIG_PCMCIA_SLOT_B /* The TQM8xxL use SLOT_B */ 26 #elif defined(CONFIG_ATC) /* The ATC use SLOT_A */ 27 # define CONFIG_PCMCIA_SLOT_A 28 #else 29 # error "PCMCIA Slot not configured" 30 #endif 31 32 #endif /* !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B) */ 33 34 /* Make sure exactly one slot is defined - we support only one for now */ 35 #if !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B) 36 #error Neither CONFIG_PCMCIA_SLOT_A nor CONFIG_PCMCIA_SLOT_B configured 37 #endif 38 #if defined(CONFIG_PCMCIA_SLOT_A) && defined(CONFIG_PCMCIA_SLOT_B) 39 #error Both CONFIG_PCMCIA_SLOT_A and CONFIG_PCMCIA_SLOT_B configured 40 #endif 41 42 #ifndef PCMCIA_SOCKETS_NO 43 #define PCMCIA_SOCKETS_NO 1 44 #endif 45 #ifndef PCMCIA_MEM_WIN_NO 46 #define PCMCIA_MEM_WIN_NO 4 47 #endif 48 #define PCMCIA_IO_WIN_NO 2 49 50 /* define _slot_ to be able to optimize macros */ 51 #ifdef CONFIG_PCMCIA_SLOT_A 52 # define _slot_ 0 53 # define PCMCIA_SLOT_MSG "slot A" 54 # define PCMCIA_SLOT_x PCMCIA_PSLOT_A 55 #else 56 # define _slot_ 1 57 # define PCMCIA_SLOT_MSG "slot B" 58 # define PCMCIA_SLOT_x PCMCIA_PSLOT_B 59 #endif 60 61 /* 62 * The TQM850L hardware has two pins swapped! Grrrrgh! 63 */ 64 #ifdef CONFIG_TQM850L 65 #define __MY_PCMCIA_GCRX_CXRESET PCMCIA_GCRX_CXOE 66 #define __MY_PCMCIA_GCRX_CXOE PCMCIA_GCRX_CXRESET 67 #else 68 #define __MY_PCMCIA_GCRX_CXRESET PCMCIA_GCRX_CXRESET 69 #define __MY_PCMCIA_GCRX_CXOE PCMCIA_GCRX_CXOE 70 #endif 71 72 /* 73 * This structure is used to address each window in the PCMCIA controller. 74 * 75 * Keep in mind that we assume that pcmcia_win_t[n+1] is mapped directly 76 * after pcmcia_win_t[n]... 77 */ 78 79 typedef struct { 80 ulong br; 81 ulong or; 82 } pcmcia_win_t; 83 84 /* 85 * Definitions for PCMCIA control registers to operate in IDE mode 86 * 87 * All timing related setup (PCMCIA_SHT, PCMCIA_SST, PCMCIA_SL) 88 * to be done later (depending on CPU clock) 89 */ 90 91 /* Window 0: 92 * Base: 0xFE100000 CS1 93 * Port Size: 2 Bytes 94 * Port Size: 16 Bit 95 * Common Memory Space 96 */ 97 98 #define CONFIG_SYS_PCMCIA_PBR0 0xFE100000 99 #define CONFIG_SYS_PCMCIA_POR0 ( PCMCIA_BSIZE_2 \ 100 | PCMCIA_PPS_16 \ 101 | PCMCIA_PRS_MEM \ 102 | PCMCIA_SLOT_x \ 103 | PCMCIA_PV \ 104 ) 105 106 /* Window 1: 107 * Base: 0xFE100080 CS1 108 * Port Size: 8 Bytes 109 * Port Size: 8 Bit 110 * Common Memory Space 111 */ 112 113 #define CONFIG_SYS_PCMCIA_PBR1 0xFE100080 114 #define CONFIG_SYS_PCMCIA_POR1 ( PCMCIA_BSIZE_8 \ 115 | PCMCIA_PPS_8 \ 116 | PCMCIA_PRS_MEM \ 117 | PCMCIA_SLOT_x \ 118 | PCMCIA_PV \ 119 ) 120 121 /* Window 2: 122 * Base: 0xFE100100 CS2 123 * Port Size: 8 Bytes 124 * Port Size: 8 Bit 125 * Common Memory Space 126 */ 127 128 #define CONFIG_SYS_PCMCIA_PBR2 0xFE100100 129 #define CONFIG_SYS_PCMCIA_POR2 ( PCMCIA_BSIZE_8 \ 130 | PCMCIA_PPS_8 \ 131 | PCMCIA_PRS_MEM \ 132 | PCMCIA_SLOT_x \ 133 | PCMCIA_PV \ 134 ) 135 136 /* Window 3: 137 * not used 138 */ 139 #define CONFIG_SYS_PCMCIA_PBR3 0 140 #define CONFIG_SYS_PCMCIA_POR3 0 141 142 /* Window 4: 143 * Base: 0xFE100C00 CS1 144 * Port Size: 2 Bytes 145 * Port Size: 16 Bit 146 * Common Memory Space 147 */ 148 149 #define CONFIG_SYS_PCMCIA_PBR4 0xFE100C00 150 #define CONFIG_SYS_PCMCIA_POR4 ( PCMCIA_BSIZE_2 \ 151 | PCMCIA_PPS_16 \ 152 | PCMCIA_PRS_MEM \ 153 | PCMCIA_SLOT_x \ 154 | PCMCIA_PV \ 155 ) 156 157 /* Window 5: 158 * Base: 0xFE100C80 CS1 159 * Port Size: 8 Bytes 160 * Port Size: 8 Bit 161 * Common Memory Space 162 */ 163 164 #define CONFIG_SYS_PCMCIA_PBR5 0xFE100C80 165 #define CONFIG_SYS_PCMCIA_POR5 ( PCMCIA_BSIZE_8 \ 166 | PCMCIA_PPS_8 \ 167 | PCMCIA_PRS_MEM \ 168 | PCMCIA_SLOT_x \ 169 | PCMCIA_PV \ 170 ) 171 172 /* Window 6: 173 * Base: 0xFE100D00 CS2 174 * Port Size: 8 Bytes 175 * Port Size: 8 Bit 176 * Common Memory Space 177 */ 178 179 #define CONFIG_SYS_PCMCIA_PBR6 0xFE100D00 180 #define CONFIG_SYS_PCMCIA_POR6 ( PCMCIA_BSIZE_8 \ 181 | PCMCIA_PPS_8 \ 182 | PCMCIA_PRS_MEM \ 183 | PCMCIA_SLOT_x \ 184 | PCMCIA_PV \ 185 ) 186 187 /* Window 7: 188 * not used 189 */ 190 #define CONFIG_SYS_PCMCIA_PBR7 0 191 #define CONFIG_SYS_PCMCIA_POR7 0 192 193 /**********************************************************************/ 194 195 /* 196 * CIS Tupel codes 197 */ 198 #define CISTPL_NULL 0x00 199 #define CISTPL_DEVICE 0x01 200 #define CISTPL_LONGLINK_CB 0x02 201 #define CISTPL_INDIRECT 0x03 202 #define CISTPL_CONFIG_CB 0x04 203 #define CISTPL_CFTABLE_ENTRY_CB 0x05 204 #define CISTPL_LONGLINK_MFC 0x06 205 #define CISTPL_BAR 0x07 206 #define CISTPL_PWR_MGMNT 0x08 207 #define CISTPL_EXTDEVICE 0x09 208 #define CISTPL_CHECKSUM 0x10 209 #define CISTPL_LONGLINK_A 0x11 210 #define CISTPL_LONGLINK_C 0x12 211 #define CISTPL_LINKTARGET 0x13 212 #define CISTPL_NO_LINK 0x14 213 #define CISTPL_VERS_1 0x15 214 #define CISTPL_ALTSTR 0x16 215 #define CISTPL_DEVICE_A 0x17 216 #define CISTPL_JEDEC_C 0x18 217 #define CISTPL_JEDEC_A 0x19 218 #define CISTPL_CONFIG 0x1a 219 #define CISTPL_CFTABLE_ENTRY 0x1b 220 #define CISTPL_DEVICE_OC 0x1c 221 #define CISTPL_DEVICE_OA 0x1d 222 #define CISTPL_DEVICE_GEO 0x1e 223 #define CISTPL_DEVICE_GEO_A 0x1f 224 #define CISTPL_MANFID 0x20 225 #define CISTPL_FUNCID 0x21 226 #define CISTPL_FUNCE 0x22 227 #define CISTPL_SWIL 0x23 228 #define CISTPL_END 0xff 229 230 /* 231 * CIS Function ID codes 232 */ 233 #define CISTPL_FUNCID_MULTI 0x00 234 #define CISTPL_FUNCID_MEMORY 0x01 235 #define CISTPL_FUNCID_SERIAL 0x02 236 #define CISTPL_FUNCID_PARALLEL 0x03 237 #define CISTPL_FUNCID_FIXED 0x04 238 #define CISTPL_FUNCID_VIDEO 0x05 239 #define CISTPL_FUNCID_NETWORK 0x06 240 #define CISTPL_FUNCID_AIMS 0x07 241 #define CISTPL_FUNCID_SCSI 0x08 242 243 /* 244 * Fixed Disk FUNCE codes 245 */ 246 #define CISTPL_IDE_INTERFACE 0x01 247 248 #define CISTPL_FUNCE_IDE_IFACE 0x01 249 #define CISTPL_FUNCE_IDE_MASTER 0x02 250 #define CISTPL_FUNCE_IDE_SLAVE 0x03 251 252 /* First feature byte */ 253 #define CISTPL_IDE_SILICON 0x04 254 #define CISTPL_IDE_UNIQUE 0x08 255 #define CISTPL_IDE_DUAL 0x10 256 257 /* Second feature byte */ 258 #define CISTPL_IDE_HAS_SLEEP 0x01 259 #define CISTPL_IDE_HAS_STANDBY 0x02 260 #define CISTPL_IDE_HAS_IDLE 0x04 261 #define CISTPL_IDE_LOW_POWER 0x08 262 #define CISTPL_IDE_REG_INHIBIT 0x10 263 #define CISTPL_IDE_HAS_INDEX 0x20 264 #define CISTPL_IDE_IOIS16 0x40 265 266 #endif 267 268 #ifdef CONFIG_8xx 269 extern u_int *pcmcia_pgcrx[]; 270 #define PCMCIA_PGCRX(slot) (*pcmcia_pgcrx[slot]) 271 #endif 272 273 #if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD) 274 extern int check_ide_device(int slot); 275 #endif 276 277 #endif /* _PCMCIA_H */ 278