1 /* 2 * (C) Copyright 2000-2004 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #ifndef _PCMCIA_H 9 #define _PCMCIA_H 10 11 #include <common.h> 12 #include <config.h> 13 14 /* 15 * Allow configuration to select PCMCIA slot, 16 * or try to generate a useful default 17 */ 18 #if defined(CONFIG_CMD_PCMCIA) || \ 19 (defined(CONFIG_CMD_IDE) && \ 20 (defined(CONFIG_IDE_8xx_PCCARD) || defined(CONFIG_IDE_8xx_DIRECT) ) ) 21 22 #if !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B) 23 24 #if defined(CONFIG_TQM8xxL) 25 # define CONFIG_PCMCIA_SLOT_B /* The TQM8xxL use SLOT_B */ 26 #elif defined(CONFIG_IVMS8) || defined(CONFIG_IVML24) /* The IVM* use SLOT_A */ 27 # define CONFIG_PCMCIA_SLOT_A 28 #elif defined(CONFIG_LWMON) /* The LWMON use SLOT_B */ 29 # define CONFIG_PCMCIA_SLOT_B 30 #elif defined(CONFIG_ATC) /* The ATC use SLOT_A */ 31 # define CONFIG_PCMCIA_SLOT_A 32 #else 33 # error "PCMCIA Slot not configured" 34 #endif 35 36 #endif /* !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B) */ 37 38 /* Make sure exactly one slot is defined - we support only one for now */ 39 #if !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B) 40 #error Neither CONFIG_PCMCIA_SLOT_A nor CONFIG_PCMCIA_SLOT_B configured 41 #endif 42 #if defined(CONFIG_PCMCIA_SLOT_A) && defined(CONFIG_PCMCIA_SLOT_B) 43 #error Both CONFIG_PCMCIA_SLOT_A and CONFIG_PCMCIA_SLOT_B configured 44 #endif 45 46 #ifndef PCMCIA_SOCKETS_NO 47 #define PCMCIA_SOCKETS_NO 1 48 #endif 49 #ifndef PCMCIA_MEM_WIN_NO 50 #define PCMCIA_MEM_WIN_NO 4 51 #endif 52 #define PCMCIA_IO_WIN_NO 2 53 54 /* define _slot_ to be able to optimize macros */ 55 #ifdef CONFIG_PCMCIA_SLOT_A 56 # define _slot_ 0 57 # define PCMCIA_SLOT_MSG "slot A" 58 # define PCMCIA_SLOT_x PCMCIA_PSLOT_A 59 #else 60 # define _slot_ 1 61 # define PCMCIA_SLOT_MSG "slot B" 62 # define PCMCIA_SLOT_x PCMCIA_PSLOT_B 63 #endif 64 65 /* 66 * The TQM850L hardware has two pins swapped! Grrrrgh! 67 */ 68 #ifdef CONFIG_TQM850L 69 #define __MY_PCMCIA_GCRX_CXRESET PCMCIA_GCRX_CXOE 70 #define __MY_PCMCIA_GCRX_CXOE PCMCIA_GCRX_CXRESET 71 #else 72 #define __MY_PCMCIA_GCRX_CXRESET PCMCIA_GCRX_CXRESET 73 #define __MY_PCMCIA_GCRX_CXOE PCMCIA_GCRX_CXOE 74 #endif 75 76 /* 77 * This structure is used to address each window in the PCMCIA controller. 78 * 79 * Keep in mind that we assume that pcmcia_win_t[n+1] is mapped directly 80 * after pcmcia_win_t[n]... 81 */ 82 83 typedef struct { 84 ulong br; 85 ulong or; 86 } pcmcia_win_t; 87 88 /* 89 * Definitions for PCMCIA control registers to operate in IDE mode 90 * 91 * All timing related setup (PCMCIA_SHT, PCMCIA_SST, PCMCIA_SL) 92 * to be done later (depending on CPU clock) 93 */ 94 95 /* Window 0: 96 * Base: 0xFE100000 CS1 97 * Port Size: 2 Bytes 98 * Port Size: 16 Bit 99 * Common Memory Space 100 */ 101 102 #define CONFIG_SYS_PCMCIA_PBR0 0xFE100000 103 #define CONFIG_SYS_PCMCIA_POR0 ( PCMCIA_BSIZE_2 \ 104 | PCMCIA_PPS_16 \ 105 | PCMCIA_PRS_MEM \ 106 | PCMCIA_SLOT_x \ 107 | PCMCIA_PV \ 108 ) 109 110 /* Window 1: 111 * Base: 0xFE100080 CS1 112 * Port Size: 8 Bytes 113 * Port Size: 8 Bit 114 * Common Memory Space 115 */ 116 117 #define CONFIG_SYS_PCMCIA_PBR1 0xFE100080 118 #define CONFIG_SYS_PCMCIA_POR1 ( PCMCIA_BSIZE_8 \ 119 | PCMCIA_PPS_8 \ 120 | PCMCIA_PRS_MEM \ 121 | PCMCIA_SLOT_x \ 122 | PCMCIA_PV \ 123 ) 124 125 /* Window 2: 126 * Base: 0xFE100100 CS2 127 * Port Size: 8 Bytes 128 * Port Size: 8 Bit 129 * Common Memory Space 130 */ 131 132 #define CONFIG_SYS_PCMCIA_PBR2 0xFE100100 133 #define CONFIG_SYS_PCMCIA_POR2 ( PCMCIA_BSIZE_8 \ 134 | PCMCIA_PPS_8 \ 135 | PCMCIA_PRS_MEM \ 136 | PCMCIA_SLOT_x \ 137 | PCMCIA_PV \ 138 ) 139 140 /* Window 3: 141 * not used 142 */ 143 #define CONFIG_SYS_PCMCIA_PBR3 0 144 #define CONFIG_SYS_PCMCIA_POR3 0 145 146 /* Window 4: 147 * Base: 0xFE100C00 CS1 148 * Port Size: 2 Bytes 149 * Port Size: 16 Bit 150 * Common Memory Space 151 */ 152 153 #define CONFIG_SYS_PCMCIA_PBR4 0xFE100C00 154 #define CONFIG_SYS_PCMCIA_POR4 ( PCMCIA_BSIZE_2 \ 155 | PCMCIA_PPS_16 \ 156 | PCMCIA_PRS_MEM \ 157 | PCMCIA_SLOT_x \ 158 | PCMCIA_PV \ 159 ) 160 161 /* Window 5: 162 * Base: 0xFE100C80 CS1 163 * Port Size: 8 Bytes 164 * Port Size: 8 Bit 165 * Common Memory Space 166 */ 167 168 #define CONFIG_SYS_PCMCIA_PBR5 0xFE100C80 169 #define CONFIG_SYS_PCMCIA_POR5 ( PCMCIA_BSIZE_8 \ 170 | PCMCIA_PPS_8 \ 171 | PCMCIA_PRS_MEM \ 172 | PCMCIA_SLOT_x \ 173 | PCMCIA_PV \ 174 ) 175 176 /* Window 6: 177 * Base: 0xFE100D00 CS2 178 * Port Size: 8 Bytes 179 * Port Size: 8 Bit 180 * Common Memory Space 181 */ 182 183 #define CONFIG_SYS_PCMCIA_PBR6 0xFE100D00 184 #define CONFIG_SYS_PCMCIA_POR6 ( PCMCIA_BSIZE_8 \ 185 | PCMCIA_PPS_8 \ 186 | PCMCIA_PRS_MEM \ 187 | PCMCIA_SLOT_x \ 188 | PCMCIA_PV \ 189 ) 190 191 /* Window 7: 192 * not used 193 */ 194 #define CONFIG_SYS_PCMCIA_PBR7 0 195 #define CONFIG_SYS_PCMCIA_POR7 0 196 197 /**********************************************************************/ 198 199 /* 200 * CIS Tupel codes 201 */ 202 #define CISTPL_NULL 0x00 203 #define CISTPL_DEVICE 0x01 204 #define CISTPL_LONGLINK_CB 0x02 205 #define CISTPL_INDIRECT 0x03 206 #define CISTPL_CONFIG_CB 0x04 207 #define CISTPL_CFTABLE_ENTRY_CB 0x05 208 #define CISTPL_LONGLINK_MFC 0x06 209 #define CISTPL_BAR 0x07 210 #define CISTPL_PWR_MGMNT 0x08 211 #define CISTPL_EXTDEVICE 0x09 212 #define CISTPL_CHECKSUM 0x10 213 #define CISTPL_LONGLINK_A 0x11 214 #define CISTPL_LONGLINK_C 0x12 215 #define CISTPL_LINKTARGET 0x13 216 #define CISTPL_NO_LINK 0x14 217 #define CISTPL_VERS_1 0x15 218 #define CISTPL_ALTSTR 0x16 219 #define CISTPL_DEVICE_A 0x17 220 #define CISTPL_JEDEC_C 0x18 221 #define CISTPL_JEDEC_A 0x19 222 #define CISTPL_CONFIG 0x1a 223 #define CISTPL_CFTABLE_ENTRY 0x1b 224 #define CISTPL_DEVICE_OC 0x1c 225 #define CISTPL_DEVICE_OA 0x1d 226 #define CISTPL_DEVICE_GEO 0x1e 227 #define CISTPL_DEVICE_GEO_A 0x1f 228 #define CISTPL_MANFID 0x20 229 #define CISTPL_FUNCID 0x21 230 #define CISTPL_FUNCE 0x22 231 #define CISTPL_SWIL 0x23 232 #define CISTPL_END 0xff 233 234 /* 235 * CIS Function ID codes 236 */ 237 #define CISTPL_FUNCID_MULTI 0x00 238 #define CISTPL_FUNCID_MEMORY 0x01 239 #define CISTPL_FUNCID_SERIAL 0x02 240 #define CISTPL_FUNCID_PARALLEL 0x03 241 #define CISTPL_FUNCID_FIXED 0x04 242 #define CISTPL_FUNCID_VIDEO 0x05 243 #define CISTPL_FUNCID_NETWORK 0x06 244 #define CISTPL_FUNCID_AIMS 0x07 245 #define CISTPL_FUNCID_SCSI 0x08 246 247 /* 248 * Fixed Disk FUNCE codes 249 */ 250 #define CISTPL_IDE_INTERFACE 0x01 251 252 #define CISTPL_FUNCE_IDE_IFACE 0x01 253 #define CISTPL_FUNCE_IDE_MASTER 0x02 254 #define CISTPL_FUNCE_IDE_SLAVE 0x03 255 256 /* First feature byte */ 257 #define CISTPL_IDE_SILICON 0x04 258 #define CISTPL_IDE_UNIQUE 0x08 259 #define CISTPL_IDE_DUAL 0x10 260 261 /* Second feature byte */ 262 #define CISTPL_IDE_HAS_SLEEP 0x01 263 #define CISTPL_IDE_HAS_STANDBY 0x02 264 #define CISTPL_IDE_HAS_IDLE 0x04 265 #define CISTPL_IDE_LOW_POWER 0x08 266 #define CISTPL_IDE_REG_INHIBIT 0x10 267 #define CISTPL_IDE_HAS_INDEX 0x20 268 #define CISTPL_IDE_IOIS16 0x40 269 270 #endif 271 272 #ifdef CONFIG_8xx 273 extern u_int *pcmcia_pgcrx[]; 274 #define PCMCIA_PGCRX(slot) (*pcmcia_pgcrx[slot]) 275 #endif 276 277 #if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD) 278 extern int check_ide_device(int slot); 279 #endif 280 281 #endif /* _PCMCIA_H */ 282