1 /* 2 * (C) Copyright 2000 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24 #ifndef _PCMCIA_H 25 #define _PCMCIA_H 26 27 #include <common.h> 28 #include <config.h> 29 30 /* 31 * Allow configuration to select PCMCIA slot, 32 * or try to generate a useful default 33 */ 34 #if ( CONFIG_COMMANDS & CFG_CMD_PCMCIA) || \ 35 ((CONFIG_COMMANDS & CFG_CMD_IDE) && \ 36 (defined(CONFIG_IDE_8xx_PCCARD) || defined(CONFIG_IDE_8xx_DIRECT) ) ) 37 38 #if !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B) 39 40 /* The RPX series use SLOT_B */ 41 #if defined(CONFIG_RPXCLASSIC) || defined(CONFIG_RPXLITE) 42 # define CONFIG_PCMCIA_SLOT_B 43 #elif defined(CONFIG_ADS) /* The ADS board uses SLOT_A */ 44 # define CONFIG_PCMCIA_SLOT_A 45 #elif defined(CONFIG_FADS) /* The FADS series are a mess */ 46 # if defined(CONFIG_MPC86x) || defined(CONFIG_MPC821) 47 # define CONFIG_PCMCIA_SLOT_A 48 # else 49 # define CONFIG_PCMCIA_SLOT_B 50 # endif 51 #elif defined(CONFIG_TQM8xxL) || defined(CONFIG_SVM_SC8xx) 52 # define CONFIG_PCMCIA_SLOT_B /* The TQM8xxL use SLOT_B */ 53 #elif defined(CONFIG_SPD823TS) /* The SPD8xx use SLOT_B */ 54 # define CONFIG_PCMCIA_SLOT_B 55 #elif defined(CONFIG_IVMS8) || defined(CONFIG_IVML24) /* The IVM* use SLOT_A */ 56 # define CONFIG_PCMCIA_SLOT_A 57 #elif defined(CONFIG_LWMON) /* The LWMON use SLOT_B */ 58 # define CONFIG_PCMCIA_SLOT_B 59 #elif defined(CONFIG_ICU862) /* The ICU862 use SLOT_B */ 60 # define CONFIG_PCMCIA_SLOT_B 61 #elif defined(CONFIG_C2MON) /* The C2MON use SLOT_B */ 62 # define CONFIG_PCMCIA_SLOT_B 63 #elif defined(CONFIG_R360MPI) /* The R360MPI use SLOT_B */ 64 # define CONFIG_PCMCIA_SLOT_B 65 #elif defined(CONFIG_ATC) /* The ATC use SLOT_A */ 66 # define CONFIG_PCMCIA_SLOT_A 67 #else 68 # error "PCMCIA Slot not configured" 69 #endif 70 71 #endif /* !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B) */ 72 73 /* Make sure exactly one slot is defined - we support only one for now */ 74 #if !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B) 75 #error Neither CONFIG_PCMCIA_SLOT_A nor CONFIG_PCMCIA_SLOT_B configured 76 #endif 77 #if defined(CONFIG_PCMCIA_SLOT_A) && defined(CONFIG_PCMCIA_SLOT_B) 78 #error Both CONFIG_PCMCIA_SLOT_A and CONFIG_PCMCIA_SLOT_B configured 79 #endif 80 81 #ifndef PCMCIA_SOCKETS_NO 82 #define PCMCIA_SOCKETS_NO 1 83 #endif 84 #ifndef PCMCIA_MEM_WIN_NO 85 #define PCMCIA_MEM_WIN_NO 4 86 #endif 87 #define PCMCIA_IO_WIN_NO 2 88 89 /* define _slot_ to be able to optimize macros */ 90 #ifdef CONFIG_PCMCIA_SLOT_A 91 # define _slot_ 0 92 # define PCMCIA_SLOT_MSG "slot A" 93 # define PCMCIA_SLOT_x PCMCIA_PSLOT_A 94 #else 95 # define _slot_ 1 96 # define PCMCIA_SLOT_MSG "slot B" 97 # define PCMCIA_SLOT_x PCMCIA_PSLOT_B 98 #endif 99 100 /* 101 * The TQM850L hardware has two pins swapped! Grrrrgh! 102 */ 103 #ifdef CONFIG_TQM850L 104 #define __MY_PCMCIA_GCRX_CXRESET PCMCIA_GCRX_CXOE 105 #define __MY_PCMCIA_GCRX_CXOE PCMCIA_GCRX_CXRESET 106 #else 107 #define __MY_PCMCIA_GCRX_CXRESET PCMCIA_GCRX_CXRESET 108 #define __MY_PCMCIA_GCRX_CXOE PCMCIA_GCRX_CXOE 109 #endif 110 111 /* 112 * This structure is used to address each window in the PCMCIA controller. 113 * 114 * Keep in mind that we assume that pcmcia_win_t[n+1] is mapped directly 115 * after pcmcia_win_t[n]... 116 */ 117 118 typedef struct { 119 ulong br; 120 ulong or; 121 } pcmcia_win_t; 122 123 /* 124 * Definitions for PCMCIA control registers to operate in IDE mode 125 * 126 * All timing related setup (PCMCIA_SHT, PCMCIA_SST, PCMCIA_SL) 127 * to be done later (depending on CPU clock) 128 */ 129 130 /* Window 0: 131 * Base: 0xFE100000 CS1 132 * Port Size: 2 Bytes 133 * Port Size: 16 Bit 134 * Common Memory Space 135 */ 136 137 #define CFG_PCMCIA_PBR0 0xFE100000 138 #define CFG_PCMCIA_POR0 ( PCMCIA_BSIZE_2 \ 139 | PCMCIA_PPS_16 \ 140 | PCMCIA_PRS_MEM \ 141 | PCMCIA_SLOT_x \ 142 | PCMCIA_PV \ 143 ) 144 145 /* Window 1: 146 * Base: 0xFE100080 CS1 147 * Port Size: 8 Bytes 148 * Port Size: 8 Bit 149 * Common Memory Space 150 */ 151 152 #define CFG_PCMCIA_PBR1 0xFE100080 153 #define CFG_PCMCIA_POR1 ( PCMCIA_BSIZE_8 \ 154 | PCMCIA_PPS_8 \ 155 | PCMCIA_PRS_MEM \ 156 | PCMCIA_SLOT_x \ 157 | PCMCIA_PV \ 158 ) 159 160 /* Window 2: 161 * Base: 0xFE100100 CS2 162 * Port Size: 8 Bytes 163 * Port Size: 8 Bit 164 * Common Memory Space 165 */ 166 167 #define CFG_PCMCIA_PBR2 0xFE100100 168 #define CFG_PCMCIA_POR2 ( PCMCIA_BSIZE_8 \ 169 | PCMCIA_PPS_8 \ 170 | PCMCIA_PRS_MEM \ 171 | PCMCIA_SLOT_x \ 172 | PCMCIA_PV \ 173 ) 174 175 /* Window 3: 176 * not used 177 */ 178 #define CFG_PCMCIA_PBR3 0 179 #define CFG_PCMCIA_POR3 0 180 181 /* Window 4: 182 * Base: 0xFE100C00 CS1 183 * Port Size: 2 Bytes 184 * Port Size: 16 Bit 185 * Common Memory Space 186 */ 187 188 #define CFG_PCMCIA_PBR4 0xFE100C00 189 #define CFG_PCMCIA_POR4 ( PCMCIA_BSIZE_2 \ 190 | PCMCIA_PPS_16 \ 191 | PCMCIA_PRS_MEM \ 192 | PCMCIA_SLOT_x \ 193 | PCMCIA_PV \ 194 ) 195 196 /* Window 5: 197 * Base: 0xFE100C80 CS1 198 * Port Size: 8 Bytes 199 * Port Size: 8 Bit 200 * Common Memory Space 201 */ 202 203 #define CFG_PCMCIA_PBR5 0xFE100C80 204 #define CFG_PCMCIA_POR5 ( PCMCIA_BSIZE_8 \ 205 | PCMCIA_PPS_8 \ 206 | PCMCIA_PRS_MEM \ 207 | PCMCIA_SLOT_x \ 208 | PCMCIA_PV \ 209 ) 210 211 /* Window 6: 212 * Base: 0xFE100D00 CS2 213 * Port Size: 8 Bytes 214 * Port Size: 8 Bit 215 * Common Memory Space 216 */ 217 218 #define CFG_PCMCIA_PBR6 0xFE100D00 219 #define CFG_PCMCIA_POR6 ( PCMCIA_BSIZE_8 \ 220 | PCMCIA_PPS_8 \ 221 | PCMCIA_PRS_MEM \ 222 | PCMCIA_SLOT_x \ 223 | PCMCIA_PV \ 224 ) 225 226 /* Window 7: 227 * not used 228 */ 229 #define CFG_PCMCIA_PBR7 0 230 #define CFG_PCMCIA_POR7 0 231 232 /**********************************************************************/ 233 234 /* 235 * CIS Tupel codes 236 */ 237 #define CISTPL_NULL 0x00 238 #define CISTPL_DEVICE 0x01 239 #define CISTPL_LONGLINK_CB 0x02 240 #define CISTPL_INDIRECT 0x03 241 #define CISTPL_CONFIG_CB 0x04 242 #define CISTPL_CFTABLE_ENTRY_CB 0x05 243 #define CISTPL_LONGLINK_MFC 0x06 244 #define CISTPL_BAR 0x07 245 #define CISTPL_PWR_MGMNT 0x08 246 #define CISTPL_EXTDEVICE 0x09 247 #define CISTPL_CHECKSUM 0x10 248 #define CISTPL_LONGLINK_A 0x11 249 #define CISTPL_LONGLINK_C 0x12 250 #define CISTPL_LINKTARGET 0x13 251 #define CISTPL_NO_LINK 0x14 252 #define CISTPL_VERS_1 0x15 253 #define CISTPL_ALTSTR 0x16 254 #define CISTPL_DEVICE_A 0x17 255 #define CISTPL_JEDEC_C 0x18 256 #define CISTPL_JEDEC_A 0x19 257 #define CISTPL_CONFIG 0x1a 258 #define CISTPL_CFTABLE_ENTRY 0x1b 259 #define CISTPL_DEVICE_OC 0x1c 260 #define CISTPL_DEVICE_OA 0x1d 261 #define CISTPL_DEVICE_GEO 0x1e 262 #define CISTPL_DEVICE_GEO_A 0x1f 263 #define CISTPL_MANFID 0x20 264 #define CISTPL_FUNCID 0x21 265 #define CISTPL_FUNCE 0x22 266 #define CISTPL_SWIL 0x23 267 #define CISTPL_END 0xff 268 269 /* 270 * CIS Function ID codes 271 */ 272 #define CISTPL_FUNCID_MULTI 0x00 273 #define CISTPL_FUNCID_MEMORY 0x01 274 #define CISTPL_FUNCID_SERIAL 0x02 275 #define CISTPL_FUNCID_PARALLEL 0x03 276 #define CISTPL_FUNCID_FIXED 0x04 277 #define CISTPL_FUNCID_VIDEO 0x05 278 #define CISTPL_FUNCID_NETWORK 0x06 279 #define CISTPL_FUNCID_AIMS 0x07 280 #define CISTPL_FUNCID_SCSI 0x08 281 282 /* 283 * Fixed Disk FUNCE codes 284 */ 285 #define CISTPL_IDE_INTERFACE 0x01 286 287 #define CISTPL_FUNCE_IDE_IFACE 0x01 288 #define CISTPL_FUNCE_IDE_MASTER 0x02 289 #define CISTPL_FUNCE_IDE_SLAVE 0x03 290 291 /* First feature byte */ 292 #define CISTPL_IDE_SILICON 0x04 293 #define CISTPL_IDE_UNIQUE 0x08 294 #define CISTPL_IDE_DUAL 0x10 295 296 /* Second feature byte */ 297 #define CISTPL_IDE_HAS_SLEEP 0x01 298 #define CISTPL_IDE_HAS_STANDBY 0x02 299 #define CISTPL_IDE_HAS_IDLE 0x04 300 #define CISTPL_IDE_LOW_POWER 0x08 301 #define CISTPL_IDE_REG_INHIBIT 0x10 302 #define CISTPL_IDE_HAS_INDEX 0x20 303 #define CISTPL_IDE_IOIS16 0x40 304 305 #endif /* CFG_CMD_PCMCIA || CFG_CMD_IDE && (CONFIG_IDE_8xx_PCCARD || CONFIG_IDE_8xx_DIRECT) */ 306 307 #endif /* _PCMCIA_H */ 308