1affae2bfSwdenk /* 2affae2bfSwdenk * (C) Copyright 2000 3affae2bfSwdenk * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4affae2bfSwdenk * 5affae2bfSwdenk * See file CREDITS for list of people who contributed to this 6affae2bfSwdenk * project. 7affae2bfSwdenk * 8affae2bfSwdenk * This program is free software; you can redistribute it and/or 9affae2bfSwdenk * modify it under the terms of the GNU General Public License as 10affae2bfSwdenk * published by the Free Software Foundation; either version 2 of 11affae2bfSwdenk * the License, or (at your option) any later version. 12affae2bfSwdenk * 13affae2bfSwdenk * This program is distributed in the hope that it will be useful, 14affae2bfSwdenk * but WITHOUT ANY WARRANTY; without even the implied warranty of 15affae2bfSwdenk * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16affae2bfSwdenk * GNU General Public License for more details. 17affae2bfSwdenk * 18affae2bfSwdenk * You should have received a copy of the GNU General Public License 19affae2bfSwdenk * along with this program; if not, write to the Free Software 20affae2bfSwdenk * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21affae2bfSwdenk * MA 02111-1307 USA 22affae2bfSwdenk */ 23affae2bfSwdenk 24affae2bfSwdenk #ifndef _PCMCIA_H 25affae2bfSwdenk #define _PCMCIA_H 26affae2bfSwdenk 27affae2bfSwdenk #include <common.h> 28affae2bfSwdenk #include <config.h> 29affae2bfSwdenk 30affae2bfSwdenk /* 31affae2bfSwdenk * Allow configuration to select PCMCIA slot, 32affae2bfSwdenk * or try to generate a useful default 33affae2bfSwdenk */ 34affae2bfSwdenk #if ( CONFIG_COMMANDS & CFG_CMD_PCMCIA) || \ 35affae2bfSwdenk ((CONFIG_COMMANDS & CFG_CMD_IDE) && \ 36affae2bfSwdenk (defined(CONFIG_IDE_8xx_PCCARD) || defined(CONFIG_IDE_8xx_DIRECT) ) ) 37affae2bfSwdenk 38affae2bfSwdenk #if !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B) 39affae2bfSwdenk 40affae2bfSwdenk /* The RPX series use SLOT_B */ 41affae2bfSwdenk #if defined(CONFIG_RPXCLASSIC) || defined(CONFIG_RPXLITE) 42affae2bfSwdenk # define CONFIG_PCMCIA_SLOT_B 43affae2bfSwdenk #elif defined(CONFIG_ADS) /* The ADS board use SLOT_A */ 44affae2bfSwdenk # define CONFIG_PCMCIA_SLOT_A 45affae2bfSwdenk #elif defined(CONFIG_FADS) /* The FADS series are a mess */ 46affae2bfSwdenk # if defined(CONFIG_MPC860T) || defined(CONFIG_MPC860) || defined(CONFIG_MPC821) 47affae2bfSwdenk # define CONFIG_PCMCIA_SLOT_A 48affae2bfSwdenk # else 49affae2bfSwdenk # define CONFIG_PCMCIA_SLOT_B 50affae2bfSwdenk # endif 51dc7c9a1aSwdenk #elif defined(CONFIG_TQM8xxL) || defined(CONFIG_SVM_SC8xx) 52affae2bfSwdenk # define CONFIG_PCMCIA_SLOT_B /* The TQM8xxL use SLOT_B */ 53affae2bfSwdenk #elif defined(CONFIG_SPD823TS) /* The SPD8xx use SLOT_B */ 54affae2bfSwdenk # define CONFIG_PCMCIA_SLOT_B 55affae2bfSwdenk #elif defined(CONFIG_IVMS8) || defined(CONFIG_IVML24) /* The IVM* use SLOT_A */ 56affae2bfSwdenk # define CONFIG_PCMCIA_SLOT_A 57affae2bfSwdenk #elif defined(CONFIG_LWMON) /* The LWMON use SLOT_B */ 58affae2bfSwdenk # define CONFIG_PCMCIA_SLOT_B 59affae2bfSwdenk #elif defined(CONFIG_ICU862) /* The ICU862 use SLOT_B */ 60affae2bfSwdenk # define CONFIG_PCMCIA_SLOT_B 61affae2bfSwdenk #elif defined(CONFIG_C2MON) /* The C2MON use SLOT_B */ 62affae2bfSwdenk # define CONFIG_PCMCIA_SLOT_B 63affae2bfSwdenk #elif defined(CONFIG_R360MPI) /* The R360MPI use SLOT_B */ 64affae2bfSwdenk # define CONFIG_PCMCIA_SLOT_B 65*66fd3d1cSwdenk #elif defined(CONFIG_ATC) /* The ATC use SLOT_A */ 66*66fd3d1cSwdenk # define CONFIG_PCMCIA_SLOT_A 67affae2bfSwdenk #else 68affae2bfSwdenk # error "PCMCIA Slot not configured" 69affae2bfSwdenk #endif 70affae2bfSwdenk 71affae2bfSwdenk #endif /* !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B) */ 72affae2bfSwdenk 73affae2bfSwdenk /* Make sure exactly one slot is defined - we support only one for now */ 74affae2bfSwdenk #if !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B) 75affae2bfSwdenk #error Neither CONFIG_PCMCIA_SLOT_A nor CONFIG_PCMCIA_SLOT_B configured 76affae2bfSwdenk #endif 77affae2bfSwdenk #if defined(CONFIG_PCMCIA_SLOT_A) && defined(CONFIG_PCMCIA_SLOT_B) 78affae2bfSwdenk #error Both CONFIG_PCMCIA_SLOT_A and CONFIG_PCMCIA_SLOT_B configured 79affae2bfSwdenk #endif 80affae2bfSwdenk 81ea909b76Swdenk #ifndef PCMCIA_SOCKETS_NO 82affae2bfSwdenk #define PCMCIA_SOCKETS_NO 1 83ea909b76Swdenk #endif 84ea909b76Swdenk #ifndef PCMCIA_MEM_WIN_NO 85affae2bfSwdenk #define PCMCIA_MEM_WIN_NO 4 86ea909b76Swdenk #endif 87affae2bfSwdenk #define PCMCIA_IO_WIN_NO 2 88affae2bfSwdenk 89affae2bfSwdenk /* define _slot_ to be able to optimize macros */ 90affae2bfSwdenk #ifdef CONFIG_PCMCIA_SLOT_A 91affae2bfSwdenk # define _slot_ 0 92affae2bfSwdenk # define PCMCIA_SLOT_MSG "slot A" 93affae2bfSwdenk # define PCMCIA_SLOT_x PCMCIA_PSLOT_A 94affae2bfSwdenk #else 95affae2bfSwdenk # define _slot_ 1 96affae2bfSwdenk # define PCMCIA_SLOT_MSG "slot B" 97affae2bfSwdenk # define PCMCIA_SLOT_x PCMCIA_PSLOT_B 98affae2bfSwdenk #endif 99affae2bfSwdenk 100affae2bfSwdenk /* 101affae2bfSwdenk * The TQM850L hardware has two pins swapped! Grrrrgh! 102affae2bfSwdenk */ 103affae2bfSwdenk #ifdef CONFIG_TQM850L 104affae2bfSwdenk #define __MY_PCMCIA_GCRX_CXRESET PCMCIA_GCRX_CXOE 105affae2bfSwdenk #define __MY_PCMCIA_GCRX_CXOE PCMCIA_GCRX_CXRESET 106affae2bfSwdenk #else 107affae2bfSwdenk #define __MY_PCMCIA_GCRX_CXRESET PCMCIA_GCRX_CXRESET 108affae2bfSwdenk #define __MY_PCMCIA_GCRX_CXOE PCMCIA_GCRX_CXOE 109affae2bfSwdenk #endif 110affae2bfSwdenk 111affae2bfSwdenk /* 112affae2bfSwdenk * This structure is used to address each window in the PCMCIA controller. 113affae2bfSwdenk * 114affae2bfSwdenk * Keep in mind that we assume that pcmcia_win_t[n+1] is mapped directly 115affae2bfSwdenk * after pcmcia_win_t[n]... 116affae2bfSwdenk */ 117affae2bfSwdenk 118affae2bfSwdenk typedef struct { 119affae2bfSwdenk ulong br; 120affae2bfSwdenk ulong or; 121affae2bfSwdenk } pcmcia_win_t; 122affae2bfSwdenk 123affae2bfSwdenk /* 124affae2bfSwdenk * Definitions for PCMCIA control registers to operate in IDE mode 125affae2bfSwdenk * 126affae2bfSwdenk * All timing related setup (PCMCIA_SHT, PCMCIA_SST, PCMCIA_SL) 127affae2bfSwdenk * to be done later (depending on CPU clock) 128affae2bfSwdenk */ 129affae2bfSwdenk 130affae2bfSwdenk /* Window 0: 131affae2bfSwdenk * Base: 0xFE100000 CS1 132affae2bfSwdenk * Port Size: 2 Bytes 133affae2bfSwdenk * Port Size: 16 Bit 134affae2bfSwdenk * Common Memory Space 135affae2bfSwdenk */ 136affae2bfSwdenk 137affae2bfSwdenk #define CFG_PCMCIA_PBR0 0xFE100000 138affae2bfSwdenk #define CFG_PCMCIA_POR0 ( PCMCIA_BSIZE_2 \ 139affae2bfSwdenk | PCMCIA_PPS_16 \ 140affae2bfSwdenk | PCMCIA_PRS_MEM \ 141affae2bfSwdenk | PCMCIA_SLOT_x \ 142affae2bfSwdenk | PCMCIA_PV \ 143affae2bfSwdenk ) 144affae2bfSwdenk 145affae2bfSwdenk /* Window 1: 146affae2bfSwdenk * Base: 0xFE100080 CS1 147affae2bfSwdenk * Port Size: 8 Bytes 148affae2bfSwdenk * Port Size: 8 Bit 149affae2bfSwdenk * Common Memory Space 150affae2bfSwdenk */ 151affae2bfSwdenk 152affae2bfSwdenk #define CFG_PCMCIA_PBR1 0xFE100080 153affae2bfSwdenk #define CFG_PCMCIA_POR1 ( PCMCIA_BSIZE_8 \ 154affae2bfSwdenk | PCMCIA_PPS_8 \ 155affae2bfSwdenk | PCMCIA_PRS_MEM \ 156affae2bfSwdenk | PCMCIA_SLOT_x \ 157affae2bfSwdenk | PCMCIA_PV \ 158affae2bfSwdenk ) 159affae2bfSwdenk 160affae2bfSwdenk /* Window 2: 161affae2bfSwdenk * Base: 0xFE100100 CS2 162affae2bfSwdenk * Port Size: 8 Bytes 163affae2bfSwdenk * Port Size: 8 Bit 164affae2bfSwdenk * Common Memory Space 165affae2bfSwdenk */ 166affae2bfSwdenk 167affae2bfSwdenk #define CFG_PCMCIA_PBR2 0xFE100100 168affae2bfSwdenk #define CFG_PCMCIA_POR2 ( PCMCIA_BSIZE_8 \ 169affae2bfSwdenk | PCMCIA_PPS_8 \ 170affae2bfSwdenk | PCMCIA_PRS_MEM \ 171affae2bfSwdenk | PCMCIA_SLOT_x \ 172affae2bfSwdenk | PCMCIA_PV \ 173affae2bfSwdenk ) 174affae2bfSwdenk 175affae2bfSwdenk /* Window 3: 176affae2bfSwdenk * not used 177affae2bfSwdenk */ 178affae2bfSwdenk #define CFG_PCMCIA_PBR3 0 179affae2bfSwdenk #define CFG_PCMCIA_POR3 0 180affae2bfSwdenk 181affae2bfSwdenk /* Window 4: 182affae2bfSwdenk * Base: 0xFE100C00 CS1 183affae2bfSwdenk * Port Size: 2 Bytes 184affae2bfSwdenk * Port Size: 16 Bit 185affae2bfSwdenk * Common Memory Space 186affae2bfSwdenk */ 187affae2bfSwdenk 188affae2bfSwdenk #define CFG_PCMCIA_PBR4 0xFE100C00 189affae2bfSwdenk #define CFG_PCMCIA_POR4 ( PCMCIA_BSIZE_2 \ 190affae2bfSwdenk | PCMCIA_PPS_16 \ 191affae2bfSwdenk | PCMCIA_PRS_MEM \ 192affae2bfSwdenk | PCMCIA_SLOT_x \ 193affae2bfSwdenk | PCMCIA_PV \ 194affae2bfSwdenk ) 195affae2bfSwdenk 196affae2bfSwdenk /* Window 5: 197affae2bfSwdenk * Base: 0xFE100C80 CS1 198affae2bfSwdenk * Port Size: 8 Bytes 199affae2bfSwdenk * Port Size: 8 Bit 200affae2bfSwdenk * Common Memory Space 201affae2bfSwdenk */ 202affae2bfSwdenk 203affae2bfSwdenk #define CFG_PCMCIA_PBR5 0xFE100C80 204affae2bfSwdenk #define CFG_PCMCIA_POR5 ( PCMCIA_BSIZE_8 \ 205affae2bfSwdenk | PCMCIA_PPS_8 \ 206affae2bfSwdenk | PCMCIA_PRS_MEM \ 207affae2bfSwdenk | PCMCIA_SLOT_x \ 208affae2bfSwdenk | PCMCIA_PV \ 209affae2bfSwdenk ) 210affae2bfSwdenk 211affae2bfSwdenk /* Window 6: 212affae2bfSwdenk * Base: 0xFE100D00 CS2 213affae2bfSwdenk * Port Size: 8 Bytes 214affae2bfSwdenk * Port Size: 8 Bit 215affae2bfSwdenk * Common Memory Space 216affae2bfSwdenk */ 217affae2bfSwdenk 218affae2bfSwdenk #define CFG_PCMCIA_PBR6 0xFE100D00 219affae2bfSwdenk #define CFG_PCMCIA_POR6 ( PCMCIA_BSIZE_8 \ 220affae2bfSwdenk | PCMCIA_PPS_8 \ 221affae2bfSwdenk | PCMCIA_PRS_MEM \ 222affae2bfSwdenk | PCMCIA_SLOT_x \ 223affae2bfSwdenk | PCMCIA_PV \ 224affae2bfSwdenk ) 225affae2bfSwdenk 226affae2bfSwdenk /* Window 7: 227affae2bfSwdenk * not used 228affae2bfSwdenk */ 229affae2bfSwdenk #define CFG_PCMCIA_PBR7 0 230affae2bfSwdenk #define CFG_PCMCIA_POR7 0 231affae2bfSwdenk 232affae2bfSwdenk /**********************************************************************/ 233affae2bfSwdenk 234affae2bfSwdenk /* 235affae2bfSwdenk * CIS Tupel codes 236affae2bfSwdenk */ 237affae2bfSwdenk #define CISTPL_NULL 0x00 238affae2bfSwdenk #define CISTPL_DEVICE 0x01 239affae2bfSwdenk #define CISTPL_LONGLINK_CB 0x02 240affae2bfSwdenk #define CISTPL_INDIRECT 0x03 241affae2bfSwdenk #define CISTPL_CONFIG_CB 0x04 242affae2bfSwdenk #define CISTPL_CFTABLE_ENTRY_CB 0x05 243affae2bfSwdenk #define CISTPL_LONGLINK_MFC 0x06 244affae2bfSwdenk #define CISTPL_BAR 0x07 245affae2bfSwdenk #define CISTPL_PWR_MGMNT 0x08 246affae2bfSwdenk #define CISTPL_EXTDEVICE 0x09 247affae2bfSwdenk #define CISTPL_CHECKSUM 0x10 248affae2bfSwdenk #define CISTPL_LONGLINK_A 0x11 249affae2bfSwdenk #define CISTPL_LONGLINK_C 0x12 250affae2bfSwdenk #define CISTPL_LINKTARGET 0x13 251affae2bfSwdenk #define CISTPL_NO_LINK 0x14 252affae2bfSwdenk #define CISTPL_VERS_1 0x15 253affae2bfSwdenk #define CISTPL_ALTSTR 0x16 254affae2bfSwdenk #define CISTPL_DEVICE_A 0x17 255affae2bfSwdenk #define CISTPL_JEDEC_C 0x18 256affae2bfSwdenk #define CISTPL_JEDEC_A 0x19 257affae2bfSwdenk #define CISTPL_CONFIG 0x1a 258affae2bfSwdenk #define CISTPL_CFTABLE_ENTRY 0x1b 259affae2bfSwdenk #define CISTPL_DEVICE_OC 0x1c 260affae2bfSwdenk #define CISTPL_DEVICE_OA 0x1d 261affae2bfSwdenk #define CISTPL_DEVICE_GEO 0x1e 262affae2bfSwdenk #define CISTPL_DEVICE_GEO_A 0x1f 263affae2bfSwdenk #define CISTPL_MANFID 0x20 264affae2bfSwdenk #define CISTPL_FUNCID 0x21 265affae2bfSwdenk #define CISTPL_FUNCE 0x22 266affae2bfSwdenk #define CISTPL_SWIL 0x23 267affae2bfSwdenk #define CISTPL_END 0xff 268affae2bfSwdenk 269affae2bfSwdenk /* 270affae2bfSwdenk * CIS Function ID codes 271affae2bfSwdenk */ 272affae2bfSwdenk #define CISTPL_FUNCID_MULTI 0x00 273affae2bfSwdenk #define CISTPL_FUNCID_MEMORY 0x01 274affae2bfSwdenk #define CISTPL_FUNCID_SERIAL 0x02 275affae2bfSwdenk #define CISTPL_FUNCID_PARALLEL 0x03 276affae2bfSwdenk #define CISTPL_FUNCID_FIXED 0x04 277affae2bfSwdenk #define CISTPL_FUNCID_VIDEO 0x05 278affae2bfSwdenk #define CISTPL_FUNCID_NETWORK 0x06 279affae2bfSwdenk #define CISTPL_FUNCID_AIMS 0x07 280affae2bfSwdenk #define CISTPL_FUNCID_SCSI 0x08 281affae2bfSwdenk 282affae2bfSwdenk /* 283affae2bfSwdenk * Fixed Disk FUNCE codes 284affae2bfSwdenk */ 285affae2bfSwdenk #define CISTPL_IDE_INTERFACE 0x01 286affae2bfSwdenk 287affae2bfSwdenk #define CISTPL_FUNCE_IDE_IFACE 0x01 288affae2bfSwdenk #define CISTPL_FUNCE_IDE_MASTER 0x02 289affae2bfSwdenk #define CISTPL_FUNCE_IDE_SLAVE 0x03 290affae2bfSwdenk 291affae2bfSwdenk /* First feature byte */ 292affae2bfSwdenk #define CISTPL_IDE_SILICON 0x04 293affae2bfSwdenk #define CISTPL_IDE_UNIQUE 0x08 294affae2bfSwdenk #define CISTPL_IDE_DUAL 0x10 295affae2bfSwdenk 296affae2bfSwdenk /* Second feature byte */ 297affae2bfSwdenk #define CISTPL_IDE_HAS_SLEEP 0x01 298affae2bfSwdenk #define CISTPL_IDE_HAS_STANDBY 0x02 299affae2bfSwdenk #define CISTPL_IDE_HAS_IDLE 0x04 300affae2bfSwdenk #define CISTPL_IDE_LOW_POWER 0x08 301affae2bfSwdenk #define CISTPL_IDE_REG_INHIBIT 0x10 302affae2bfSwdenk #define CISTPL_IDE_HAS_INDEX 0x20 303affae2bfSwdenk #define CISTPL_IDE_IOIS16 0x40 304affae2bfSwdenk 305affae2bfSwdenk #endif /* CFG_CMD_PCMCIA || CFG_CMD_IDE && (CONFIG_IDE_8xx_PCCARD || CONFIG_IDE_8xx_DIRECT) */ 306affae2bfSwdenk 307affae2bfSwdenk #endif /* _PCMCIA_H */ 308