1*4cf9e464SStefan Roese /* 2*4cf9e464SStefan Roese * Copyright (C) 2016 Stefan Roese <sr@denx.de> 3*4cf9e464SStefan Roese * 4*4cf9e464SStefan Roese * SPDX-License-Identifier: GPL-2.0+ 5*4cf9e464SStefan Roese */ 6*4cf9e464SStefan Roese 7*4cf9e464SStefan Roese #ifndef _NUVOTON_NCT6102D_H_ 8*4cf9e464SStefan Roese #define _NUVOTON_NCT6102D_H_ 9*4cf9e464SStefan Roese 10*4cf9e464SStefan Roese /* I/O address of Nuvoton Super IO chip */ 11*4cf9e464SStefan Roese #define NCT6102D_IO_PORT 0x4e 12*4cf9e464SStefan Roese 13*4cf9e464SStefan Roese /* Extended Function Enable Registers */ 14*4cf9e464SStefan Roese #define NCT_EFER (NCT6102D_IO_PORT + 0) 15*4cf9e464SStefan Roese /* Extended Function Index Register (same as EFER) */ 16*4cf9e464SStefan Roese #define NCT_EFIR (NCT6102D_IO_PORT + 0) 17*4cf9e464SStefan Roese /* Extended Function Data Register */ 18*4cf9e464SStefan Roese #define NCT_EFDR (NCT_EFIR + 1) 19*4cf9e464SStefan Roese 20*4cf9e464SStefan Roese #define NCT_LD_SELECT_REG 0x07 21*4cf9e464SStefan Roese 22*4cf9e464SStefan Roese /* Logical device number */ 23*4cf9e464SStefan Roese #define NCT6102D_LD_UARTA 0x02 24*4cf9e464SStefan Roese #define NCT6102D_LD_WDT 0x08 25*4cf9e464SStefan Roese 26*4cf9e464SStefan Roese #define NCT6102D_UARTA_ENABLE 0x30 27*4cf9e464SStefan Roese #define NCT6102D_WDT_TIMEOUT 0xf1 28*4cf9e464SStefan Roese 29*4cf9e464SStefan Roese #define NCT_ENTRY_KEY 0x87 30*4cf9e464SStefan Roese #define NCT_EXIT_KEY 0xaa 31*4cf9e464SStefan Roese 32*4cf9e464SStefan Roese int nct6102d_wdt_disable(void); 33*4cf9e464SStefan Roese 34*4cf9e464SStefan Roese #endif /* _NUVOTON_NCT6102D_H_ */ 35