1717b5aadSwdenk /* 2717b5aadSwdenk * NS16550 Serial Port 3a47a12beSStefan Roese * originally from linux source (arch/powerpc/boot/ns16550.h) 4200779e3SDetlev Zundel * 5200779e3SDetlev Zundel * Cleanup and unification 6200779e3SDetlev Zundel * (C) 2009 by Detlev Zundel, DENX Software Engineering GmbH 7200779e3SDetlev Zundel * 8717b5aadSwdenk * modified slightly to 96d0f6bcfSJean-Christophe PLAGNIOL-VILLARD * have addresses as offsets from CONFIG_SYS_ISA_BASE 10717b5aadSwdenk * added a few more definitions 11717b5aadSwdenk * added prototypes for ns16550.c 12717b5aadSwdenk * reduced no of com ports to 2 13717b5aadSwdenk * modifications (c) Rob Taylor, Flying Pig Systems. 2000. 14f5e0d039SHeiko Schocher * 15f5e0d039SHeiko Schocher * added support for port on 64-bit bus 16f5e0d039SHeiko Schocher * by Richard Danter (richard.danter@windriver.com), (C) 2005 Wind River Systems 17717b5aadSwdenk */ 18717b5aadSwdenk 19453c0d75SDetlev Zundel /* 20453c0d75SDetlev Zundel * Note that the following macro magic uses the fact that the compiler 21453c0d75SDetlev Zundel * will not allocate storage for arrays of size 0 22453c0d75SDetlev Zundel */ 23453c0d75SDetlev Zundel 2479df1208SDave Aldridge #include <linux/types.h> 2579df1208SDave Aldridge 26453c0d75SDetlev Zundel #if !defined(CONFIG_SYS_NS16550_REG_SIZE) || (CONFIG_SYS_NS16550_REG_SIZE == 0) 27717b5aadSwdenk #error "Please define NS16550 registers size." 2879df1208SDave Aldridge #elif defined(CONFIG_SYS_NS16550_MEM32) 2979df1208SDave Aldridge #define UART_REG(x) u32 x 30453c0d75SDetlev Zundel #elif (CONFIG_SYS_NS16550_REG_SIZE > 0) 31453c0d75SDetlev Zundel #define UART_REG(x) \ 32453c0d75SDetlev Zundel unsigned char prepad_##x[CONFIG_SYS_NS16550_REG_SIZE - 1]; \ 33453c0d75SDetlev Zundel unsigned char x; 34453c0d75SDetlev Zundel #elif (CONFIG_SYS_NS16550_REG_SIZE < 0) 35453c0d75SDetlev Zundel #define UART_REG(x) \ 36453c0d75SDetlev Zundel unsigned char x; \ 37453c0d75SDetlev Zundel unsigned char postpad_##x[-CONFIG_SYS_NS16550_REG_SIZE - 1]; 38717b5aadSwdenk #endif 39717b5aadSwdenk 40453c0d75SDetlev Zundel struct NS16550 { 41453c0d75SDetlev Zundel UART_REG(rbr); /* 0 */ 42453c0d75SDetlev Zundel UART_REG(ier); /* 1 */ 43453c0d75SDetlev Zundel UART_REG(fcr); /* 2 */ 44453c0d75SDetlev Zundel UART_REG(lcr); /* 3 */ 45453c0d75SDetlev Zundel UART_REG(mcr); /* 4 */ 46453c0d75SDetlev Zundel UART_REG(lsr); /* 5 */ 47453c0d75SDetlev Zundel UART_REG(msr); /* 6 */ 48453c0d75SDetlev Zundel UART_REG(spr); /* 7 */ 4999b603e7SMikhail Kshevetskiy #ifdef CONFIG_SOC_DA8XX 5099b603e7SMikhail Kshevetskiy UART_REG(reg8); /* 8 */ 5199b603e7SMikhail Kshevetskiy UART_REG(reg9); /* 9 */ 5299b603e7SMikhail Kshevetskiy UART_REG(revid1); /* A */ 5399b603e7SMikhail Kshevetskiy UART_REG(revid2); /* B */ 5499b603e7SMikhail Kshevetskiy UART_REG(pwr_mgmt); /* C */ 5599b603e7SMikhail Kshevetskiy UART_REG(mdr1); /* D */ 5699b603e7SMikhail Kshevetskiy #else 57453c0d75SDetlev Zundel UART_REG(mdr1); /* 8 */ 58453c0d75SDetlev Zundel UART_REG(reg9); /* 9 */ 59453c0d75SDetlev Zundel UART_REG(regA); /* A */ 60453c0d75SDetlev Zundel UART_REG(regB); /* B */ 61453c0d75SDetlev Zundel UART_REG(regC); /* C */ 62453c0d75SDetlev Zundel UART_REG(regD); /* D */ 63453c0d75SDetlev Zundel UART_REG(regE); /* E */ 64453c0d75SDetlev Zundel UART_REG(uasr); /* F */ 65453c0d75SDetlev Zundel UART_REG(scr); /* 10*/ 66453c0d75SDetlev Zundel UART_REG(ssr); /* 11*/ 6799b603e7SMikhail Kshevetskiy #endif 68453c0d75SDetlev Zundel }; 69453c0d75SDetlev Zundel 70717b5aadSwdenk #define thr rbr 71717b5aadSwdenk #define iir fcr 72717b5aadSwdenk #define dll rbr 73717b5aadSwdenk #define dlm ier 74717b5aadSwdenk 75f8df9d0dSSimon Glass typedef struct NS16550 *NS16550_t; 76717b5aadSwdenk 77200779e3SDetlev Zundel /* 78200779e3SDetlev Zundel * These are the definitions for the FIFO Control Register 79200779e3SDetlev Zundel */ 80200779e3SDetlev Zundel #define UART_FCR_FIFO_EN 0x01 /* Fifo enable */ 81200779e3SDetlev Zundel #define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */ 82200779e3SDetlev Zundel #define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */ 83200779e3SDetlev Zundel #define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */ 84200779e3SDetlev Zundel #define UART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */ 85200779e3SDetlev Zundel #define UART_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */ 86200779e3SDetlev Zundel #define UART_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */ 87200779e3SDetlev Zundel #define UART_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */ 88200779e3SDetlev Zundel #define UART_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */ 89717b5aadSwdenk 90200779e3SDetlev Zundel #define UART_FCR_RXSR 0x02 /* Receiver soft reset */ 91200779e3SDetlev Zundel #define UART_FCR_TXSR 0x04 /* Transmitter soft reset */ 92717b5aadSwdenk 93200779e3SDetlev Zundel /* 94200779e3SDetlev Zundel * These are the definitions for the Modem Control Register 95200779e3SDetlev Zundel */ 96200779e3SDetlev Zundel #define UART_MCR_DTR 0x01 /* DTR */ 97200779e3SDetlev Zundel #define UART_MCR_RTS 0x02 /* RTS */ 98200779e3SDetlev Zundel #define UART_MCR_OUT1 0x04 /* Out 1 */ 99200779e3SDetlev Zundel #define UART_MCR_OUT2 0x08 /* Out 2 */ 100200779e3SDetlev Zundel #define UART_MCR_LOOP 0x10 /* Enable loopback test mode */ 101d57dee57SKaricheri, Muralidharan #define UART_MCR_AFE 0x20 /* Enable auto-RTS/CTS */ 102717b5aadSwdenk 103200779e3SDetlev Zundel #define UART_MCR_DMA_EN 0x04 104200779e3SDetlev Zundel #define UART_MCR_TX_DFR 0x08 105717b5aadSwdenk 106200779e3SDetlev Zundel /* 107200779e3SDetlev Zundel * These are the definitions for the Line Control Register 108200779e3SDetlev Zundel * 109200779e3SDetlev Zundel * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting 110200779e3SDetlev Zundel * UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits. 111200779e3SDetlev Zundel */ 112200779e3SDetlev Zundel #define UART_LCR_WLS_MSK 0x03 /* character length select mask */ 113200779e3SDetlev Zundel #define UART_LCR_WLS_5 0x00 /* 5 bit character length */ 114200779e3SDetlev Zundel #define UART_LCR_WLS_6 0x01 /* 6 bit character length */ 115200779e3SDetlev Zundel #define UART_LCR_WLS_7 0x02 /* 7 bit character length */ 116200779e3SDetlev Zundel #define UART_LCR_WLS_8 0x03 /* 8 bit character length */ 117f8df9d0dSSimon Glass #define UART_LCR_STB 0x04 /* # stop Bits, off=1, on=1.5 or 2) */ 118200779e3SDetlev Zundel #define UART_LCR_PEN 0x08 /* Parity eneble */ 119200779e3SDetlev Zundel #define UART_LCR_EPS 0x10 /* Even Parity Select */ 120200779e3SDetlev Zundel #define UART_LCR_STKP 0x20 /* Stick Parity */ 121200779e3SDetlev Zundel #define UART_LCR_SBRK 0x40 /* Set Break */ 122200779e3SDetlev Zundel #define UART_LCR_BKSE 0x80 /* Bank select enable */ 123200779e3SDetlev Zundel #define UART_LCR_DLAB 0x80 /* Divisor latch access bit */ 124200779e3SDetlev Zundel 125200779e3SDetlev Zundel /* 126200779e3SDetlev Zundel * These are the definitions for the Line Status Register 127200779e3SDetlev Zundel */ 128200779e3SDetlev Zundel #define UART_LSR_DR 0x01 /* Data ready */ 129200779e3SDetlev Zundel #define UART_LSR_OE 0x02 /* Overrun */ 130200779e3SDetlev Zundel #define UART_LSR_PE 0x04 /* Parity error */ 131200779e3SDetlev Zundel #define UART_LSR_FE 0x08 /* Framing error */ 132200779e3SDetlev Zundel #define UART_LSR_BI 0x10 /* Break */ 133200779e3SDetlev Zundel #define UART_LSR_THRE 0x20 /* Xmit holding register empty */ 134200779e3SDetlev Zundel #define UART_LSR_TEMT 0x40 /* Xmitter empty */ 135200779e3SDetlev Zundel #define UART_LSR_ERR 0x80 /* Error */ 136200779e3SDetlev Zundel 137200779e3SDetlev Zundel #define UART_MSR_DCD 0x80 /* Data Carrier Detect */ 138200779e3SDetlev Zundel #define UART_MSR_RI 0x40 /* Ring Indicator */ 139200779e3SDetlev Zundel #define UART_MSR_DSR 0x20 /* Data Set Ready */ 140200779e3SDetlev Zundel #define UART_MSR_CTS 0x10 /* Clear to Send */ 141200779e3SDetlev Zundel #define UART_MSR_DDCD 0x08 /* Delta DCD */ 142200779e3SDetlev Zundel #define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */ 143200779e3SDetlev Zundel #define UART_MSR_DDSR 0x02 /* Delta DSR */ 144200779e3SDetlev Zundel #define UART_MSR_DCTS 0x01 /* Delta CTS */ 145200779e3SDetlev Zundel 146200779e3SDetlev Zundel /* 147200779e3SDetlev Zundel * These are the definitions for the Interrupt Identification Register 148200779e3SDetlev Zundel */ 149200779e3SDetlev Zundel #define UART_IIR_NO_INT 0x01 /* No interrupts pending */ 150200779e3SDetlev Zundel #define UART_IIR_ID 0x06 /* Mask for the interrupt ID */ 151200779e3SDetlev Zundel 152200779e3SDetlev Zundel #define UART_IIR_MSI 0x00 /* Modem status interrupt */ 153200779e3SDetlev Zundel #define UART_IIR_THRI 0x02 /* Transmitter holding register empty */ 154200779e3SDetlev Zundel #define UART_IIR_RDI 0x04 /* Receiver data interrupt */ 155200779e3SDetlev Zundel #define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */ 156200779e3SDetlev Zundel 157200779e3SDetlev Zundel /* 158200779e3SDetlev Zundel * These are the definitions for the Interrupt Enable Register 159200779e3SDetlev Zundel */ 160200779e3SDetlev Zundel #define UART_IER_MSI 0x08 /* Enable Modem status interrupt */ 161200779e3SDetlev Zundel #define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */ 162200779e3SDetlev Zundel #define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */ 163200779e3SDetlev Zundel #define UART_IER_RDI 0x01 /* Enable receiver data interrupt */ 164200779e3SDetlev Zundel 165717b5aadSwdenk /* useful defaults for LCR */ 166200779e3SDetlev Zundel #define UART_LCR_8N1 0x03 167717b5aadSwdenk 168717b5aadSwdenk void NS16550_init(NS16550_t com_port, int baud_divisor); 169717b5aadSwdenk void NS16550_putc(NS16550_t com_port, char c); 170717b5aadSwdenk char NS16550_getc(NS16550_t com_port); 171717b5aadSwdenk int NS16550_tstc(NS16550_t com_port); 172717b5aadSwdenk void NS16550_reinit(NS16550_t com_port, int baud_divisor); 173*fa54eb12SSimon Glass 174*fa54eb12SSimon Glass /** 175*fa54eb12SSimon Glass * ns16550_calc_divisor() - calculate the divisor given clock and baud rate 176*fa54eb12SSimon Glass * 177*fa54eb12SSimon Glass * Given the UART input clock and required baudrate, calculate the divisor 178*fa54eb12SSimon Glass * that should be used. 179*fa54eb12SSimon Glass * 180*fa54eb12SSimon Glass * @port: UART port 181*fa54eb12SSimon Glass * @clock: UART input clock speed in Hz 182*fa54eb12SSimon Glass * @baudrate: Required baud rate 183*fa54eb12SSimon Glass * @return baud rate divisor that should be used 184*fa54eb12SSimon Glass */ 185*fa54eb12SSimon Glass int ns16550_calc_divisor(NS16550_t port, int clock, int baudrate); 186