1e5f495d1SPrafulla Wadaskar /* 2e5f495d1SPrafulla Wadaskar * (C) Copyright 2010 3e5f495d1SPrafulla Wadaskar * Marvell Semiconductor <www.marvell.com> 4e5f495d1SPrafulla Wadaskar * Written-by: Prafulla Wadaskar <prafulla@marvell.com> 5e5f495d1SPrafulla Wadaskar * 61a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 7e5f495d1SPrafulla Wadaskar */ 8e5f495d1SPrafulla Wadaskar 9e5f495d1SPrafulla Wadaskar #ifndef __MVMFP_H 10e5f495d1SPrafulla Wadaskar #define __MVMFP_H 11e5f495d1SPrafulla Wadaskar 12e5f495d1SPrafulla Wadaskar /* 13e5f495d1SPrafulla Wadaskar * Header file for MultiFunctionPin (MFP) Configururation framework 14e5f495d1SPrafulla Wadaskar * 15e5f495d1SPrafulla Wadaskar * Processors Supported: 16e5f495d1SPrafulla Wadaskar * 1. Marvell ARMADA100 Processors 17e5f495d1SPrafulla Wadaskar * 18e5f495d1SPrafulla Wadaskar * processor to be supported should be added here 19e5f495d1SPrafulla Wadaskar */ 20e5f495d1SPrafulla Wadaskar 21e5f495d1SPrafulla Wadaskar /* 22e5f495d1SPrafulla Wadaskar * MFP configuration is represented by a 32-bit unsigned integer 23e5f495d1SPrafulla Wadaskar */ 24*ee4303cfSXiang Wang #ifdef CONFIG_MVMFP_V2 25*ee4303cfSXiang Wang #define MFP(_off, _pull, _drv, _slp, _edge, _sleep, _afn) ( \ 26*ee4303cfSXiang Wang /* bits 31..16 - MFP Register Offset */ (((_off) & 0xffff) << 16) | \ 27*ee4303cfSXiang Wang /* bits 15..13 - Run Mode Pull State */ (((_pull) & 0x7) << 13) | \ 28*ee4303cfSXiang Wang /* bit 12..11 - Driver Strength */ (((_drv) & 0x3) << 11) | \ 29*ee4303cfSXiang Wang /* bits 10 - pad driver */ (((_slp) & 0x1) << 10) | \ 30*ee4303cfSXiang Wang /* bit 09..07 - sleep mode */ (((_sleep) & 0xe) << 6) | \ 31*ee4303cfSXiang Wang /* bits 06..04 - Edge Detection */ (((_edge) & 0x7) << 4) | \ 32*ee4303cfSXiang Wang /* bits 03 - sleep mode */ (((_sleep) & 0x1) << 3) | \ 33*ee4303cfSXiang Wang /* bits 02..00 - Alt-fun select */ ((_afn) & 0x7)) 34*ee4303cfSXiang Wang #else 35*ee4303cfSXiang Wang #define MFP(_off, _pull, _drv, _slp, _edge, _sleep, _afn) ( \ 36e5f495d1SPrafulla Wadaskar /* bits 31..16 - MFP Register Offset */ (((_off) & 0xffff) << 16) | \ 37e5f495d1SPrafulla Wadaskar /* bits 15..13 - Run Mode Pull State */ (((_pull) & 0x7) << 13) | \ 38e5f495d1SPrafulla Wadaskar /* bit 12 - Unused */ \ 39e5f495d1SPrafulla Wadaskar /* bits 11..10 - Driver Strength */ (((_drv) & 0x3) << 10) | \ 40*ee4303cfSXiang Wang /* bit 09..07 - sleep mode */ (((_sleep) & 0xe) << 6) | \ 41e5f495d1SPrafulla Wadaskar /* bits 06..04 - Edge Detection */ (((_edge) & 0x7) << 4) | \ 42*ee4303cfSXiang Wang /* bits 03 - sleep mode */ (((_sleep) & 0x1) << 3) | \ 43*ee4303cfSXiang Wang /* bits 02..00 - Alt-fun select */ ((_afn) & 0x7)) 44*ee4303cfSXiang Wang #endif 45e5f495d1SPrafulla Wadaskar 46e5f495d1SPrafulla Wadaskar /* 47e5f495d1SPrafulla Wadaskar * to facilitate the definition, the following macros are provided 48e5f495d1SPrafulla Wadaskar * 49e5f495d1SPrafulla Wadaskar * offset, pull,pF, drv,dF, edge,eF ,afn,aF 50e5f495d1SPrafulla Wadaskar */ 51*ee4303cfSXiang Wang #define MFP_OFFSET_MASK MFP(0xffff, 0, 0, 0, 0, 0, 0) 52*ee4303cfSXiang Wang #define MFP_REG(x) MFP(x, 0, 0, 0, 0, 0, 0) 53e5f495d1SPrafulla Wadaskar #define MFP_REG_GET_OFFSET(x) ((x & MFP_OFFSET_MASK) >> 16) 54e5f495d1SPrafulla Wadaskar 55*ee4303cfSXiang Wang #define MFP_AF0 MFP(0x0000, 0, 0, 0, 0, 0, 0) 56*ee4303cfSXiang Wang #define MFP_AF1 MFP(0x0000, 0, 0, 0, 0, 0, 1) 57*ee4303cfSXiang Wang #define MFP_AF2 MFP(0x0000, 0, 0, 0, 0, 0, 2) 58*ee4303cfSXiang Wang #define MFP_AF3 MFP(0x0000, 0, 0, 0, 0, 0, 3) 59*ee4303cfSXiang Wang #define MFP_AF4 MFP(0x0000, 0, 0, 0, 0, 0, 4) 60*ee4303cfSXiang Wang #define MFP_AF5 MFP(0x0000, 0, 0, 0, 0, 0, 5) 61*ee4303cfSXiang Wang #define MFP_AF6 MFP(0x0000, 0, 0, 0, 0, 0, 6) 62*ee4303cfSXiang Wang #define MFP_AF7 MFP(0x0000, 0, 0, 0, 0, 0, 7) 63*ee4303cfSXiang Wang #define MFP_AF_MASK MFP(0x0000, 0, 0, 0, 0, 0, 7) 64e5f495d1SPrafulla Wadaskar 65*ee4303cfSXiang Wang #define MFP_SLEEP_CTRL2 MFP(0x0000, 0, 0, 0, 0, 1, 0) 66*ee4303cfSXiang Wang #define MFP_SLEEP_DIR MFP(0x0000, 0, 0, 0, 0, 2, 0) 67*ee4303cfSXiang Wang #define MFP_SLEEP_DATA MFP(0x0000, 0, 0, 0, 0, 4, 0) 68*ee4303cfSXiang Wang #define MFP_SLEEP_CTRL MFP(0x0000, 0, 0, 0, 0, 8, 0) 69*ee4303cfSXiang Wang #define MFP_SLEEP_MASK MFP(0x0000, 0, 0, 0, 0, 0xf, 0) 70e5f495d1SPrafulla Wadaskar 71*ee4303cfSXiang Wang #define MFP_LPM_EDGE_NONE MFP(0x0000, 0, 0, 0, 4, 0, 0) 72*ee4303cfSXiang Wang #define MFP_LPM_EDGE_RISE MFP(0x0000, 0, 0, 0, 1, 0, 0) 73*ee4303cfSXiang Wang #define MFP_LPM_EDGE_FALL MFP(0x0000, 0, 0, 0, 2, 0, 0) 74*ee4303cfSXiang Wang #define MFP_LPM_EDGE_BOTH MFP(0x0000, 0, 0, 0, 3, 0, 0) 75*ee4303cfSXiang Wang #define MFP_LPM_EDGE_MASK MFP(0x0000, 0, 0, 0, 7, 0, 0) 76e5f495d1SPrafulla Wadaskar 77*ee4303cfSXiang Wang #define MFP_SLP_DI MFP(0x0000, 0, 0, 1, 0, 0, 0) 78e5f495d1SPrafulla Wadaskar 79*ee4303cfSXiang Wang #define MFP_DRIVE_VERY_SLOW MFP(0x0000, 0, 0, 0, 0, 0, 0) 80*ee4303cfSXiang Wang #define MFP_DRIVE_SLOW MFP(0x0000, 0, 1, 0, 0, 0, 0) 81*ee4303cfSXiang Wang #define MFP_DRIVE_MEDIUM MFP(0x0000, 0, 2, 0, 0, 0, 0) 82*ee4303cfSXiang Wang #define MFP_DRIVE_FAST MFP(0x0000, 0, 3, 0, 0, 0, 0) 83*ee4303cfSXiang Wang #define MFP_DRIVE_MASK MFP(0x0000, 0, 3, 0, 0, 0, 0) 84e5f495d1SPrafulla Wadaskar 85*ee4303cfSXiang Wang #define MFP_PULL_NONE MFP(0x0000, 0, 0, 0, 0, 0, 0) 86*ee4303cfSXiang Wang #define MFP_PULL_LOW MFP(0x0000, 5, 0, 0, 0, 0, 0) 87*ee4303cfSXiang Wang #define MFP_PULL_HIGH MFP(0x0000, 6, 0, 0, 0, 0, 0) 88*ee4303cfSXiang Wang #define MFP_PULL_BOTH MFP(0x0000, 7, 0, 0, 0, 0, 0) 89*ee4303cfSXiang Wang #define MFP_PULL_FLOAT MFP(0x0000, 4, 0, 0, 0, 0, 0) 90*ee4303cfSXiang Wang #define MFP_PULL_MASK MFP(0x0000, 7, 0, 0, 0, 0, 0) 91*ee4303cfSXiang Wang 92*ee4303cfSXiang Wang #define MFP_VALUE_MASK (MFP_PULL_MASK | MFP_DRIVE_MASK | MFP_SLP_DI \ 93*ee4303cfSXiang Wang | MFP_LPM_EDGE_MASK | MFP_SLEEP_MASK \ 94*ee4303cfSXiang Wang | MFP_AF_MASK) 95e5f495d1SPrafulla Wadaskar #define MFP_EOC 0xffffffff /* indicates end-of-conf */ 96e5f495d1SPrafulla Wadaskar 97e5f495d1SPrafulla Wadaskar /* Functions */ 98e5f495d1SPrafulla Wadaskar void mfp_config(u32 *mfp_cfgs); 99e5f495d1SPrafulla Wadaskar 100e5f495d1SPrafulla Wadaskar #endif /* __MVMFP_H */ 101