10669d4d3Swdenk /* 20669d4d3Swdenk * (C) Copyright 2000 30669d4d3Swdenk * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 40669d4d3Swdenk * 50669d4d3Swdenk * See file CREDITS for list of people who contributed to this 60669d4d3Swdenk * project. 70669d4d3Swdenk * 80669d4d3Swdenk * This program is free software; you can redistribute it and/or 90669d4d3Swdenk * modify it under the terms of the GNU General Public License as 100669d4d3Swdenk * published by the Free Software Foundation; either version 2 of 110669d4d3Swdenk * the License, or (at your option) any later version. 120669d4d3Swdenk * 130669d4d3Swdenk * This program is distributed in the hope that it will be useful, 140669d4d3Swdenk * but WITHOUT ANY WARRANTY; without even the implied warranty of 150669d4d3Swdenk * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 160669d4d3Swdenk * GNU General Public License for more details. 170669d4d3Swdenk * 180669d4d3Swdenk * You should have received a copy of the GNU General Public License 190669d4d3Swdenk * along with this program; if not, write to the Free Software 200669d4d3Swdenk * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 210669d4d3Swdenk * MA 02111-1307 USA 220669d4d3Swdenk */ 230669d4d3Swdenk 240669d4d3Swdenk /* 250669d4d3Swdenk * mpc8xx.h 260669d4d3Swdenk * 270669d4d3Swdenk * MPC8xx specific definitions 280669d4d3Swdenk */ 290669d4d3Swdenk 300669d4d3Swdenk #ifndef __MPCXX_H__ 310669d4d3Swdenk #define __MPCXX_H__ 320669d4d3Swdenk 330669d4d3Swdenk 340669d4d3Swdenk /*----------------------------------------------------------------------- 350669d4d3Swdenk * Exception offsets (PowerPC standard) 360669d4d3Swdenk */ 370669d4d3Swdenk #define EXC_OFF_SYS_RESET 0x0100 /* System reset */ 380669d4d3Swdenk 390669d4d3Swdenk 400669d4d3Swdenk /*----------------------------------------------------------------------- 410669d4d3Swdenk * SYPCR - System Protection Control Register 11-9 420669d4d3Swdenk */ 43*682011ffSwdenk #define SYPCR_SWTC 0xFFFF0000 /* Software Watchdog Timer Count */ 44*682011ffSwdenk #define SYPCR_BMT 0x0000FF00 /* Bus Monitor Timing */ 450669d4d3Swdenk #define SYPCR_BME 0x00000080 /* Bus Monitor Enable */ 460669d4d3Swdenk #define SYPCR_SWF 0x00000008 /* Software Watchdog Freeze */ 470669d4d3Swdenk #define SYPCR_SWE 0x00000004 /* Software Watchdog Enable */ 480669d4d3Swdenk #define SYPCR_SWRI 0x00000002 /* Software Watchdog Reset/Int Select */ 490669d4d3Swdenk #define SYPCR_SWP 0x00000001 /* Software Watchdog Prescale */ 500669d4d3Swdenk 510669d4d3Swdenk /*----------------------------------------------------------------------- 520669d4d3Swdenk * SIUMCR - SIU Module Configuration Register 11-6 530669d4d3Swdenk */ 540669d4d3Swdenk #define SIUMCR_EARB 0x80000000 /* External Arbitration */ 550669d4d3Swdenk #define SIUMCR_EARP0 0x00000000 /* External Arbi. Request priority 0 */ 560669d4d3Swdenk #define SIUMCR_EARP1 0x10000000 /* External Arbi. Request priority 1 */ 570669d4d3Swdenk #define SIUMCR_EARP2 0x20000000 /* External Arbi. Request priority 2 */ 580669d4d3Swdenk #define SIUMCR_EARP3 0x30000000 /* External Arbi. Request priority 3 */ 590669d4d3Swdenk #define SIUMCR_EARP4 0x40000000 /* External Arbi. Request priority 4 */ 600669d4d3Swdenk #define SIUMCR_EARP5 0x50000000 /* External Arbi. Request priority 5 */ 610669d4d3Swdenk #define SIUMCR_EARP6 0x60000000 /* External Arbi. Request priority 6 */ 620669d4d3Swdenk #define SIUMCR_EARP7 0x70000000 /* External Arbi. Request priority 7 */ 630669d4d3Swdenk #define SIUMCR_DSHW 0x00800000 /* Data Showcycles */ 640669d4d3Swdenk #define SIUMCR_DBGC00 0x00000000 /* Debug pins configuration */ 650669d4d3Swdenk #define SIUMCR_DBGC01 0x00200000 /* - " - */ 660669d4d3Swdenk #define SIUMCR_DBGC10 0x00400000 /* - " - */ 670669d4d3Swdenk #define SIUMCR_DBGC11 0x00600000 /* - " - */ 680669d4d3Swdenk #define SIUMCR_DBPC00 0x00000000 /* Debug Port pins Config. */ 690669d4d3Swdenk #define SIUMCR_DBPC01 0x00080000 /* - " - */ 700669d4d3Swdenk #define SIUMCR_DBPC10 0x00100000 /* - " - */ 710669d4d3Swdenk #define SIUMCR_DBPC11 0x00180000 /* - " - */ 720669d4d3Swdenk #define SIUMCR_FRC 0x00020000 /* FRZ pin Configuration */ 730669d4d3Swdenk #define SIUMCR_DLK 0x00010000 /* Debug Register Lock */ 740669d4d3Swdenk #define SIUMCR_PNCS 0x00008000 /* Parity Non-mem Crtl reg */ 750669d4d3Swdenk #define SIUMCR_OPAR 0x00004000 /* Odd Parity */ 760669d4d3Swdenk #define SIUMCR_DPC 0x00002000 /* Data Parity pins Config. */ 770669d4d3Swdenk #define SIUMCR_MPRE 0x00001000 /* Multi CPU Reserva. Enable */ 780669d4d3Swdenk #define SIUMCR_MLRC00 0x00000000 /* Multi Level Reserva. Ctrl */ 790669d4d3Swdenk #define SIUMCR_MLRC01 0x00000400 /* - " - */ 800669d4d3Swdenk #define SIUMCR_MLRC10 0x00000800 /* - " - */ 81*682011ffSwdenk #define SIUMCR_MLRC11 0x00000C00 /* - " - */ 820669d4d3Swdenk #define SIUMCR_AEME 0x00000200 /* Asynchro External Master */ 830669d4d3Swdenk #define SIUMCR_SEME 0x00000100 /* Synchro External Master */ 840669d4d3Swdenk #define SIUMCR_BSC 0x00000080 /* Byte Select Configuration */ 850669d4d3Swdenk #define SIUMCR_GB5E 0x00000040 /* GPL_B(5) Enable */ 860669d4d3Swdenk #define SIUMCR_B2DD 0x00000020 /* Bank 2 Double Drive */ 870669d4d3Swdenk #define SIUMCR_B3DD 0x00000010 /* Bank 3 Double Drive */ 880669d4d3Swdenk 890669d4d3Swdenk /*----------------------------------------------------------------------- 900669d4d3Swdenk * TBSCR - Time Base Status and Control Register 11-26 910669d4d3Swdenk */ 920669d4d3Swdenk #define TBSCR_TBIRQ7 0x8000 /* Time Base Interrupt Request 7 */ 930669d4d3Swdenk #define TBSCR_TBIRQ6 0x4000 /* Time Base Interrupt Request 6 */ 940669d4d3Swdenk #define TBSCR_TBIRQ5 0x2000 /* Time Base Interrupt Request 5 */ 950669d4d3Swdenk #define TBSCR_TBIRQ4 0x1000 /* Time Base Interrupt Request 4 */ 960669d4d3Swdenk #define TBSCR_TBIRQ3 0x0800 /* Time Base Interrupt Request 3 */ 970669d4d3Swdenk #define TBSCR_TBIRQ2 0x0400 /* Time Base Interrupt Request 2 */ 980669d4d3Swdenk #define TBSCR_TBIRQ1 0x0200 /* Time Base Interrupt Request 1 */ 990669d4d3Swdenk #define TBSCR_TBIRQ0 0x0100 /* Time Base Interrupt Request 0 */ 1000669d4d3Swdenk #if 0 /* already in asm/8xx_immap.h */ 1010669d4d3Swdenk #define TBSCR_REFA 0x0080 /* Reference Interrupt Status A */ 1020669d4d3Swdenk #define TBSCR_REFB 0x0040 /* Reference Interrupt Status B */ 1030669d4d3Swdenk #define TBSCR_REFAE 0x0008 /* Second Interrupt Enable A */ 1040669d4d3Swdenk #define TBSCR_REFBE 0x0004 /* Second Interrupt Enable B */ 1050669d4d3Swdenk #define TBSCR_TBF 0x0002 /* Time Base Freeze */ 1060669d4d3Swdenk #define TBSCR_TBE 0x0001 /* Time Base Enable */ 1070669d4d3Swdenk #endif 1080669d4d3Swdenk 1090669d4d3Swdenk /*----------------------------------------------------------------------- 1100669d4d3Swdenk * PISCR - Periodic Interrupt Status and Control Register 11-31 1110669d4d3Swdenk */ 1120669d4d3Swdenk #undef PISCR_PIRQ /* TBD */ 1130669d4d3Swdenk #define PISCR_PITF 0x0002 /* Periodic Interrupt Timer Freeze */ 1140669d4d3Swdenk #if 0 /* already in asm/8xx_immap.h */ 1150669d4d3Swdenk #define PISCR_PS 0x0080 /* Periodic interrupt Status */ 1160669d4d3Swdenk #define PISCR_PIE 0x0004 /* Periodic Interrupt Enable */ 1170669d4d3Swdenk #define PISCR_PTE 0x0001 /* Periodic Timer Enable */ 1180669d4d3Swdenk #endif 1190669d4d3Swdenk 1200669d4d3Swdenk /*----------------------------------------------------------------------- 1210669d4d3Swdenk * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 1220669d4d3Swdenk */ 123*682011ffSwdenk #define PLPRCR_MF_MSK 0xFFF00000 /* Multiplication factor bits */ 1240669d4d3Swdenk #define PLPRCR_MF_SHIFT 0x00000014 /* Multiplication factor shift value */ 1250669d4d3Swdenk #define PLPRCR_SPLSS 0x00008000 /* SPLL Lock Status Sticky bit */ 1260669d4d3Swdenk #define PLPRCR_TEXPS 0x00004000 /* TEXP Status */ 1270669d4d3Swdenk #define PLPRCR_TMIST 0x00001000 /* Timers Interrupt Status */ 1280669d4d3Swdenk #define PLPRCR_CSRC 0x00000400 /* Clock Source */ 1290669d4d3Swdenk #define PLPRCR_LPM_MSK 0x00000300 /* Low Power Mode mask */ 1300669d4d3Swdenk #define PLPRCR_LPM_NORMAL 0x00000000 /* normal power management mode */ 1310669d4d3Swdenk #define PLPRCR_LPM_DOZE 0x00000100 /* doze power management mode */ 1320669d4d3Swdenk #define PLPRCR_LPM_SLEEP 0x00000200 /* sleep power management mode */ 1330669d4d3Swdenk #define PLPRCR_LPM_DEEP_SLEEP 0x00000300 /* deep sleep power mgt mode */ 1340669d4d3Swdenk #define PLPRCR_LPM_DOWN 0x00000300 /* down power management mode */ 1350669d4d3Swdenk #define PLPRCR_CSR 0x00000080 /* CheskStop Reset value */ 1360669d4d3Swdenk #define PLPRCR_LOLRE 0x00000040 /* Loss Of Lock Reset Enable */ 1370669d4d3Swdenk #define PLPRCR_FIOPD 0x00000020 /* Force I/O Pull Down */ 1380669d4d3Swdenk 1390669d4d3Swdenk /*----------------------------------------------------------------------- 1400669d4d3Swdenk * SCCR - System Clock and reset Control Register 15-27 1410669d4d3Swdenk */ 1420669d4d3Swdenk #define SCCR_COM00 0x00000000 /* full strength CLKOUT output buffer */ 1430669d4d3Swdenk #define SCCR_COM01 0x20000000 /* half strength CLKOUT output buffer */ 1440669d4d3Swdenk #define SCCR_COM10 0x40000000 /* reserved */ 1450669d4d3Swdenk #define SCCR_COM11 0x60000000 /* CLKOUT output buffer disabled */ 1460669d4d3Swdenk #define SCCR_TBS 0x02000000 /* Time Base Source */ 1470669d4d3Swdenk #define SCCR_RTDIV 0x01000000 /* RTC Clock Divide */ 1480669d4d3Swdenk #define SCCR_RTSEL 0x00800000 /* RTC circuit input source select */ 1490669d4d3Swdenk #define SCCR_CRQEN 0x00400000 /* CPM Request Enable */ 1500669d4d3Swdenk #define SCCR_PRQEN 0x00200000 /* Power Management Request Enable */ 1510669d4d3Swdenk #define SCCR_EBDF00 0x00000000 /* CLKOUT is GCLK2 / 1 (normal op.) */ 1520669d4d3Swdenk #define SCCR_EBDF01 0x00020000 /* CLKOUT is GCLK2 / 2 */ 1530669d4d3Swdenk #define SCCR_EBDF10 0x00040000 /* reserved */ 1540669d4d3Swdenk #define SCCR_EBDF11 0x00060000 /* reserved */ 1550669d4d3Swdenk #define SCCR_DFSYNC00 0x00000000 /* SyncCLK division by 1 (normal op.) */ 1560669d4d3Swdenk #define SCCR_DFSYNC01 0x00002000 /* SyncCLK division by 4 */ 1570669d4d3Swdenk #define SCCR_DFSYNC10 0x00004000 /* SyncCLK division by 16 */ 1580669d4d3Swdenk #define SCCR_DFSYNC11 0x00006000 /* SyncCLK division by 64 */ 1590669d4d3Swdenk #define SCCR_DFBRG00 0x00000000 /* BRGCLK division by 1 (normal op.) */ 1600669d4d3Swdenk #define SCCR_DFBRG01 0x00000800 /* BRGCLK division by 4 */ 1610669d4d3Swdenk #define SCCR_DFBRG10 0x00001000 /* BRGCLK division by 16 */ 1620669d4d3Swdenk #define SCCR_DFBRG11 0x00001800 /* BRGCLK division by 64 */ 1630669d4d3Swdenk #define SCCR_DFNL000 0x00000000 /* Division by 2 (default = minimum) */ 1640669d4d3Swdenk #define SCCR_DFNL111 0x00000700 /* Division by 256 (maximum) */ 1650669d4d3Swdenk #define SCCR_DFNH000 0x00000000 /* Division by 1 (default = minimum) */ 1660669d4d3Swdenk #define SCCR_DFNH110 0x000000D0 /* Division by 64 (maximum) */ 1670669d4d3Swdenk #define SCCR_DFNH111 0x000000E0 /* reserved */ 1680669d4d3Swdenk #define SCCR_DFLCD000 0x00000000 /* Division by 1 (default = minimum) */ 1690669d4d3Swdenk #define SCCR_DFLCD001 0x00000004 /* Division by 2 */ 1700669d4d3Swdenk #define SCCR_DFLCD010 0x00000008 /* Division by 4 */ 1710669d4d3Swdenk #define SCCR_DFLCD011 0x0000000C /* Division by 8 */ 1720669d4d3Swdenk #define SCCR_DFLCD100 0x00000010 /* Division by 16 */ 1730669d4d3Swdenk #define SCCR_DFLCD101 0x00000014 /* Division by 32 */ 1740669d4d3Swdenk #define SCCR_DFLCD110 0x00000018 /* Division by 64 (maximum) */ 1750669d4d3Swdenk #define SCCR_DFLCD111 0x0000001C /* reserved */ 1760669d4d3Swdenk #define SCCR_DFALCD00 0x00000000 /* Division by 1 (default = minimum) */ 1770669d4d3Swdenk #define SCCR_DFALCD01 0x00000001 /* Division by 3 */ 1780669d4d3Swdenk #define SCCR_DFALCD10 0x00000002 /* Division by 5 */ 1790669d4d3Swdenk #define SCCR_DFALCD11 0x00000003 /* Division by 7 (maximum) */ 1800669d4d3Swdenk 1810669d4d3Swdenk 1820669d4d3Swdenk /*----------------------------------------------------------------------- 1830669d4d3Swdenk * BR - Memory Controler: Base Register 16-9 1840669d4d3Swdenk */ 185*682011ffSwdenk #define BR_BA_MSK 0xFFFF8000 /* Base Address Mask */ 1860669d4d3Swdenk #define BR_AT_MSK 0x00007000 /* Address Type Mask */ 187*682011ffSwdenk #define BR_PS_MSK 0x00000C00 /* Port Size Mask */ 1880669d4d3Swdenk #define BR_PS_32 0x00000000 /* 32 bit port size */ 1890669d4d3Swdenk #define BR_PS_16 0x00000800 /* 16 bit port size */ 1900669d4d3Swdenk #define BR_PS_8 0x00000400 /* 8 bit port size */ 1910669d4d3Swdenk #define BR_PARE 0x00000200 /* Parity Enable */ 1920669d4d3Swdenk #define BR_WP 0x00000100 /* Write Protect */ 193*682011ffSwdenk #define BR_MS_MSK 0x000000C0 /* Machine Select Mask */ 1940669d4d3Swdenk #define BR_MS_GPCM 0x00000000 /* G.P.C.M. Machine Select */ 1950669d4d3Swdenk #define BR_MS_UPMA 0x00000080 /* U.P.M.A Machine Select */ 196*682011ffSwdenk #define BR_MS_UPMB 0x000000C0 /* U.P.M.B Machine Select */ 1970669d4d3Swdenk #define BR_V 0x00000001 /* Bank Valid */ 1980669d4d3Swdenk 1990669d4d3Swdenk /*----------------------------------------------------------------------- 2000669d4d3Swdenk * OR - Memory Controler: Option Register 16-11 2010669d4d3Swdenk */ 202*682011ffSwdenk #define OR_AM_MSK 0xFFFF8000 /* Address Mask Mask */ 2030669d4d3Swdenk #define OR_ATM_MSK 0x00007000 /* Address Type Mask Mask */ 2040669d4d3Swdenk #define OR_CSNT_SAM 0x00000800 /* Chip Select Negation Time/ Start */ 2050669d4d3Swdenk /* Address Multiplex */ 2060669d4d3Swdenk #define OR_ACS_MSK 0x00000600 /* Address to Chip Select Setup mask */ 2070669d4d3Swdenk #define OR_ACS_DIV1 0x00000000 /* CS is output at the same time */ 2080669d4d3Swdenk #define OR_ACS_DIV4 0x00000400 /* CS is output 1/4 a clock later */ 2090669d4d3Swdenk #define OR_ACS_DIV2 0x00000600 /* CS is output 1/2 a clock later */ 2100669d4d3Swdenk #define OR_G5LA 0x00000400 /* Output #GPL5 on #GPL_A5 */ 2110669d4d3Swdenk #define OR_G5LS 0x00000200 /* Drive #GPL high on falling edge of...*/ 2120669d4d3Swdenk #define OR_BI 0x00000100 /* Burst inhibit */ 213*682011ffSwdenk #define OR_SCY_MSK 0x000000F0 /* Cycle Lenght in Clocks */ 2140669d4d3Swdenk #define OR_SCY_0_CLK 0x00000000 /* 0 clock cycles wait states */ 2150669d4d3Swdenk #define OR_SCY_1_CLK 0x00000010 /* 1 clock cycles wait states */ 2160669d4d3Swdenk #define OR_SCY_2_CLK 0x00000020 /* 2 clock cycles wait states */ 2170669d4d3Swdenk #define OR_SCY_3_CLK 0x00000030 /* 3 clock cycles wait states */ 2180669d4d3Swdenk #define OR_SCY_4_CLK 0x00000040 /* 4 clock cycles wait states */ 2190669d4d3Swdenk #define OR_SCY_5_CLK 0x00000050 /* 5 clock cycles wait states */ 2200669d4d3Swdenk #define OR_SCY_6_CLK 0x00000060 /* 6 clock cycles wait states */ 2210669d4d3Swdenk #define OR_SCY_7_CLK 0x00000070 /* 7 clock cycles wait states */ 2220669d4d3Swdenk #define OR_SCY_8_CLK 0x00000080 /* 8 clock cycles wait states */ 2230669d4d3Swdenk #define OR_SCY_9_CLK 0x00000090 /* 9 clock cycles wait states */ 224*682011ffSwdenk #define OR_SCY_10_CLK 0x000000A0 /* 10 clock cycles wait states */ 225*682011ffSwdenk #define OR_SCY_11_CLK 0x000000B0 /* 11 clock cycles wait states */ 226*682011ffSwdenk #define OR_SCY_12_CLK 0x000000C0 /* 12 clock cycles wait states */ 227*682011ffSwdenk #define OR_SCY_13_CLK 0x000000D0 /* 13 clock cycles wait states */ 228*682011ffSwdenk #define OR_SCY_14_CLK 0x000000E0 /* 14 clock cycles wait states */ 229*682011ffSwdenk #define OR_SCY_15_CLK 0x000000F0 /* 15 clock cycles wait states */ 2300669d4d3Swdenk #define OR_SETA 0x00000008 /* External Transfer Acknowledge */ 2310669d4d3Swdenk #define OR_TRLX 0x00000004 /* Timing Relaxed */ 2320669d4d3Swdenk #define OR_EHTR 0x00000002 /* Extended Hold Time on Read */ 2330669d4d3Swdenk 2340669d4d3Swdenk 2350669d4d3Swdenk /*----------------------------------------------------------------------- 2360669d4d3Swdenk * MPTPR - Memory Periodic Timer Prescaler Register 16-17 2370669d4d3Swdenk */ 238*682011ffSwdenk #define MPTPR_PTP_MSK 0xFF00 /* Periodic Timers Prescaler Mask */ 2390669d4d3Swdenk #define MPTPR_PTP_DIV2 0x2000 /* BRGCLK divided by 2 */ 2400669d4d3Swdenk #define MPTPR_PTP_DIV4 0x1000 /* BRGCLK divided by 4 */ 2410669d4d3Swdenk #define MPTPR_PTP_DIV8 0x0800 /* BRGCLK divided by 8 */ 2420669d4d3Swdenk #define MPTPR_PTP_DIV16 0x0400 /* BRGCLK divided by 16 */ 2430669d4d3Swdenk #define MPTPR_PTP_DIV32 0x0200 /* BRGCLK divided by 32 */ 2440669d4d3Swdenk #define MPTPR_PTP_DIV64 0x0100 /* BRGCLK divided by 64 */ 2450669d4d3Swdenk 2460669d4d3Swdenk /*----------------------------------------------------------------------- 2470669d4d3Swdenk * MCR - Memory Command Register 2480669d4d3Swdenk */ 2490669d4d3Swdenk #define MCR_OP_WRITE 0x00000000 /* WRITE command */ 2500669d4d3Swdenk #define MCR_OP_READ 0x40000000 /* READ command */ 2510669d4d3Swdenk #define MCR_OP_RUN 0x80000000 /* RUN command */ 2520669d4d3Swdenk #define MCR_UPM_A 0x00000000 /* Select UPM A */ 2530669d4d3Swdenk #define MCR_UPM_B 0x00800000 /* Select UPM B */ 2540669d4d3Swdenk #define MCR_MB_CS0 0x00000000 /* Use Chip Select /CS0 */ 2550669d4d3Swdenk #define MCR_MB_CS1 0x00002000 /* Use Chip Select /CS1 */ 2560669d4d3Swdenk #define MCR_MB_CS2 0x00004000 /* Use Chip Select /CS2 */ 2570669d4d3Swdenk #define MCR_MB_CS3 0x00006000 /* Use Chip Select /CS3 */ 2580669d4d3Swdenk #define MCR_MB_CS4 0x00008000 /* Use Chip Select /CS4 */ 2590669d4d3Swdenk #define MCR_MB_CS5 0x0000A000 /* Use Chip Select /CS5 */ 2600669d4d3Swdenk #define MCR_MB_CS6 0x0000C000 /* Use Chip Select /CS6 */ 2610669d4d3Swdenk #define MCR_MB_CS7 0x0000E000 /* Use Chip Select /CS7 */ 2620669d4d3Swdenk #define MCR_MLCF(n) (((n)&0xF)<<8) /* Memory Command Loop Count Field */ 2630669d4d3Swdenk #define MCR_MAD(addr) ((addr)&0x3F) /* Memory Array Index */ 2640669d4d3Swdenk 2650669d4d3Swdenk /*----------------------------------------------------------------------- 2660669d4d3Swdenk * Machine A Mode Register 16-13 2670669d4d3Swdenk */ 268*682011ffSwdenk #define MAMR_PTA_MSK 0xFF000000 /* Periodic Timer A period mask */ 2690669d4d3Swdenk #define MAMR_PTA_SHIFT 0x00000018 /* Periodic Timer A period shift */ 2700669d4d3Swdenk #define MAMR_PTAE 0x00800000 /* Periodic Timer A Enable */ 2710669d4d3Swdenk #define MAMR_AMA_MSK 0x00700000 /* Addess Multiplexing size A */ 2720669d4d3Swdenk #define MAMR_AMA_TYPE_0 0x00000000 /* Addess Multiplexing Type 0 */ 2730669d4d3Swdenk #define MAMR_AMA_TYPE_1 0x00100000 /* Addess Multiplexing Type 1 */ 2740669d4d3Swdenk #define MAMR_AMA_TYPE_2 0x00200000 /* Addess Multiplexing Type 2 */ 2750669d4d3Swdenk #define MAMR_AMA_TYPE_3 0x00300000 /* Addess Multiplexing Type 3 */ 2760669d4d3Swdenk #define MAMR_AMA_TYPE_4 0x00400000 /* Addess Multiplexing Type 4 */ 2770669d4d3Swdenk #define MAMR_AMA_TYPE_5 0x00500000 /* Addess Multiplexing Type 5 */ 2780669d4d3Swdenk #define MAMR_DSA_MSK 0x00060000 /* Disable Timer period mask */ 2790669d4d3Swdenk #define MAMR_DSA_1_CYCL 0x00000000 /* 1 cycle Disable Period */ 2800669d4d3Swdenk #define MAMR_DSA_2_CYCL 0x00020000 /* 2 cycle Disable Period */ 2810669d4d3Swdenk #define MAMR_DSA_3_CYCL 0x00040000 /* 3 cycle Disable Period */ 2820669d4d3Swdenk #define MAMR_DSA_4_CYCL 0x00060000 /* 4 cycle Disable Period */ 283*682011ffSwdenk #define MAMR_G0CLA_MSK 0x0000E000 /* General Line 0 Control A */ 2840669d4d3Swdenk #define MAMR_G0CLA_A12 0x00000000 /* General Line 0 : A12 */ 2850669d4d3Swdenk #define MAMR_G0CLA_A11 0x00002000 /* General Line 0 : A11 */ 2860669d4d3Swdenk #define MAMR_G0CLA_A10 0x00004000 /* General Line 0 : A10 */ 2870669d4d3Swdenk #define MAMR_G0CLA_A9 0x00006000 /* General Line 0 : A9 */ 2880669d4d3Swdenk #define MAMR_G0CLA_A8 0x00008000 /* General Line 0 : A8 */ 289*682011ffSwdenk #define MAMR_G0CLA_A7 0x0000A000 /* General Line 0 : A7 */ 290*682011ffSwdenk #define MAMR_G0CLA_A6 0x0000C000 /* General Line 0 : A6 */ 291*682011ffSwdenk #define MAMR_G0CLA_A5 0x0000E000 /* General Line 0 : A5 */ 2920669d4d3Swdenk #define MAMR_GPL_A4DIS 0x00001000 /* GPL_A4 ouput line Disable */ 293*682011ffSwdenk #define MAMR_RLFA_MSK 0x00000F00 /* Read Loop Field A mask */ 2940669d4d3Swdenk #define MAMR_RLFA_1X 0x00000100 /* The Read Loop is executed 1 time */ 2950669d4d3Swdenk #define MAMR_RLFA_2X 0x00000200 /* The Read Loop is executed 2 times */ 2960669d4d3Swdenk #define MAMR_RLFA_3X 0x00000300 /* The Read Loop is executed 3 times */ 2970669d4d3Swdenk #define MAMR_RLFA_4X 0x00000400 /* The Read Loop is executed 4 times */ 2980669d4d3Swdenk #define MAMR_RLFA_5X 0x00000500 /* The Read Loop is executed 5 times */ 2990669d4d3Swdenk #define MAMR_RLFA_6X 0x00000600 /* The Read Loop is executed 6 times */ 3000669d4d3Swdenk #define MAMR_RLFA_7X 0x00000700 /* The Read Loop is executed 7 times */ 3010669d4d3Swdenk #define MAMR_RLFA_8X 0x00000800 /* The Read Loop is executed 8 times */ 3020669d4d3Swdenk #define MAMR_RLFA_9X 0x00000900 /* The Read Loop is executed 9 times */ 303*682011ffSwdenk #define MAMR_RLFA_10X 0x00000A00 /* The Read Loop is executed 10 times */ 304*682011ffSwdenk #define MAMR_RLFA_11X 0x00000B00 /* The Read Loop is executed 11 times */ 305*682011ffSwdenk #define MAMR_RLFA_12X 0x00000C00 /* The Read Loop is executed 12 times */ 306*682011ffSwdenk #define MAMR_RLFA_13X 0x00000D00 /* The Read Loop is executed 13 times */ 307*682011ffSwdenk #define MAMR_RLFA_14X 0x00000E00 /* The Read Loop is executed 14 times */ 308*682011ffSwdenk #define MAMR_RLFA_15X 0x00000F00 /* The Read Loop is executed 15 times */ 3090669d4d3Swdenk #define MAMR_RLFA_16X 0x00000000 /* The Read Loop is executed 16 times */ 310*682011ffSwdenk #define MAMR_WLFA_MSK 0x000000F0 /* Write Loop Field A mask */ 3110669d4d3Swdenk #define MAMR_WLFA_1X 0x00000010 /* The Write Loop is executed 1 time */ 3120669d4d3Swdenk #define MAMR_WLFA_2X 0x00000020 /* The Write Loop is executed 2 times */ 3130669d4d3Swdenk #define MAMR_WLFA_3X 0x00000030 /* The Write Loop is executed 3 times */ 3140669d4d3Swdenk #define MAMR_WLFA_4X 0x00000040 /* The Write Loop is executed 4 times */ 3150669d4d3Swdenk #define MAMR_WLFA_5X 0x00000050 /* The Write Loop is executed 5 times */ 3160669d4d3Swdenk #define MAMR_WLFA_6X 0x00000060 /* The Write Loop is executed 6 times */ 3170669d4d3Swdenk #define MAMR_WLFA_7X 0x00000070 /* The Write Loop is executed 7 times */ 3180669d4d3Swdenk #define MAMR_WLFA_8X 0x00000080 /* The Write Loop is executed 8 times */ 3190669d4d3Swdenk #define MAMR_WLFA_9X 0x00000090 /* The Write Loop is executed 9 times */ 320*682011ffSwdenk #define MAMR_WLFA_10X 0x000000A0 /* The Write Loop is executed 10 times */ 321*682011ffSwdenk #define MAMR_WLFA_11X 0x000000B0 /* The Write Loop is executed 11 times */ 322*682011ffSwdenk #define MAMR_WLFA_12X 0x000000C0 /* The Write Loop is executed 12 times */ 323*682011ffSwdenk #define MAMR_WLFA_13X 0x000000D0 /* The Write Loop is executed 13 times */ 324*682011ffSwdenk #define MAMR_WLFA_14X 0x000000E0 /* The Write Loop is executed 14 times */ 325*682011ffSwdenk #define MAMR_WLFA_15X 0x000000F0 /* The Write Loop is executed 15 times */ 3260669d4d3Swdenk #define MAMR_WLFA_16X 0x00000000 /* The Write Loop is executed 16 times */ 327*682011ffSwdenk #define MAMR_TLFA_MSK 0x0000000F /* Timer Loop Field A mask */ 3280669d4d3Swdenk #define MAMR_TLFA_1X 0x00000001 /* The Timer Loop is executed 1 time */ 3290669d4d3Swdenk #define MAMR_TLFA_2X 0x00000002 /* The Timer Loop is executed 2 times */ 3300669d4d3Swdenk #define MAMR_TLFA_3X 0x00000003 /* The Timer Loop is executed 3 times */ 3310669d4d3Swdenk #define MAMR_TLFA_4X 0x00000004 /* The Timer Loop is executed 4 times */ 3320669d4d3Swdenk #define MAMR_TLFA_5X 0x00000005 /* The Timer Loop is executed 5 times */ 3330669d4d3Swdenk #define MAMR_TLFA_6X 0x00000006 /* The Timer Loop is executed 6 times */ 3340669d4d3Swdenk #define MAMR_TLFA_7X 0x00000007 /* The Timer Loop is executed 7 times */ 3350669d4d3Swdenk #define MAMR_TLFA_8X 0x00000008 /* The Timer Loop is executed 8 times */ 3360669d4d3Swdenk #define MAMR_TLFA_9X 0x00000009 /* The Timer Loop is executed 9 times */ 337*682011ffSwdenk #define MAMR_TLFA_10X 0x0000000A /* The Timer Loop is executed 10 times */ 338*682011ffSwdenk #define MAMR_TLFA_11X 0x0000000B /* The Timer Loop is executed 11 times */ 339*682011ffSwdenk #define MAMR_TLFA_12X 0x0000000C /* The Timer Loop is executed 12 times */ 340*682011ffSwdenk #define MAMR_TLFA_13X 0x0000000D /* The Timer Loop is executed 13 times */ 341*682011ffSwdenk #define MAMR_TLFA_14X 0x0000000E /* The Timer Loop is executed 14 times */ 342*682011ffSwdenk #define MAMR_TLFA_15X 0x0000000F /* The Timer Loop is executed 15 times */ 3430669d4d3Swdenk #define MAMR_TLFA_16X 0x00000000 /* The Timer Loop is executed 16 times */ 3440669d4d3Swdenk 3450669d4d3Swdenk /*----------------------------------------------------------------------- 3460669d4d3Swdenk * Machine B Mode Register 16-13 3470669d4d3Swdenk */ 348*682011ffSwdenk #define MAMR_PTB_MSK 0xFF000000 /* Periodic Timer B period mask */ 3490669d4d3Swdenk #define MAMR_PTB_SHIFT 0x00000018 /* Periodic Timer B period shift */ 3500669d4d3Swdenk #define MAMR_PTBE 0x00800000 /* Periodic Timer B Enable */ 3510669d4d3Swdenk #define MAMR_AMB_MSK 0x00700000 /* Addess Multiplex size B */ 3520669d4d3Swdenk #define MAMR_AMB_TYPE_0 0x00000000 /* Addess Multiplexing Type 0 */ 3530669d4d3Swdenk #define MAMR_AMB_TYPE_1 0x00100000 /* Addess Multiplexing Type 1 */ 3540669d4d3Swdenk #define MAMR_AMB_TYPE_2 0x00200000 /* Addess Multiplexing Type 2 */ 3550669d4d3Swdenk #define MAMR_AMB_TYPE_3 0x00300000 /* Addess Multiplexing Type 3 */ 3560669d4d3Swdenk #define MAMR_AMB_TYPE_4 0x00400000 /* Addess Multiplexing Type 4 */ 3570669d4d3Swdenk #define MAMR_AMB_TYPE_5 0x00500000 /* Addess Multiplexing Type 5 */ 3580669d4d3Swdenk #define MAMR_DSB_MSK 0x00060000 /* Disable Timer period mask */ 3590669d4d3Swdenk #define MAMR_DSB_1_CYCL 0x00000000 /* 1 cycle Disable Period */ 3600669d4d3Swdenk #define MAMR_DSB_2_CYCL 0x00020000 /* 2 cycle Disable Period */ 3610669d4d3Swdenk #define MAMR_DSB_3_CYCL 0x00040000 /* 3 cycle Disable Period */ 3620669d4d3Swdenk #define MAMR_DSB_4_CYCL 0x00060000 /* 4 cycle Disable Period */ 363*682011ffSwdenk #define MAMR_G0CLB_MSK 0x0000E000 /* General Line 0 Control B */ 3640669d4d3Swdenk #define MAMR_G0CLB_A12 0x00000000 /* General Line 0 : A12 */ 3650669d4d3Swdenk #define MAMR_G0CLB_A11 0x00002000 /* General Line 0 : A11 */ 3660669d4d3Swdenk #define MAMR_G0CLB_A10 0x00004000 /* General Line 0 : A10 */ 3670669d4d3Swdenk #define MAMR_G0CLB_A9 0x00006000 /* General Line 0 : A9 */ 3680669d4d3Swdenk #define MAMR_G0CLB_A8 0x00008000 /* General Line 0 : A8 */ 369*682011ffSwdenk #define MAMR_G0CLB_A7 0x0000A000 /* General Line 0 : A7 */ 370*682011ffSwdenk #define MAMR_G0CLB_A6 0x0000C000 /* General Line 0 : A6 */ 371*682011ffSwdenk #define MAMR_G0CLB_A5 0x0000E000 /* General Line 0 : A5 */ 3720669d4d3Swdenk #define MAMR_GPL_B4DIS 0x00001000 /* GPL_B4 ouput line Disable */ 373*682011ffSwdenk #define MAMR_RLFB_MSK 0x00000F00 /* Read Loop Field B mask */ 3740669d4d3Swdenk #define MAMR_RLFB_1X 0x00000100 /* The Read Loop is executed 1 time */ 3750669d4d3Swdenk #define MAMR_RLFB_2X 0x00000200 /* The Read Loop is executed 2 times */ 3760669d4d3Swdenk #define MAMR_RLFB_3X 0x00000300 /* The Read Loop is executed 3 times */ 3770669d4d3Swdenk #define MAMR_RLFB_4X 0x00000400 /* The Read Loop is executed 4 times */ 3780669d4d3Swdenk #define MAMR_RLFB_5X 0x00000500 /* The Read Loop is executed 5 times */ 3790669d4d3Swdenk #define MAMR_RLFB_6X 0x00000600 /* The Read Loop is executed 6 times */ 3800669d4d3Swdenk #define MAMR_RLFB_7X 0x00000700 /* The Read Loop is executed 7 times */ 3810669d4d3Swdenk #define MAMR_RLFB_8X 0x00000800 /* The Read Loop is executed 8 times */ 3820669d4d3Swdenk #define MAMR_RLFB_9X 0x00000900 /* The Read Loop is executed 9 times */ 383*682011ffSwdenk #define MAMR_RLFB_10X 0x00000A00 /* The Read Loop is executed 10 times */ 384*682011ffSwdenk #define MAMR_RLFB_11X 0x00000B00 /* The Read Loop is executed 11 times */ 385*682011ffSwdenk #define MAMR_RLFB_12X 0x00000C00 /* The Read Loop is executed 12 times */ 386*682011ffSwdenk #define MAMR_RLFB_13X 0x00000D00 /* The Read Loop is executed 13 times */ 387*682011ffSwdenk #define MAMR_RLFB_14X 0x00000E00 /* The Read Loop is executed 14 times */ 3880669d4d3Swdenk #define MAMR_RLFB_15X 0x00000f00 /* The Read Loop is executed 15 times */ 3890669d4d3Swdenk #define MAMR_RLFB_16X 0x00000000 /* The Read Loop is executed 16 times */ 390*682011ffSwdenk #define MAMR_WLFB_MSK 0x000000F0 /* Write Loop Field B mask */ 3910669d4d3Swdenk #define MAMR_WLFB_1X 0x00000010 /* The Write Loop is executed 1 time */ 3920669d4d3Swdenk #define MAMR_WLFB_2X 0x00000020 /* The Write Loop is executed 2 times */ 3930669d4d3Swdenk #define MAMR_WLFB_3X 0x00000030 /* The Write Loop is executed 3 times */ 3940669d4d3Swdenk #define MAMR_WLFB_4X 0x00000040 /* The Write Loop is executed 4 times */ 3950669d4d3Swdenk #define MAMR_WLFB_5X 0x00000050 /* The Write Loop is executed 5 times */ 3960669d4d3Swdenk #define MAMR_WLFB_6X 0x00000060 /* The Write Loop is executed 6 times */ 3970669d4d3Swdenk #define MAMR_WLFB_7X 0x00000070 /* The Write Loop is executed 7 times */ 3980669d4d3Swdenk #define MAMR_WLFB_8X 0x00000080 /* The Write Loop is executed 8 times */ 3990669d4d3Swdenk #define MAMR_WLFB_9X 0x00000090 /* The Write Loop is executed 9 times */ 400*682011ffSwdenk #define MAMR_WLFB_10X 0x000000A0 /* The Write Loop is executed 10 times */ 401*682011ffSwdenk #define MAMR_WLFB_11X 0x000000B0 /* The Write Loop is executed 11 times */ 402*682011ffSwdenk #define MAMR_WLFB_12X 0x000000C0 /* The Write Loop is executed 12 times */ 403*682011ffSwdenk #define MAMR_WLFB_13X 0x000000D0 /* The Write Loop is executed 13 times */ 404*682011ffSwdenk #define MAMR_WLFB_14X 0x000000E0 /* The Write Loop is executed 14 times */ 405*682011ffSwdenk #define MAMR_WLFB_15X 0x000000F0 /* The Write Loop is executed 15 times */ 4060669d4d3Swdenk #define MAMR_WLFB_16X 0x00000000 /* The Write Loop is executed 16 times */ 407*682011ffSwdenk #define MAMR_TLFB_MSK 0x0000000F /* Timer Loop Field B mask */ 4080669d4d3Swdenk #define MAMR_TLFB_1X 0x00000001 /* The Timer Loop is executed 1 time */ 4090669d4d3Swdenk #define MAMR_TLFB_2X 0x00000002 /* The Timer Loop is executed 2 times */ 4100669d4d3Swdenk #define MAMR_TLFB_3X 0x00000003 /* The Timer Loop is executed 3 times */ 4110669d4d3Swdenk #define MAMR_TLFB_4X 0x00000004 /* The Timer Loop is executed 4 times */ 4120669d4d3Swdenk #define MAMR_TLFB_5X 0x00000005 /* The Timer Loop is executed 5 times */ 4130669d4d3Swdenk #define MAMR_TLFB_6X 0x00000006 /* The Timer Loop is executed 6 times */ 4140669d4d3Swdenk #define MAMR_TLFB_7X 0x00000007 /* The Timer Loop is executed 7 times */ 4150669d4d3Swdenk #define MAMR_TLFB_8X 0x00000008 /* The Timer Loop is executed 8 times */ 4160669d4d3Swdenk #define MAMR_TLFB_9X 0x00000009 /* The Timer Loop is executed 9 times */ 417*682011ffSwdenk #define MAMR_TLFB_10X 0x0000000A /* The Timer Loop is executed 10 times */ 418*682011ffSwdenk #define MAMR_TLFB_11X 0x0000000B /* The Timer Loop is executed 11 times */ 419*682011ffSwdenk #define MAMR_TLFB_12X 0x0000000C /* The Timer Loop is executed 12 times */ 420*682011ffSwdenk #define MAMR_TLFB_13X 0x0000000D /* The Timer Loop is executed 13 times */ 421*682011ffSwdenk #define MAMR_TLFB_14X 0x0000000E /* The Timer Loop is executed 14 times */ 422*682011ffSwdenk #define MAMR_TLFB_15X 0x0000000F /* The Timer Loop is executed 15 times */ 4230669d4d3Swdenk #define MAMR_TLFB_16X 0x00000000 /* The Timer Loop is executed 16 times */ 4240669d4d3Swdenk 4250669d4d3Swdenk /*----------------------------------------------------------------------- 4260669d4d3Swdenk * Timer Global Configuration Register 18-8 4270669d4d3Swdenk */ 4280669d4d3Swdenk #define TGCR_CAS4 0x8000 /* Cascade Timer 3 and 4 */ 4290669d4d3Swdenk #define TGCR_FRZ4 0x4000 /* Freeze timer 4 */ 4300669d4d3Swdenk #define TGCR_STP4 0x2000 /* Stop timer 4 */ 4310669d4d3Swdenk #define TGCR_RST4 0x1000 /* Reset timer 4 */ 4320669d4d3Swdenk #define TGCR_GM2 0x0800 /* Gate Mode for Pin 2 */ 4330669d4d3Swdenk #define TGCR_FRZ3 0x0400 /* Freeze timer 3 */ 4340669d4d3Swdenk #define TGCR_STP3 0x0200 /* Stop timer 3 */ 4350669d4d3Swdenk #define TGCR_RST3 0x0100 /* Reset timer 3 */ 4360669d4d3Swdenk #define TGCR_CAS2 0x0080 /* Cascade Timer 1 and 2 */ 4370669d4d3Swdenk #define TGCR_FRZ2 0x0040 /* Freeze timer 2 */ 4380669d4d3Swdenk #define TGCR_STP2 0x0020 /* Stop timer 2 */ 4390669d4d3Swdenk #define TGCR_RST2 0x0010 /* Reset timer 2 */ 4400669d4d3Swdenk #define TGCR_GM1 0x0008 /* Gate Mode for Pin 1 */ 4410669d4d3Swdenk #define TGCR_FRZ1 0x0004 /* Freeze timer 1 */ 4420669d4d3Swdenk #define TGCR_STP1 0x0002 /* Stop timer 1 */ 4430669d4d3Swdenk #define TGCR_RST1 0x0001 /* Reset timer 1 */ 4440669d4d3Swdenk 4450669d4d3Swdenk 4460669d4d3Swdenk /*----------------------------------------------------------------------- 4470669d4d3Swdenk * Timer Mode Register 18-9 4480669d4d3Swdenk */ 449*682011ffSwdenk #define TMR_PS_MSK 0xFF00 /* Prescaler Value */ 4500669d4d3Swdenk #define TMR_PS_SHIFT 8 /* Prescaler position */ 451*682011ffSwdenk #define TMR_CE_MSK 0x00C0 /* Capture Edge and Enable Interrupt */ 4520669d4d3Swdenk #define TMR_CE_INTR_DIS 0x0000 /* Disable Interrupt on capture event */ 4530669d4d3Swdenk #define TMR_CE_RISING 0x0040 /* Capture on Rising TINx edge only */ 4540669d4d3Swdenk #define TMR_CE_FALLING 0x0080 /* Capture on Falling TINx edge only */ 455*682011ffSwdenk #define TMR_CE_ANY 0x00C0 /* Capture on any TINx edge */ 4560669d4d3Swdenk #define TMR_OM 0x0020 /* Output Mode */ 4570669d4d3Swdenk #define TMR_ORI 0x0010 /* Output Reference Interrupt Enable */ 4580669d4d3Swdenk #define TMR_FRR 0x0008 /* Free Run/Restart */ 4590669d4d3Swdenk #define TMR_ICLK_MSK 0x0006 /* Timer Input Clock Source mask */ 4600669d4d3Swdenk #define TMR_ICLK_IN_CAS 0x0000 /* Internally cascaded input */ 4610669d4d3Swdenk #define TMR_ICLK_IN_GEN 0x0002 /* Internal General system clock */ 4620669d4d3Swdenk #define TMR_ICLK_IN_GEN_DIV16 0x0004 /* Internal General system clk div 16 */ 4630669d4d3Swdenk #define TMR_ICLK_TIN_PIN 0x0006 /* TINx pin */ 4640669d4d3Swdenk #define TMR_GE 0x0001 /* Gate Enable */ 4650669d4d3Swdenk 4660669d4d3Swdenk 4670669d4d3Swdenk /*----------------------------------------------------------------------- 4680669d4d3Swdenk * I2C Controller Registers 4690669d4d3Swdenk */ 4700669d4d3Swdenk #define I2MOD_REVD 0x20 /* Reverese Data */ 4710669d4d3Swdenk #define I2MOD_GCD 0x10 /* General Call Disable */ 4720669d4d3Swdenk #define I2MOD_FLT 0x08 /* Clock Filter */ 4730669d4d3Swdenk #define I2MOD_PDIV32 0x00 /* Pre-Divider 32 */ 4740669d4d3Swdenk #define I2MOD_PDIV16 0x02 /* Pre-Divider 16 */ 4750669d4d3Swdenk #define I2MOD_PDIV8 0x04 /* Pre-Divider 8 */ 4760669d4d3Swdenk #define I2MOD_PDIV4 0x06 /* Pre-Divider 4 */ 4770669d4d3Swdenk #define I2MOD_EN 0x01 /* Enable */ 4780669d4d3Swdenk 4790669d4d3Swdenk #define I2CER_TXE 0x10 /* Tx Error */ 4800669d4d3Swdenk #define I2CER_BSY 0x04 /* Busy Condition */ 4810669d4d3Swdenk #define I2CER_TXB 0x02 /* Tx Buffer Transmitted */ 4820669d4d3Swdenk #define I2CER_RXB 0x01 /* Rx Buffer Received */ 4830669d4d3Swdenk #define I2CER_ALL (I2CER_TXE | I2CER_BSY | I2CER_TXB | I2CER_RXB) 4840669d4d3Swdenk 4850669d4d3Swdenk #define I2COM_STR 0x80 /* Start Transmit */ 4860669d4d3Swdenk #define I2COM_MASTER 0x01 /* Master mode */ 4870669d4d3Swdenk 4880669d4d3Swdenk /*----------------------------------------------------------------------- 4890669d4d3Swdenk * SPI Controller Registers 31-10 4900669d4d3Swdenk */ 4910669d4d3Swdenk #define SPI_EMASK 0x37 /* Event Mask */ 4920669d4d3Swdenk #define SPI_MME 0x20 /* Multi-Master Error */ 4930669d4d3Swdenk #define SPI_TXE 0x10 /* Transmit Error */ 4940669d4d3Swdenk #define SPI_BSY 0x04 /* Busy */ 4950669d4d3Swdenk #define SPI_TXB 0x02 /* Tx Buffer Empty */ 4960669d4d3Swdenk #define SPI_RXB 0x01 /* RX Buffer full/closed */ 4970669d4d3Swdenk 4980669d4d3Swdenk #define SPI_STR 0x80 /* SPCOM: Start transmit */ 4990669d4d3Swdenk 5000669d4d3Swdenk /*----------------------------------------------------------------------- 5010669d4d3Swdenk * PCMCIA Interface General Control Register 17-12 5020669d4d3Swdenk */ 5030669d4d3Swdenk #define PCMCIA_GCRX_CXRESET 0x00000040 5040669d4d3Swdenk #define PCMCIA_GCRX_CXOE 0x00000080 5050669d4d3Swdenk 5060669d4d3Swdenk #define PCMCIA_VS1(slot) (0x80000000 >> (slot << 4)) 5070669d4d3Swdenk #define PCMCIA_VS2(slot) (0x40000000 >> (slot << 4)) 508*682011ffSwdenk #define PCMCIA_VS_MASK(slot) (0xC0000000 >> (slot << 4)) 5090669d4d3Swdenk #define PCMCIA_VS_SHIFT(slot) (30 - (slot << 4)) 5100669d4d3Swdenk 5110669d4d3Swdenk #define PCMCIA_WP(slot) (0x20000000 >> (slot << 4)) 5120669d4d3Swdenk #define PCMCIA_CD2(slot) (0x10000000 >> (slot << 4)) 5130669d4d3Swdenk #define PCMCIA_CD1(slot) (0x08000000 >> (slot << 4)) 5140669d4d3Swdenk #define PCMCIA_BVD2(slot) (0x04000000 >> (slot << 4)) 5150669d4d3Swdenk #define PCMCIA_BVD1(slot) (0x02000000 >> (slot << 4)) 5160669d4d3Swdenk #define PCMCIA_RDY(slot) (0x01000000 >> (slot << 4)) 5170669d4d3Swdenk #define PCMCIA_RDY_L(slot) (0x00800000 >> (slot << 4)) 5180669d4d3Swdenk #define PCMCIA_RDY_H(slot) (0x00400000 >> (slot << 4)) 5190669d4d3Swdenk #define PCMCIA_RDY_R(slot) (0x00200000 >> (slot << 4)) 5200669d4d3Swdenk #define PCMCIA_RDY_F(slot) (0x00100000 >> (slot << 4)) 5210669d4d3Swdenk #define PCMCIA_MASK(slot) (0xFFFF0000 >> (slot << 4)) 5220669d4d3Swdenk 5230669d4d3Swdenk /*----------------------------------------------------------------------- 5240669d4d3Swdenk * PCMCIA Option Register Definitions 5250669d4d3Swdenk * 5260669d4d3Swdenk * Bank Sizes: 5270669d4d3Swdenk */ 5280669d4d3Swdenk #define PCMCIA_BSIZE_1 0x00000000 /* Bank size: 1 Bytes */ 5290669d4d3Swdenk #define PCMCIA_BSIZE_2 0x08000000 /* Bank size: 2 Bytes */ 5300669d4d3Swdenk #define PCMCIA_BSIZE_4 0x18000000 /* Bank size: 4 Bytes */ 5310669d4d3Swdenk #define PCMCIA_BSIZE_8 0x10000000 /* Bank size: 8 Bytes */ 5320669d4d3Swdenk #define PCMCIA_BSIZE_16 0x30000000 /* Bank size: 16 Bytes */ 5330669d4d3Swdenk #define PCMCIA_BSIZE_32 0x38000000 /* Bank size: 32 Bytes */ 5340669d4d3Swdenk #define PCMCIA_BSIZE_64 0x28000000 /* Bank size: 64 Bytes */ 5350669d4d3Swdenk #define PCMCIA_BSIZE_128 0x20000000 /* Bank size: 128 Bytes */ 5360669d4d3Swdenk #define PCMCIA_BSIZE_256 0x60000000 /* Bank size: 256 Bytes */ 5370669d4d3Swdenk #define PCMCIA_BSIZE_512 0x68000000 /* Bank size: 512 Bytes */ 5380669d4d3Swdenk #define PCMCIA_BSIZE_1K 0x78000000 /* Bank size: 1 kB */ 5390669d4d3Swdenk #define PCMCIA_BSIZE_2K 0x70000000 /* Bank size: 2 kB */ 5400669d4d3Swdenk #define PCMCIA_BSIZE_4K 0x50000000 /* Bank size: 4 kB */ 5410669d4d3Swdenk #define PCMCIA_BSIZE_8K 0x58000000 /* Bank size: 8 kB */ 5420669d4d3Swdenk #define PCMCIA_BSIZE_16K 0x48000000 /* Bank size: 16 kB */ 5430669d4d3Swdenk #define PCMCIA_BSIZE_32K 0x40000000 /* Bank size: 32 kB */ 5440669d4d3Swdenk #define PCMCIA_BSIZE_64K 0xC0000000 /* Bank size: 64 kB */ 5450669d4d3Swdenk #define PCMCIA_BSIZE_128K 0xC8000000 /* Bank size: 128 kB */ 5460669d4d3Swdenk #define PCMCIA_BSIZE_256K 0xD8000000 /* Bank size: 256 kB */ 5470669d4d3Swdenk #define PCMCIA_BSIZE_512K 0xD0000000 /* Bank size: 512 kB */ 5480669d4d3Swdenk #define PCMCIA_BSIZE_1M 0xF0000000 /* Bank size: 1 MB */ 5490669d4d3Swdenk #define PCMCIA_BSIZE_2M 0xF8000000 /* Bank size: 2 MB */ 5500669d4d3Swdenk #define PCMCIA_BSIZE_4M 0xE8000000 /* Bank size: 4 MB */ 5510669d4d3Swdenk #define PCMCIA_BSIZE_8M 0xE0000000 /* Bank size: 8 MB */ 5520669d4d3Swdenk #define PCMCIA_BSIZE_16M 0xA0000000 /* Bank size: 16 MB */ 5530669d4d3Swdenk #define PCMCIA_BSIZE_32M 0xA8000000 /* Bank size: 32 MB */ 5540669d4d3Swdenk #define PCMCIA_BSIZE_64M 0xB8000000 /* Bank size: 64 MB */ 5550669d4d3Swdenk 5560669d4d3Swdenk /* PCMCIA Timing */ 5570669d4d3Swdenk #define PCMCIA_SHT(t) ((t & 0x0F)<<16) /* Strobe Hold Time */ 5580669d4d3Swdenk #define PCMCIA_SST(t) ((t & 0x0F)<<12) /* Strobe Setup Time */ 5590669d4d3Swdenk #define PCMCIA_SL(t) ((t==32) ? 0 : ((t & 0x1F)<<7)) /* Strobe Length */ 5600669d4d3Swdenk 5610669d4d3Swdenk /* PCMCIA Port Sizes */ 5620669d4d3Swdenk #define PCMCIA_PPS_8 0x00000000 /* 8 bit port size */ 5630669d4d3Swdenk #define PCMCIA_PPS_16 0x00000040 /* 16 bit port size */ 5640669d4d3Swdenk 5650669d4d3Swdenk /* PCMCIA Region Select */ 5660669d4d3Swdenk #define PCMCIA_PRS_MEM 0x00000000 /* Common Memory Space */ 5670669d4d3Swdenk #define PCMCIA_PRS_ATTR 0x00000010 /* Attribute Space */ 5680669d4d3Swdenk #define PCMCIA_PRS_IO 0x00000018 /* I/O Space */ 5690669d4d3Swdenk #define PCMCIA_PRS_DMA 0x00000020 /* DMA, normal transfer */ 5700669d4d3Swdenk #define PCMCIA_PRS_DMA_LAST 0x00000028 /* DMA, last transactn */ 5710669d4d3Swdenk #define PCMCIA_PRS_CEx 0x00000030 /* A[22:23] ==> CE1,CE2 */ 5720669d4d3Swdenk 5730669d4d3Swdenk #define PCMCIA_PSLOT_A 0x00000000 /* Slot A */ 5740669d4d3Swdenk #define PCMCIA_PSLOT_B 0x00000004 /* Slot B */ 5750669d4d3Swdenk #define PCMCIA_WPROT 0x00000002 /* Write Protect */ 5760669d4d3Swdenk #define PCMCIA_PV 0x00000001 /* Valid Bit */ 5770669d4d3Swdenk 5780669d4d3Swdenk #define UPMA 0x00000000 5790669d4d3Swdenk #define UPMB 0x00800000 5800669d4d3Swdenk 5810669d4d3Swdenk #endif /* __MPCXX_H__ */ 582