10669d4d3Swdenk /* 2d4ca31c4Swdenk * (C) Copyright 2000-2004 30669d4d3Swdenk * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 40669d4d3Swdenk * 51a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 60669d4d3Swdenk */ 70669d4d3Swdenk 80669d4d3Swdenk /* 90669d4d3Swdenk * mpc8xx.h 100669d4d3Swdenk * 110669d4d3Swdenk * MPC8xx specific definitions 120669d4d3Swdenk */ 130669d4d3Swdenk 140669d4d3Swdenk #ifndef __MPCXX_H__ 150669d4d3Swdenk #define __MPCXX_H__ 160669d4d3Swdenk 170669d4d3Swdenk 180669d4d3Swdenk /*----------------------------------------------------------------------- 190669d4d3Swdenk * Exception offsets (PowerPC standard) 200669d4d3Swdenk */ 210669d4d3Swdenk #define EXC_OFF_SYS_RESET 0x0100 /* System reset */ 2202032e8fSRafal Jaworowski #define _START_OFFSET EXC_OFF_SYS_RESET 230669d4d3Swdenk 240669d4d3Swdenk /*----------------------------------------------------------------------- 250669d4d3Swdenk * SYPCR - System Protection Control Register 11-9 260669d4d3Swdenk */ 27682011ffSwdenk #define SYPCR_SWTC 0xFFFF0000 /* Software Watchdog Timer Count */ 28682011ffSwdenk #define SYPCR_BMT 0x0000FF00 /* Bus Monitor Timing */ 290669d4d3Swdenk #define SYPCR_BME 0x00000080 /* Bus Monitor Enable */ 300669d4d3Swdenk #define SYPCR_SWF 0x00000008 /* Software Watchdog Freeze */ 310669d4d3Swdenk #define SYPCR_SWE 0x00000004 /* Software Watchdog Enable */ 320669d4d3Swdenk #define SYPCR_SWRI 0x00000002 /* Software Watchdog Reset/Int Select */ 330669d4d3Swdenk #define SYPCR_SWP 0x00000001 /* Software Watchdog Prescale */ 340669d4d3Swdenk 350669d4d3Swdenk /*----------------------------------------------------------------------- 360669d4d3Swdenk * SIUMCR - SIU Module Configuration Register 11-6 370669d4d3Swdenk */ 380669d4d3Swdenk #define SIUMCR_EARB 0x80000000 /* External Arbitration */ 390669d4d3Swdenk #define SIUMCR_EARP0 0x00000000 /* External Arbi. Request priority 0 */ 400669d4d3Swdenk #define SIUMCR_EARP1 0x10000000 /* External Arbi. Request priority 1 */ 410669d4d3Swdenk #define SIUMCR_EARP2 0x20000000 /* External Arbi. Request priority 2 */ 420669d4d3Swdenk #define SIUMCR_EARP3 0x30000000 /* External Arbi. Request priority 3 */ 430669d4d3Swdenk #define SIUMCR_EARP4 0x40000000 /* External Arbi. Request priority 4 */ 440669d4d3Swdenk #define SIUMCR_EARP5 0x50000000 /* External Arbi. Request priority 5 */ 450669d4d3Swdenk #define SIUMCR_EARP6 0x60000000 /* External Arbi. Request priority 6 */ 460669d4d3Swdenk #define SIUMCR_EARP7 0x70000000 /* External Arbi. Request priority 7 */ 470669d4d3Swdenk #define SIUMCR_DSHW 0x00800000 /* Data Showcycles */ 480669d4d3Swdenk #define SIUMCR_DBGC00 0x00000000 /* Debug pins configuration */ 490669d4d3Swdenk #define SIUMCR_DBGC01 0x00200000 /* - " - */ 500669d4d3Swdenk #define SIUMCR_DBGC10 0x00400000 /* - " - */ 510669d4d3Swdenk #define SIUMCR_DBGC11 0x00600000 /* - " - */ 520669d4d3Swdenk #define SIUMCR_DBPC00 0x00000000 /* Debug Port pins Config. */ 530669d4d3Swdenk #define SIUMCR_DBPC01 0x00080000 /* - " - */ 540669d4d3Swdenk #define SIUMCR_DBPC10 0x00100000 /* - " - */ 550669d4d3Swdenk #define SIUMCR_DBPC11 0x00180000 /* - " - */ 560669d4d3Swdenk #define SIUMCR_FRC 0x00020000 /* FRZ pin Configuration */ 570669d4d3Swdenk #define SIUMCR_DLK 0x00010000 /* Debug Register Lock */ 580669d4d3Swdenk #define SIUMCR_PNCS 0x00008000 /* Parity Non-mem Crtl reg */ 590669d4d3Swdenk #define SIUMCR_OPAR 0x00004000 /* Odd Parity */ 600669d4d3Swdenk #define SIUMCR_DPC 0x00002000 /* Data Parity pins Config. */ 610669d4d3Swdenk #define SIUMCR_MPRE 0x00001000 /* Multi CPU Reserva. Enable */ 620669d4d3Swdenk #define SIUMCR_MLRC00 0x00000000 /* Multi Level Reserva. Ctrl */ 630669d4d3Swdenk #define SIUMCR_MLRC01 0x00000400 /* - " - */ 640669d4d3Swdenk #define SIUMCR_MLRC10 0x00000800 /* - " - */ 65682011ffSwdenk #define SIUMCR_MLRC11 0x00000C00 /* - " - */ 660669d4d3Swdenk #define SIUMCR_AEME 0x00000200 /* Asynchro External Master */ 670669d4d3Swdenk #define SIUMCR_SEME 0x00000100 /* Synchro External Master */ 680669d4d3Swdenk #define SIUMCR_BSC 0x00000080 /* Byte Select Configuration */ 690669d4d3Swdenk #define SIUMCR_GB5E 0x00000040 /* GPL_B(5) Enable */ 700669d4d3Swdenk #define SIUMCR_B2DD 0x00000020 /* Bank 2 Double Drive */ 710669d4d3Swdenk #define SIUMCR_B3DD 0x00000010 /* Bank 3 Double Drive */ 720669d4d3Swdenk 730669d4d3Swdenk /*----------------------------------------------------------------------- 740669d4d3Swdenk * TBSCR - Time Base Status and Control Register 11-26 750669d4d3Swdenk */ 760669d4d3Swdenk #define TBSCR_TBIRQ7 0x8000 /* Time Base Interrupt Request 7 */ 770669d4d3Swdenk #define TBSCR_TBIRQ6 0x4000 /* Time Base Interrupt Request 6 */ 780669d4d3Swdenk #define TBSCR_TBIRQ5 0x2000 /* Time Base Interrupt Request 5 */ 790669d4d3Swdenk #define TBSCR_TBIRQ4 0x1000 /* Time Base Interrupt Request 4 */ 800669d4d3Swdenk #define TBSCR_TBIRQ3 0x0800 /* Time Base Interrupt Request 3 */ 810669d4d3Swdenk #define TBSCR_TBIRQ2 0x0400 /* Time Base Interrupt Request 2 */ 820669d4d3Swdenk #define TBSCR_TBIRQ1 0x0200 /* Time Base Interrupt Request 1 */ 830669d4d3Swdenk #define TBSCR_TBIRQ0 0x0100 /* Time Base Interrupt Request 0 */ 84*87e4c602SChristophe Leroy #if 0 /* already in asm/immap_8xx.h */ 850669d4d3Swdenk #define TBSCR_REFA 0x0080 /* Reference Interrupt Status A */ 860669d4d3Swdenk #define TBSCR_REFB 0x0040 /* Reference Interrupt Status B */ 870669d4d3Swdenk #define TBSCR_REFAE 0x0008 /* Second Interrupt Enable A */ 880669d4d3Swdenk #define TBSCR_REFBE 0x0004 /* Second Interrupt Enable B */ 890669d4d3Swdenk #define TBSCR_TBF 0x0002 /* Time Base Freeze */ 900669d4d3Swdenk #define TBSCR_TBE 0x0001 /* Time Base Enable */ 910669d4d3Swdenk #endif 920669d4d3Swdenk 930669d4d3Swdenk /*----------------------------------------------------------------------- 940669d4d3Swdenk * PISCR - Periodic Interrupt Status and Control Register 11-31 950669d4d3Swdenk */ 960669d4d3Swdenk #undef PISCR_PIRQ /* TBD */ 970669d4d3Swdenk #define PISCR_PITF 0x0002 /* Periodic Interrupt Timer Freeze */ 98*87e4c602SChristophe Leroy #if 0 /* already in asm/immap_8xx.h */ 990669d4d3Swdenk #define PISCR_PS 0x0080 /* Periodic interrupt Status */ 1000669d4d3Swdenk #define PISCR_PIE 0x0004 /* Periodic Interrupt Enable */ 1010669d4d3Swdenk #define PISCR_PTE 0x0001 /* Periodic Timer Enable */ 1020669d4d3Swdenk #endif 1030669d4d3Swdenk 1040669d4d3Swdenk /*----------------------------------------------------------------------- 105d1cbe85bSwdenk * RSR - Reset Status Register 5-4 106d1cbe85bSwdenk */ 107d1cbe85bSwdenk #define RSR_JTRS 0x01000000 /* JTAG Reset Status */ 108d1cbe85bSwdenk #define RSR_DBSRS 0x02000000 /* Debug Port Soft Reset Status */ 109d1cbe85bSwdenk #define RSR_DBHRS 0x04000000 /* Debug Port Hard Reset Status */ 110d1cbe85bSwdenk #define RSR_CSRS 0x08000000 /* Check Stop Reset Status */ 111d1cbe85bSwdenk #define RSR_SWRS 0x10000000 /* Software Watchdog Reset Status*/ 112d1cbe85bSwdenk #define RSR_LLRS 0x20000000 /* Loss-of-Lock Reset Status */ 113d1cbe85bSwdenk #define RSR_ESRS 0x40000000 /* External Soft Reset Status */ 114d1cbe85bSwdenk #define RSR_EHRS 0x80000000 /* External Hard Reset Status */ 115d1cbe85bSwdenk 116d1cbe85bSwdenk #define RSR_ALLBITS (RSR_JTRS|RSR_DBSRS|RSR_DBHRS|RSR_CSRS|RSR_SWRS|RSR_LLRS|RSR_ESRS|RSR_EHRS) 117d1cbe85bSwdenk 118d1cbe85bSwdenk /*----------------------------------------------------------------------- 119180d3f74Swdenk * Newer chips (MPC866 family and MPC87x/88x family) have different 120180d3f74Swdenk * clock distribution system. Their IMMR lower half is >= 0x0800 121180d3f74Swdenk */ 122180d3f74Swdenk #define MPC8xx_NEW_CLK 0x0800 123180d3f74Swdenk 124180d3f74Swdenk /*----------------------------------------------------------------------- 1250669d4d3Swdenk * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 1260669d4d3Swdenk */ 127180d3f74Swdenk /* Newer chips (MPC866/87x/88x et al) defines */ 128d4ca31c4Swdenk #define PLPRCR_MFN_MSK 0xF8000000 /* Multiplication factor numerator bits */ 129d4ca31c4Swdenk #define PLPRCR_MFN_SHIFT 27 /* Multiplication factor numerator shift*/ 130d4ca31c4Swdenk #define PLPRCR_MFD_MSK 0x07C00000 /* Multiplication factor denominator bits */ 131d4ca31c4Swdenk #define PLPRCR_MFD_SHIFT 22 /* Multiplication factor denominator shift*/ 1322535d602Swdenk #define PLPRCR_S_MSK 0x00300000 /* Multiplication factor integer bits */ 133d4ca31c4Swdenk #define PLPRCR_S_SHIFT 20 /* Multiplication factor integer shift */ 134d4ca31c4Swdenk #define PLPRCR_MFI_MSK 0x000F0000 /* Multiplication factor integer bits */ 135d4ca31c4Swdenk #define PLPRCR_MFI_SHIFT 16 /* Multiplication factor integer shift */ 136180d3f74Swdenk 137180d3f74Swdenk #define PLPRCR_PDF_MSK 0x0000001E /* Predivision Factor bits */ 138180d3f74Swdenk #define PLPRCR_PDF_SHIFT 1 /* Predivision Factor shift value */ 139180d3f74Swdenk #define PLPRCR_DBRMO 0x00000001 /* DPLL BRM Order bit */ 140180d3f74Swdenk 141180d3f74Swdenk /* Multiplication factor + PDF bits */ 142180d3f74Swdenk #define PLPRCR_MFACT_MSK (PLPRCR_MFN_MSK | \ 143180d3f74Swdenk PLPRCR_MFD_MSK | \ 144180d3f74Swdenk PLPRCR_S_MSK | \ 145180d3f74Swdenk PLPRCR_MFI_MSK | \ 146180d3f74Swdenk PLPRCR_PDF_MSK) 147180d3f74Swdenk 148180d3f74Swdenk /* Common defines */ 149180d3f74Swdenk #define PLPRCR_TEXPS 0x00004000 /* TEXP Status */ 150180d3f74Swdenk #define PLPRCR_CSRC 0x00000400 /* Clock Source */ 151180d3f74Swdenk 1520669d4d3Swdenk #define PLPRCR_CSR 0x00000080 /* CheskStop Reset value */ 1530669d4d3Swdenk #define PLPRCR_LOLRE 0x00000040 /* Loss Of Lock Reset Enable */ 1540669d4d3Swdenk #define PLPRCR_FIOPD 0x00000020 /* Force I/O Pull Down */ 1550669d4d3Swdenk 1560669d4d3Swdenk /*----------------------------------------------------------------------- 1570669d4d3Swdenk * SCCR - System Clock and reset Control Register 15-27 1580669d4d3Swdenk */ 1590669d4d3Swdenk #define SCCR_COM00 0x00000000 /* full strength CLKOUT output buffer */ 1600669d4d3Swdenk #define SCCR_COM01 0x20000000 /* half strength CLKOUT output buffer */ 1610669d4d3Swdenk #define SCCR_COM10 0x40000000 /* reserved */ 1620669d4d3Swdenk #define SCCR_COM11 0x60000000 /* CLKOUT output buffer disabled */ 1630669d4d3Swdenk #define SCCR_TBS 0x02000000 /* Time Base Source */ 1640669d4d3Swdenk #define SCCR_RTDIV 0x01000000 /* RTC Clock Divide */ 1650669d4d3Swdenk #define SCCR_RTSEL 0x00800000 /* RTC circuit input source select */ 1660669d4d3Swdenk #define SCCR_CRQEN 0x00400000 /* CPM Request Enable */ 1670669d4d3Swdenk #define SCCR_PRQEN 0x00200000 /* Power Management Request Enable */ 1680669d4d3Swdenk #define SCCR_EBDF00 0x00000000 /* CLKOUT is GCLK2 / 1 (normal op.) */ 1690669d4d3Swdenk #define SCCR_EBDF01 0x00020000 /* CLKOUT is GCLK2 / 2 */ 1700669d4d3Swdenk #define SCCR_EBDF10 0x00040000 /* reserved */ 1710669d4d3Swdenk #define SCCR_EBDF11 0x00060000 /* reserved */ 1720669d4d3Swdenk #define SCCR_DFSYNC00 0x00000000 /* SyncCLK division by 1 (normal op.) */ 1730669d4d3Swdenk #define SCCR_DFSYNC01 0x00002000 /* SyncCLK division by 4 */ 1740669d4d3Swdenk #define SCCR_DFSYNC10 0x00004000 /* SyncCLK division by 16 */ 1750669d4d3Swdenk #define SCCR_DFSYNC11 0x00006000 /* SyncCLK division by 64 */ 1760669d4d3Swdenk #define SCCR_DFBRG00 0x00000000 /* BRGCLK division by 1 (normal op.) */ 1770669d4d3Swdenk #define SCCR_DFBRG01 0x00000800 /* BRGCLK division by 4 */ 1780669d4d3Swdenk #define SCCR_DFBRG10 0x00001000 /* BRGCLK division by 16 */ 1790669d4d3Swdenk #define SCCR_DFBRG11 0x00001800 /* BRGCLK division by 64 */ 1800669d4d3Swdenk #define SCCR_DFNL000 0x00000000 /* Division by 2 (default = minimum) */ 181a6ab4bf9Swdenk #define SCCR_DFNL001 0x00000100 /* Division by 4 */ 182a6ab4bf9Swdenk #define SCCR_DFNL010 0x00000200 /* Division by 8 */ 183a6ab4bf9Swdenk #define SCCR_DFNL011 0x00000300 /* Division by 16 */ 184a6ab4bf9Swdenk #define SCCR_DFNL100 0x00000400 /* Division by 32 */ 185a6ab4bf9Swdenk #define SCCR_DFNL101 0x00000500 /* Division by 64 */ 186a6ab4bf9Swdenk #define SCCR_DFNL110 0x00000600 /* Division by 128 */ 1870669d4d3Swdenk #define SCCR_DFNL111 0x00000700 /* Division by 256 (maximum) */ 1880669d4d3Swdenk #define SCCR_DFNH000 0x00000000 /* Division by 1 (default = minimum) */ 1890669d4d3Swdenk #define SCCR_DFNH110 0x000000D0 /* Division by 64 (maximum) */ 1900669d4d3Swdenk #define SCCR_DFNH111 0x000000E0 /* reserved */ 1910669d4d3Swdenk #define SCCR_DFLCD000 0x00000000 /* Division by 1 (default = minimum) */ 1920669d4d3Swdenk #define SCCR_DFLCD001 0x00000004 /* Division by 2 */ 1930669d4d3Swdenk #define SCCR_DFLCD010 0x00000008 /* Division by 4 */ 1940669d4d3Swdenk #define SCCR_DFLCD011 0x0000000C /* Division by 8 */ 1950669d4d3Swdenk #define SCCR_DFLCD100 0x00000010 /* Division by 16 */ 1960669d4d3Swdenk #define SCCR_DFLCD101 0x00000014 /* Division by 32 */ 1970669d4d3Swdenk #define SCCR_DFLCD110 0x00000018 /* Division by 64 (maximum) */ 1980669d4d3Swdenk #define SCCR_DFLCD111 0x0000001C /* reserved */ 1990669d4d3Swdenk #define SCCR_DFALCD00 0x00000000 /* Division by 1 (default = minimum) */ 2000669d4d3Swdenk #define SCCR_DFALCD01 0x00000001 /* Division by 3 */ 2010669d4d3Swdenk #define SCCR_DFALCD10 0x00000002 /* Division by 5 */ 2020669d4d3Swdenk #define SCCR_DFALCD11 0x00000003 /* Division by 7 (maximum) */ 2030669d4d3Swdenk 2040669d4d3Swdenk 2050669d4d3Swdenk /*----------------------------------------------------------------------- 2060669d4d3Swdenk * BR - Memory Controler: Base Register 16-9 2070669d4d3Swdenk */ 208682011ffSwdenk #define BR_BA_MSK 0xFFFF8000 /* Base Address Mask */ 2090669d4d3Swdenk #define BR_AT_MSK 0x00007000 /* Address Type Mask */ 210682011ffSwdenk #define BR_PS_MSK 0x00000C00 /* Port Size Mask */ 2110669d4d3Swdenk #define BR_PS_32 0x00000000 /* 32 bit port size */ 2120669d4d3Swdenk #define BR_PS_16 0x00000800 /* 16 bit port size */ 2130669d4d3Swdenk #define BR_PS_8 0x00000400 /* 8 bit port size */ 2140669d4d3Swdenk #define BR_PARE 0x00000200 /* Parity Enable */ 2150669d4d3Swdenk #define BR_WP 0x00000100 /* Write Protect */ 216682011ffSwdenk #define BR_MS_MSK 0x000000C0 /* Machine Select Mask */ 2170669d4d3Swdenk #define BR_MS_GPCM 0x00000000 /* G.P.C.M. Machine Select */ 2180669d4d3Swdenk #define BR_MS_UPMA 0x00000080 /* U.P.M.A Machine Select */ 219682011ffSwdenk #define BR_MS_UPMB 0x000000C0 /* U.P.M.B Machine Select */ 2200669d4d3Swdenk #define BR_V 0x00000001 /* Bank Valid */ 2210669d4d3Swdenk 2220669d4d3Swdenk /*----------------------------------------------------------------------- 2230669d4d3Swdenk * OR - Memory Controler: Option Register 16-11 2240669d4d3Swdenk */ 225682011ffSwdenk #define OR_AM_MSK 0xFFFF8000 /* Address Mask Mask */ 2260669d4d3Swdenk #define OR_ATM_MSK 0x00007000 /* Address Type Mask Mask */ 2270669d4d3Swdenk #define OR_CSNT_SAM 0x00000800 /* Chip Select Negation Time/ Start */ 2280669d4d3Swdenk /* Address Multiplex */ 2290669d4d3Swdenk #define OR_ACS_MSK 0x00000600 /* Address to Chip Select Setup mask */ 2300669d4d3Swdenk #define OR_ACS_DIV1 0x00000000 /* CS is output at the same time */ 2310669d4d3Swdenk #define OR_ACS_DIV4 0x00000400 /* CS is output 1/4 a clock later */ 2320669d4d3Swdenk #define OR_ACS_DIV2 0x00000600 /* CS is output 1/2 a clock later */ 2330669d4d3Swdenk #define OR_G5LA 0x00000400 /* Output #GPL5 on #GPL_A5 */ 2340669d4d3Swdenk #define OR_G5LS 0x00000200 /* Drive #GPL high on falling edge of...*/ 2350669d4d3Swdenk #define OR_BI 0x00000100 /* Burst inhibit */ 236682011ffSwdenk #define OR_SCY_MSK 0x000000F0 /* Cycle Lenght in Clocks */ 2370669d4d3Swdenk #define OR_SCY_0_CLK 0x00000000 /* 0 clock cycles wait states */ 2380669d4d3Swdenk #define OR_SCY_1_CLK 0x00000010 /* 1 clock cycles wait states */ 2390669d4d3Swdenk #define OR_SCY_2_CLK 0x00000020 /* 2 clock cycles wait states */ 2400669d4d3Swdenk #define OR_SCY_3_CLK 0x00000030 /* 3 clock cycles wait states */ 2410669d4d3Swdenk #define OR_SCY_4_CLK 0x00000040 /* 4 clock cycles wait states */ 2420669d4d3Swdenk #define OR_SCY_5_CLK 0x00000050 /* 5 clock cycles wait states */ 2430669d4d3Swdenk #define OR_SCY_6_CLK 0x00000060 /* 6 clock cycles wait states */ 2440669d4d3Swdenk #define OR_SCY_7_CLK 0x00000070 /* 7 clock cycles wait states */ 2450669d4d3Swdenk #define OR_SCY_8_CLK 0x00000080 /* 8 clock cycles wait states */ 2460669d4d3Swdenk #define OR_SCY_9_CLK 0x00000090 /* 9 clock cycles wait states */ 247682011ffSwdenk #define OR_SCY_10_CLK 0x000000A0 /* 10 clock cycles wait states */ 248682011ffSwdenk #define OR_SCY_11_CLK 0x000000B0 /* 11 clock cycles wait states */ 249682011ffSwdenk #define OR_SCY_12_CLK 0x000000C0 /* 12 clock cycles wait states */ 250682011ffSwdenk #define OR_SCY_13_CLK 0x000000D0 /* 13 clock cycles wait states */ 251682011ffSwdenk #define OR_SCY_14_CLK 0x000000E0 /* 14 clock cycles wait states */ 252682011ffSwdenk #define OR_SCY_15_CLK 0x000000F0 /* 15 clock cycles wait states */ 2530669d4d3Swdenk #define OR_SETA 0x00000008 /* External Transfer Acknowledge */ 2540669d4d3Swdenk #define OR_TRLX 0x00000004 /* Timing Relaxed */ 2550669d4d3Swdenk #define OR_EHTR 0x00000002 /* Extended Hold Time on Read */ 2560669d4d3Swdenk 2570669d4d3Swdenk 2580669d4d3Swdenk /*----------------------------------------------------------------------- 2590669d4d3Swdenk * MPTPR - Memory Periodic Timer Prescaler Register 16-17 2600669d4d3Swdenk */ 261682011ffSwdenk #define MPTPR_PTP_MSK 0xFF00 /* Periodic Timers Prescaler Mask */ 2620669d4d3Swdenk #define MPTPR_PTP_DIV2 0x2000 /* BRGCLK divided by 2 */ 2630669d4d3Swdenk #define MPTPR_PTP_DIV4 0x1000 /* BRGCLK divided by 4 */ 2640669d4d3Swdenk #define MPTPR_PTP_DIV8 0x0800 /* BRGCLK divided by 8 */ 2650669d4d3Swdenk #define MPTPR_PTP_DIV16 0x0400 /* BRGCLK divided by 16 */ 2660669d4d3Swdenk #define MPTPR_PTP_DIV32 0x0200 /* BRGCLK divided by 32 */ 2670669d4d3Swdenk #define MPTPR_PTP_DIV64 0x0100 /* BRGCLK divided by 64 */ 2680669d4d3Swdenk 2690669d4d3Swdenk /*----------------------------------------------------------------------- 2700669d4d3Swdenk * MCR - Memory Command Register 2710669d4d3Swdenk */ 2720669d4d3Swdenk #define MCR_OP_WRITE 0x00000000 /* WRITE command */ 2730669d4d3Swdenk #define MCR_OP_READ 0x40000000 /* READ command */ 2740669d4d3Swdenk #define MCR_OP_RUN 0x80000000 /* RUN command */ 2750669d4d3Swdenk #define MCR_UPM_A 0x00000000 /* Select UPM A */ 2760669d4d3Swdenk #define MCR_UPM_B 0x00800000 /* Select UPM B */ 2770669d4d3Swdenk #define MCR_MB_CS0 0x00000000 /* Use Chip Select /CS0 */ 2780669d4d3Swdenk #define MCR_MB_CS1 0x00002000 /* Use Chip Select /CS1 */ 2790669d4d3Swdenk #define MCR_MB_CS2 0x00004000 /* Use Chip Select /CS2 */ 2800669d4d3Swdenk #define MCR_MB_CS3 0x00006000 /* Use Chip Select /CS3 */ 2810669d4d3Swdenk #define MCR_MB_CS4 0x00008000 /* Use Chip Select /CS4 */ 2820669d4d3Swdenk #define MCR_MB_CS5 0x0000A000 /* Use Chip Select /CS5 */ 2830669d4d3Swdenk #define MCR_MB_CS6 0x0000C000 /* Use Chip Select /CS6 */ 2840669d4d3Swdenk #define MCR_MB_CS7 0x0000E000 /* Use Chip Select /CS7 */ 2850669d4d3Swdenk #define MCR_MLCF(n) (((n)&0xF)<<8) /* Memory Command Loop Count Field */ 2860669d4d3Swdenk #define MCR_MAD(addr) ((addr)&0x3F) /* Memory Array Index */ 2870669d4d3Swdenk 2880669d4d3Swdenk /*----------------------------------------------------------------------- 2890669d4d3Swdenk * Machine A Mode Register 16-13 2900669d4d3Swdenk */ 291682011ffSwdenk #define MAMR_PTA_MSK 0xFF000000 /* Periodic Timer A period mask */ 2920669d4d3Swdenk #define MAMR_PTA_SHIFT 0x00000018 /* Periodic Timer A period shift */ 2930669d4d3Swdenk #define MAMR_PTAE 0x00800000 /* Periodic Timer A Enable */ 2940669d4d3Swdenk #define MAMR_AMA_MSK 0x00700000 /* Addess Multiplexing size A */ 2950669d4d3Swdenk #define MAMR_AMA_TYPE_0 0x00000000 /* Addess Multiplexing Type 0 */ 2960669d4d3Swdenk #define MAMR_AMA_TYPE_1 0x00100000 /* Addess Multiplexing Type 1 */ 2970669d4d3Swdenk #define MAMR_AMA_TYPE_2 0x00200000 /* Addess Multiplexing Type 2 */ 2980669d4d3Swdenk #define MAMR_AMA_TYPE_3 0x00300000 /* Addess Multiplexing Type 3 */ 2990669d4d3Swdenk #define MAMR_AMA_TYPE_4 0x00400000 /* Addess Multiplexing Type 4 */ 3000669d4d3Swdenk #define MAMR_AMA_TYPE_5 0x00500000 /* Addess Multiplexing Type 5 */ 3010669d4d3Swdenk #define MAMR_DSA_MSK 0x00060000 /* Disable Timer period mask */ 3020669d4d3Swdenk #define MAMR_DSA_1_CYCL 0x00000000 /* 1 cycle Disable Period */ 3030669d4d3Swdenk #define MAMR_DSA_2_CYCL 0x00020000 /* 2 cycle Disable Period */ 3040669d4d3Swdenk #define MAMR_DSA_3_CYCL 0x00040000 /* 3 cycle Disable Period */ 3050669d4d3Swdenk #define MAMR_DSA_4_CYCL 0x00060000 /* 4 cycle Disable Period */ 306682011ffSwdenk #define MAMR_G0CLA_MSK 0x0000E000 /* General Line 0 Control A */ 3070669d4d3Swdenk #define MAMR_G0CLA_A12 0x00000000 /* General Line 0 : A12 */ 3080669d4d3Swdenk #define MAMR_G0CLA_A11 0x00002000 /* General Line 0 : A11 */ 3090669d4d3Swdenk #define MAMR_G0CLA_A10 0x00004000 /* General Line 0 : A10 */ 3100669d4d3Swdenk #define MAMR_G0CLA_A9 0x00006000 /* General Line 0 : A9 */ 3110669d4d3Swdenk #define MAMR_G0CLA_A8 0x00008000 /* General Line 0 : A8 */ 312682011ffSwdenk #define MAMR_G0CLA_A7 0x0000A000 /* General Line 0 : A7 */ 313682011ffSwdenk #define MAMR_G0CLA_A6 0x0000C000 /* General Line 0 : A6 */ 314682011ffSwdenk #define MAMR_G0CLA_A5 0x0000E000 /* General Line 0 : A5 */ 3150669d4d3Swdenk #define MAMR_GPL_A4DIS 0x00001000 /* GPL_A4 ouput line Disable */ 316682011ffSwdenk #define MAMR_RLFA_MSK 0x00000F00 /* Read Loop Field A mask */ 3170669d4d3Swdenk #define MAMR_RLFA_1X 0x00000100 /* The Read Loop is executed 1 time */ 3180669d4d3Swdenk #define MAMR_RLFA_2X 0x00000200 /* The Read Loop is executed 2 times */ 3190669d4d3Swdenk #define MAMR_RLFA_3X 0x00000300 /* The Read Loop is executed 3 times */ 3200669d4d3Swdenk #define MAMR_RLFA_4X 0x00000400 /* The Read Loop is executed 4 times */ 3210669d4d3Swdenk #define MAMR_RLFA_5X 0x00000500 /* The Read Loop is executed 5 times */ 3220669d4d3Swdenk #define MAMR_RLFA_6X 0x00000600 /* The Read Loop is executed 6 times */ 3230669d4d3Swdenk #define MAMR_RLFA_7X 0x00000700 /* The Read Loop is executed 7 times */ 3240669d4d3Swdenk #define MAMR_RLFA_8X 0x00000800 /* The Read Loop is executed 8 times */ 3250669d4d3Swdenk #define MAMR_RLFA_9X 0x00000900 /* The Read Loop is executed 9 times */ 326682011ffSwdenk #define MAMR_RLFA_10X 0x00000A00 /* The Read Loop is executed 10 times */ 327682011ffSwdenk #define MAMR_RLFA_11X 0x00000B00 /* The Read Loop is executed 11 times */ 328682011ffSwdenk #define MAMR_RLFA_12X 0x00000C00 /* The Read Loop is executed 12 times */ 329682011ffSwdenk #define MAMR_RLFA_13X 0x00000D00 /* The Read Loop is executed 13 times */ 330682011ffSwdenk #define MAMR_RLFA_14X 0x00000E00 /* The Read Loop is executed 14 times */ 331682011ffSwdenk #define MAMR_RLFA_15X 0x00000F00 /* The Read Loop is executed 15 times */ 3320669d4d3Swdenk #define MAMR_RLFA_16X 0x00000000 /* The Read Loop is executed 16 times */ 333682011ffSwdenk #define MAMR_WLFA_MSK 0x000000F0 /* Write Loop Field A mask */ 3340669d4d3Swdenk #define MAMR_WLFA_1X 0x00000010 /* The Write Loop is executed 1 time */ 3350669d4d3Swdenk #define MAMR_WLFA_2X 0x00000020 /* The Write Loop is executed 2 times */ 3360669d4d3Swdenk #define MAMR_WLFA_3X 0x00000030 /* The Write Loop is executed 3 times */ 3370669d4d3Swdenk #define MAMR_WLFA_4X 0x00000040 /* The Write Loop is executed 4 times */ 3380669d4d3Swdenk #define MAMR_WLFA_5X 0x00000050 /* The Write Loop is executed 5 times */ 3390669d4d3Swdenk #define MAMR_WLFA_6X 0x00000060 /* The Write Loop is executed 6 times */ 3400669d4d3Swdenk #define MAMR_WLFA_7X 0x00000070 /* The Write Loop is executed 7 times */ 3410669d4d3Swdenk #define MAMR_WLFA_8X 0x00000080 /* The Write Loop is executed 8 times */ 3420669d4d3Swdenk #define MAMR_WLFA_9X 0x00000090 /* The Write Loop is executed 9 times */ 343682011ffSwdenk #define MAMR_WLFA_10X 0x000000A0 /* The Write Loop is executed 10 times */ 344682011ffSwdenk #define MAMR_WLFA_11X 0x000000B0 /* The Write Loop is executed 11 times */ 345682011ffSwdenk #define MAMR_WLFA_12X 0x000000C0 /* The Write Loop is executed 12 times */ 346682011ffSwdenk #define MAMR_WLFA_13X 0x000000D0 /* The Write Loop is executed 13 times */ 347682011ffSwdenk #define MAMR_WLFA_14X 0x000000E0 /* The Write Loop is executed 14 times */ 348682011ffSwdenk #define MAMR_WLFA_15X 0x000000F0 /* The Write Loop is executed 15 times */ 3490669d4d3Swdenk #define MAMR_WLFA_16X 0x00000000 /* The Write Loop is executed 16 times */ 350682011ffSwdenk #define MAMR_TLFA_MSK 0x0000000F /* Timer Loop Field A mask */ 3510669d4d3Swdenk #define MAMR_TLFA_1X 0x00000001 /* The Timer Loop is executed 1 time */ 3520669d4d3Swdenk #define MAMR_TLFA_2X 0x00000002 /* The Timer Loop is executed 2 times */ 3530669d4d3Swdenk #define MAMR_TLFA_3X 0x00000003 /* The Timer Loop is executed 3 times */ 3540669d4d3Swdenk #define MAMR_TLFA_4X 0x00000004 /* The Timer Loop is executed 4 times */ 3550669d4d3Swdenk #define MAMR_TLFA_5X 0x00000005 /* The Timer Loop is executed 5 times */ 3560669d4d3Swdenk #define MAMR_TLFA_6X 0x00000006 /* The Timer Loop is executed 6 times */ 3570669d4d3Swdenk #define MAMR_TLFA_7X 0x00000007 /* The Timer Loop is executed 7 times */ 3580669d4d3Swdenk #define MAMR_TLFA_8X 0x00000008 /* The Timer Loop is executed 8 times */ 3590669d4d3Swdenk #define MAMR_TLFA_9X 0x00000009 /* The Timer Loop is executed 9 times */ 360682011ffSwdenk #define MAMR_TLFA_10X 0x0000000A /* The Timer Loop is executed 10 times */ 361682011ffSwdenk #define MAMR_TLFA_11X 0x0000000B /* The Timer Loop is executed 11 times */ 362682011ffSwdenk #define MAMR_TLFA_12X 0x0000000C /* The Timer Loop is executed 12 times */ 363682011ffSwdenk #define MAMR_TLFA_13X 0x0000000D /* The Timer Loop is executed 13 times */ 364682011ffSwdenk #define MAMR_TLFA_14X 0x0000000E /* The Timer Loop is executed 14 times */ 365682011ffSwdenk #define MAMR_TLFA_15X 0x0000000F /* The Timer Loop is executed 15 times */ 3660669d4d3Swdenk #define MAMR_TLFA_16X 0x00000000 /* The Timer Loop is executed 16 times */ 3670669d4d3Swdenk 3680669d4d3Swdenk /*----------------------------------------------------------------------- 3690669d4d3Swdenk * Machine B Mode Register 16-13 3700669d4d3Swdenk */ 3712535d602Swdenk #define MBMR_PTB_MSK 0xFF000000 /* Periodic Timer B period mask */ 3722535d602Swdenk #define MBMR_PTB_SHIFT 0x00000018 /* Periodic Timer B period shift */ 3732535d602Swdenk #define MBMR_PTBE 0x00800000 /* Periodic Timer B Enable */ 3742535d602Swdenk #define MBMR_AMB_MSK 0x00700000 /* Addess Multiplex size B */ 3752535d602Swdenk #define MBMR_AMB_TYPE_0 0x00000000 /* Addess Multiplexing Type 0 */ 3762535d602Swdenk #define MBMR_AMB_TYPE_1 0x00100000 /* Addess Multiplexing Type 1 */ 3772535d602Swdenk #define MBMR_AMB_TYPE_2 0x00200000 /* Addess Multiplexing Type 2 */ 3782535d602Swdenk #define MBMR_AMB_TYPE_3 0x00300000 /* Addess Multiplexing Type 3 */ 3792535d602Swdenk #define MBMR_AMB_TYPE_4 0x00400000 /* Addess Multiplexing Type 4 */ 3802535d602Swdenk #define MBMR_AMB_TYPE_5 0x00500000 /* Addess Multiplexing Type 5 */ 3812535d602Swdenk #define MBMR_DSB_MSK 0x00060000 /* Disable Timer period mask */ 3822535d602Swdenk #define MBMR_DSB_1_CYCL 0x00000000 /* 1 cycle Disable Period */ 3832535d602Swdenk #define MBMR_DSB_2_CYCL 0x00020000 /* 2 cycle Disable Period */ 3842535d602Swdenk #define MBMR_DSB_3_CYCL 0x00040000 /* 3 cycle Disable Period */ 3852535d602Swdenk #define MBMR_DSB_4_CYCL 0x00060000 /* 4 cycle Disable Period */ 3862535d602Swdenk #define MBMR_G0CLB_MSK 0x0000E000 /* General Line 0 Control B */ 3872535d602Swdenk #define MBMR_G0CLB_A12 0x00000000 /* General Line 0 : A12 */ 3882535d602Swdenk #define MBMR_G0CLB_A11 0x00002000 /* General Line 0 : A11 */ 3892535d602Swdenk #define MBMR_G0CLB_A10 0x00004000 /* General Line 0 : A10 */ 3902535d602Swdenk #define MBMR_G0CLB_A9 0x00006000 /* General Line 0 : A9 */ 3912535d602Swdenk #define MBMR_G0CLB_A8 0x00008000 /* General Line 0 : A8 */ 3922535d602Swdenk #define MBMR_G0CLB_A7 0x0000A000 /* General Line 0 : A7 */ 3932535d602Swdenk #define MBMR_G0CLB_A6 0x0000C000 /* General Line 0 : A6 */ 3942535d602Swdenk #define MBMR_G0CLB_A5 0x0000E000 /* General Line 0 : A5 */ 3952535d602Swdenk #define MBMR_GPL_B4DIS 0x00001000 /* GPL_B4 ouput line Disable */ 3962535d602Swdenk #define MBMR_RLFB_MSK 0x00000F00 /* Read Loop Field B mask */ 3972535d602Swdenk #define MBMR_RLFB_1X 0x00000100 /* The Read Loop is executed 1 time */ 3982535d602Swdenk #define MBMR_RLFB_2X 0x00000200 /* The Read Loop is executed 2 times */ 3992535d602Swdenk #define MBMR_RLFB_3X 0x00000300 /* The Read Loop is executed 3 times */ 4002535d602Swdenk #define MBMR_RLFB_4X 0x00000400 /* The Read Loop is executed 4 times */ 4012535d602Swdenk #define MBMR_RLFB_5X 0x00000500 /* The Read Loop is executed 5 times */ 4022535d602Swdenk #define MBMR_RLFB_6X 0x00000600 /* The Read Loop is executed 6 times */ 4032535d602Swdenk #define MBMR_RLFB_7X 0x00000700 /* The Read Loop is executed 7 times */ 4042535d602Swdenk #define MBMR_RLFB_8X 0x00000800 /* The Read Loop is executed 8 times */ 4052535d602Swdenk #define MBMR_RLFB_9X 0x00000900 /* The Read Loop is executed 9 times */ 4062535d602Swdenk #define MBMR_RLFB_10X 0x00000A00 /* The Read Loop is executed 10 times */ 4072535d602Swdenk #define MBMR_RLFB_11X 0x00000B00 /* The Read Loop is executed 11 times */ 4082535d602Swdenk #define MBMR_RLFB_12X 0x00000C00 /* The Read Loop is executed 12 times */ 4092535d602Swdenk #define MBMR_RLFB_13X 0x00000D00 /* The Read Loop is executed 13 times */ 4102535d602Swdenk #define MBMR_RLFB_14X 0x00000E00 /* The Read Loop is executed 14 times */ 4112535d602Swdenk #define MBMR_RLFB_15X 0x00000f00 /* The Read Loop is executed 15 times */ 4122535d602Swdenk #define MBMR_RLFB_16X 0x00000000 /* The Read Loop is executed 16 times */ 4132535d602Swdenk #define MBMR_WLFB_MSK 0x000000F0 /* Write Loop Field B mask */ 4142535d602Swdenk #define MBMR_WLFB_1X 0x00000010 /* The Write Loop is executed 1 time */ 4152535d602Swdenk #define MBMR_WLFB_2X 0x00000020 /* The Write Loop is executed 2 times */ 4162535d602Swdenk #define MBMR_WLFB_3X 0x00000030 /* The Write Loop is executed 3 times */ 4172535d602Swdenk #define MBMR_WLFB_4X 0x00000040 /* The Write Loop is executed 4 times */ 4182535d602Swdenk #define MBMR_WLFB_5X 0x00000050 /* The Write Loop is executed 5 times */ 4192535d602Swdenk #define MBMR_WLFB_6X 0x00000060 /* The Write Loop is executed 6 times */ 4202535d602Swdenk #define MBMR_WLFB_7X 0x00000070 /* The Write Loop is executed 7 times */ 4212535d602Swdenk #define MBMR_WLFB_8X 0x00000080 /* The Write Loop is executed 8 times */ 4222535d602Swdenk #define MBMR_WLFB_9X 0x00000090 /* The Write Loop is executed 9 times */ 4232535d602Swdenk #define MBMR_WLFB_10X 0x000000A0 /* The Write Loop is executed 10 times */ 4242535d602Swdenk #define MBMR_WLFB_11X 0x000000B0 /* The Write Loop is executed 11 times */ 4252535d602Swdenk #define MBMR_WLFB_12X 0x000000C0 /* The Write Loop is executed 12 times */ 4262535d602Swdenk #define MBMR_WLFB_13X 0x000000D0 /* The Write Loop is executed 13 times */ 4272535d602Swdenk #define MBMR_WLFB_14X 0x000000E0 /* The Write Loop is executed 14 times */ 4282535d602Swdenk #define MBMR_WLFB_15X 0x000000F0 /* The Write Loop is executed 15 times */ 4292535d602Swdenk #define MBMR_WLFB_16X 0x00000000 /* The Write Loop is executed 16 times */ 4302535d602Swdenk #define MBMR_TLFB_MSK 0x0000000F /* Timer Loop Field B mask */ 4312535d602Swdenk #define MBMR_TLFB_1X 0x00000001 /* The Timer Loop is executed 1 time */ 4322535d602Swdenk #define MBMR_TLFB_2X 0x00000002 /* The Timer Loop is executed 2 times */ 4332535d602Swdenk #define MBMR_TLFB_3X 0x00000003 /* The Timer Loop is executed 3 times */ 4342535d602Swdenk #define MBMR_TLFB_4X 0x00000004 /* The Timer Loop is executed 4 times */ 4352535d602Swdenk #define MBMR_TLFB_5X 0x00000005 /* The Timer Loop is executed 5 times */ 4362535d602Swdenk #define MBMR_TLFB_6X 0x00000006 /* The Timer Loop is executed 6 times */ 4372535d602Swdenk #define MBMR_TLFB_7X 0x00000007 /* The Timer Loop is executed 7 times */ 4382535d602Swdenk #define MBMR_TLFB_8X 0x00000008 /* The Timer Loop is executed 8 times */ 4392535d602Swdenk #define MBMR_TLFB_9X 0x00000009 /* The Timer Loop is executed 9 times */ 4402535d602Swdenk #define MBMR_TLFB_10X 0x0000000A /* The Timer Loop is executed 10 times */ 4412535d602Swdenk #define MBMR_TLFB_11X 0x0000000B /* The Timer Loop is executed 11 times */ 4422535d602Swdenk #define MBMR_TLFB_12X 0x0000000C /* The Timer Loop is executed 12 times */ 4432535d602Swdenk #define MBMR_TLFB_13X 0x0000000D /* The Timer Loop is executed 13 times */ 4442535d602Swdenk #define MBMR_TLFB_14X 0x0000000E /* The Timer Loop is executed 14 times */ 4452535d602Swdenk #define MBMR_TLFB_15X 0x0000000F /* The Timer Loop is executed 15 times */ 4462535d602Swdenk #define MBMR_TLFB_16X 0x00000000 /* The Timer Loop is executed 16 times */ 4470669d4d3Swdenk 4480669d4d3Swdenk /*----------------------------------------------------------------------- 4490669d4d3Swdenk * Timer Global Configuration Register 18-8 4500669d4d3Swdenk */ 4510669d4d3Swdenk #define TGCR_CAS4 0x8000 /* Cascade Timer 3 and 4 */ 4520669d4d3Swdenk #define TGCR_FRZ4 0x4000 /* Freeze timer 4 */ 4530669d4d3Swdenk #define TGCR_STP4 0x2000 /* Stop timer 4 */ 4540669d4d3Swdenk #define TGCR_RST4 0x1000 /* Reset timer 4 */ 4550669d4d3Swdenk #define TGCR_GM2 0x0800 /* Gate Mode for Pin 2 */ 4560669d4d3Swdenk #define TGCR_FRZ3 0x0400 /* Freeze timer 3 */ 4570669d4d3Swdenk #define TGCR_STP3 0x0200 /* Stop timer 3 */ 4580669d4d3Swdenk #define TGCR_RST3 0x0100 /* Reset timer 3 */ 4590669d4d3Swdenk #define TGCR_CAS2 0x0080 /* Cascade Timer 1 and 2 */ 4600669d4d3Swdenk #define TGCR_FRZ2 0x0040 /* Freeze timer 2 */ 4610669d4d3Swdenk #define TGCR_STP2 0x0020 /* Stop timer 2 */ 4620669d4d3Swdenk #define TGCR_RST2 0x0010 /* Reset timer 2 */ 4630669d4d3Swdenk #define TGCR_GM1 0x0008 /* Gate Mode for Pin 1 */ 4640669d4d3Swdenk #define TGCR_FRZ1 0x0004 /* Freeze timer 1 */ 4650669d4d3Swdenk #define TGCR_STP1 0x0002 /* Stop timer 1 */ 4660669d4d3Swdenk #define TGCR_RST1 0x0001 /* Reset timer 1 */ 4670669d4d3Swdenk 4680669d4d3Swdenk 4690669d4d3Swdenk /*----------------------------------------------------------------------- 4700669d4d3Swdenk * Timer Mode Register 18-9 4710669d4d3Swdenk */ 472682011ffSwdenk #define TMR_PS_MSK 0xFF00 /* Prescaler Value */ 4730669d4d3Swdenk #define TMR_PS_SHIFT 8 /* Prescaler position */ 474682011ffSwdenk #define TMR_CE_MSK 0x00C0 /* Capture Edge and Enable Interrupt */ 4750669d4d3Swdenk #define TMR_CE_INTR_DIS 0x0000 /* Disable Interrupt on capture event */ 4760669d4d3Swdenk #define TMR_CE_RISING 0x0040 /* Capture on Rising TINx edge only */ 4770669d4d3Swdenk #define TMR_CE_FALLING 0x0080 /* Capture on Falling TINx edge only */ 478682011ffSwdenk #define TMR_CE_ANY 0x00C0 /* Capture on any TINx edge */ 4790669d4d3Swdenk #define TMR_OM 0x0020 /* Output Mode */ 4800669d4d3Swdenk #define TMR_ORI 0x0010 /* Output Reference Interrupt Enable */ 4810669d4d3Swdenk #define TMR_FRR 0x0008 /* Free Run/Restart */ 4820669d4d3Swdenk #define TMR_ICLK_MSK 0x0006 /* Timer Input Clock Source mask */ 4830669d4d3Swdenk #define TMR_ICLK_IN_CAS 0x0000 /* Internally cascaded input */ 4840669d4d3Swdenk #define TMR_ICLK_IN_GEN 0x0002 /* Internal General system clock */ 4850669d4d3Swdenk #define TMR_ICLK_IN_GEN_DIV16 0x0004 /* Internal General system clk div 16 */ 4860669d4d3Swdenk #define TMR_ICLK_TIN_PIN 0x0006 /* TINx pin */ 4870669d4d3Swdenk #define TMR_GE 0x0001 /* Gate Enable */ 4880669d4d3Swdenk 4890669d4d3Swdenk 4900669d4d3Swdenk /*----------------------------------------------------------------------- 4910669d4d3Swdenk * I2C Controller Registers 4920669d4d3Swdenk */ 4930669d4d3Swdenk #define I2MOD_REVD 0x20 /* Reverese Data */ 4940669d4d3Swdenk #define I2MOD_GCD 0x10 /* General Call Disable */ 4950669d4d3Swdenk #define I2MOD_FLT 0x08 /* Clock Filter */ 4960669d4d3Swdenk #define I2MOD_PDIV32 0x00 /* Pre-Divider 32 */ 4970669d4d3Swdenk #define I2MOD_PDIV16 0x02 /* Pre-Divider 16 */ 4980669d4d3Swdenk #define I2MOD_PDIV8 0x04 /* Pre-Divider 8 */ 4990669d4d3Swdenk #define I2MOD_PDIV4 0x06 /* Pre-Divider 4 */ 5000669d4d3Swdenk #define I2MOD_EN 0x01 /* Enable */ 5010669d4d3Swdenk 5020669d4d3Swdenk #define I2CER_TXE 0x10 /* Tx Error */ 5030669d4d3Swdenk #define I2CER_BSY 0x04 /* Busy Condition */ 5040669d4d3Swdenk #define I2CER_TXB 0x02 /* Tx Buffer Transmitted */ 5050669d4d3Swdenk #define I2CER_RXB 0x01 /* Rx Buffer Received */ 5060669d4d3Swdenk #define I2CER_ALL (I2CER_TXE | I2CER_BSY | I2CER_TXB | I2CER_RXB) 5070669d4d3Swdenk 5080669d4d3Swdenk #define I2COM_STR 0x80 /* Start Transmit */ 5090669d4d3Swdenk #define I2COM_MASTER 0x01 /* Master mode */ 5100669d4d3Swdenk 5110669d4d3Swdenk /*----------------------------------------------------------------------- 5120669d4d3Swdenk * SPI Controller Registers 31-10 5130669d4d3Swdenk */ 5140669d4d3Swdenk #define SPI_EMASK 0x37 /* Event Mask */ 5150669d4d3Swdenk #define SPI_MME 0x20 /* Multi-Master Error */ 5160669d4d3Swdenk #define SPI_TXE 0x10 /* Transmit Error */ 5170669d4d3Swdenk #define SPI_BSY 0x04 /* Busy */ 5180669d4d3Swdenk #define SPI_TXB 0x02 /* Tx Buffer Empty */ 5190669d4d3Swdenk #define SPI_RXB 0x01 /* RX Buffer full/closed */ 5200669d4d3Swdenk 5210669d4d3Swdenk #define SPI_STR 0x80 /* SPCOM: Start transmit */ 5220669d4d3Swdenk 5230669d4d3Swdenk /*----------------------------------------------------------------------- 5240669d4d3Swdenk * PCMCIA Interface General Control Register 17-12 5250669d4d3Swdenk */ 5260669d4d3Swdenk #define PCMCIA_GCRX_CXRESET 0x00000040 5270669d4d3Swdenk #define PCMCIA_GCRX_CXOE 0x00000080 5280669d4d3Swdenk 5290669d4d3Swdenk #define PCMCIA_VS1(slot) (0x80000000 >> (slot << 4)) 5300669d4d3Swdenk #define PCMCIA_VS2(slot) (0x40000000 >> (slot << 4)) 531682011ffSwdenk #define PCMCIA_VS_MASK(slot) (0xC0000000 >> (slot << 4)) 5320669d4d3Swdenk #define PCMCIA_VS_SHIFT(slot) (30 - (slot << 4)) 5330669d4d3Swdenk 5340669d4d3Swdenk #define PCMCIA_WP(slot) (0x20000000 >> (slot << 4)) 5350669d4d3Swdenk #define PCMCIA_CD2(slot) (0x10000000 >> (slot << 4)) 5360669d4d3Swdenk #define PCMCIA_CD1(slot) (0x08000000 >> (slot << 4)) 5370669d4d3Swdenk #define PCMCIA_BVD2(slot) (0x04000000 >> (slot << 4)) 5380669d4d3Swdenk #define PCMCIA_BVD1(slot) (0x02000000 >> (slot << 4)) 5390669d4d3Swdenk #define PCMCIA_RDY(slot) (0x01000000 >> (slot << 4)) 5400669d4d3Swdenk #define PCMCIA_RDY_L(slot) (0x00800000 >> (slot << 4)) 5410669d4d3Swdenk #define PCMCIA_RDY_H(slot) (0x00400000 >> (slot << 4)) 5420669d4d3Swdenk #define PCMCIA_RDY_R(slot) (0x00200000 >> (slot << 4)) 5430669d4d3Swdenk #define PCMCIA_RDY_F(slot) (0x00100000 >> (slot << 4)) 5440669d4d3Swdenk #define PCMCIA_MASK(slot) (0xFFFF0000 >> (slot << 4)) 5450669d4d3Swdenk 5460669d4d3Swdenk /*----------------------------------------------------------------------- 5470669d4d3Swdenk * PCMCIA Option Register Definitions 5480669d4d3Swdenk * 5490669d4d3Swdenk * Bank Sizes: 5500669d4d3Swdenk */ 5510669d4d3Swdenk #define PCMCIA_BSIZE_1 0x00000000 /* Bank size: 1 Bytes */ 5520669d4d3Swdenk #define PCMCIA_BSIZE_2 0x08000000 /* Bank size: 2 Bytes */ 5530669d4d3Swdenk #define PCMCIA_BSIZE_4 0x18000000 /* Bank size: 4 Bytes */ 5540669d4d3Swdenk #define PCMCIA_BSIZE_8 0x10000000 /* Bank size: 8 Bytes */ 5550669d4d3Swdenk #define PCMCIA_BSIZE_16 0x30000000 /* Bank size: 16 Bytes */ 5560669d4d3Swdenk #define PCMCIA_BSIZE_32 0x38000000 /* Bank size: 32 Bytes */ 5570669d4d3Swdenk #define PCMCIA_BSIZE_64 0x28000000 /* Bank size: 64 Bytes */ 5580669d4d3Swdenk #define PCMCIA_BSIZE_128 0x20000000 /* Bank size: 128 Bytes */ 5590669d4d3Swdenk #define PCMCIA_BSIZE_256 0x60000000 /* Bank size: 256 Bytes */ 5600669d4d3Swdenk #define PCMCIA_BSIZE_512 0x68000000 /* Bank size: 512 Bytes */ 5610669d4d3Swdenk #define PCMCIA_BSIZE_1K 0x78000000 /* Bank size: 1 kB */ 5620669d4d3Swdenk #define PCMCIA_BSIZE_2K 0x70000000 /* Bank size: 2 kB */ 5630669d4d3Swdenk #define PCMCIA_BSIZE_4K 0x50000000 /* Bank size: 4 kB */ 5640669d4d3Swdenk #define PCMCIA_BSIZE_8K 0x58000000 /* Bank size: 8 kB */ 5650669d4d3Swdenk #define PCMCIA_BSIZE_16K 0x48000000 /* Bank size: 16 kB */ 5660669d4d3Swdenk #define PCMCIA_BSIZE_32K 0x40000000 /* Bank size: 32 kB */ 5670669d4d3Swdenk #define PCMCIA_BSIZE_64K 0xC0000000 /* Bank size: 64 kB */ 5680669d4d3Swdenk #define PCMCIA_BSIZE_128K 0xC8000000 /* Bank size: 128 kB */ 5690669d4d3Swdenk #define PCMCIA_BSIZE_256K 0xD8000000 /* Bank size: 256 kB */ 5700669d4d3Swdenk #define PCMCIA_BSIZE_512K 0xD0000000 /* Bank size: 512 kB */ 5710669d4d3Swdenk #define PCMCIA_BSIZE_1M 0xF0000000 /* Bank size: 1 MB */ 5720669d4d3Swdenk #define PCMCIA_BSIZE_2M 0xF8000000 /* Bank size: 2 MB */ 5730669d4d3Swdenk #define PCMCIA_BSIZE_4M 0xE8000000 /* Bank size: 4 MB */ 5740669d4d3Swdenk #define PCMCIA_BSIZE_8M 0xE0000000 /* Bank size: 8 MB */ 5750669d4d3Swdenk #define PCMCIA_BSIZE_16M 0xA0000000 /* Bank size: 16 MB */ 5760669d4d3Swdenk #define PCMCIA_BSIZE_32M 0xA8000000 /* Bank size: 32 MB */ 5770669d4d3Swdenk #define PCMCIA_BSIZE_64M 0xB8000000 /* Bank size: 64 MB */ 5780669d4d3Swdenk 5790669d4d3Swdenk /* PCMCIA Timing */ 5800669d4d3Swdenk #define PCMCIA_SHT(t) ((t & 0x0F)<<16) /* Strobe Hold Time */ 5810669d4d3Swdenk #define PCMCIA_SST(t) ((t & 0x0F)<<12) /* Strobe Setup Time */ 5820669d4d3Swdenk #define PCMCIA_SL(t) ((t==32) ? 0 : ((t & 0x1F)<<7)) /* Strobe Length */ 5830669d4d3Swdenk 5840669d4d3Swdenk /* PCMCIA Port Sizes */ 5850669d4d3Swdenk #define PCMCIA_PPS_8 0x00000000 /* 8 bit port size */ 5860669d4d3Swdenk #define PCMCIA_PPS_16 0x00000040 /* 16 bit port size */ 5870669d4d3Swdenk 5880669d4d3Swdenk /* PCMCIA Region Select */ 5890669d4d3Swdenk #define PCMCIA_PRS_MEM 0x00000000 /* Common Memory Space */ 5900669d4d3Swdenk #define PCMCIA_PRS_ATTR 0x00000010 /* Attribute Space */ 5910669d4d3Swdenk #define PCMCIA_PRS_IO 0x00000018 /* I/O Space */ 5920669d4d3Swdenk #define PCMCIA_PRS_DMA 0x00000020 /* DMA, normal transfer */ 5930669d4d3Swdenk #define PCMCIA_PRS_DMA_LAST 0x00000028 /* DMA, last transactn */ 5940669d4d3Swdenk #define PCMCIA_PRS_CEx 0x00000030 /* A[22:23] ==> CE1,CE2 */ 5950669d4d3Swdenk 5960669d4d3Swdenk #define PCMCIA_PSLOT_A 0x00000000 /* Slot A */ 5970669d4d3Swdenk #define PCMCIA_PSLOT_B 0x00000004 /* Slot B */ 5980669d4d3Swdenk #define PCMCIA_WPROT 0x00000002 /* Write Protect */ 5990669d4d3Swdenk #define PCMCIA_PV 0x00000001 /* Valid Bit */ 6000669d4d3Swdenk 6010669d4d3Swdenk #define UPMA 0x00000000 6020669d4d3Swdenk #define UPMB 0x00800000 6030669d4d3Swdenk 6040669d4d3Swdenk #endif /* __MPCXX_H__ */ 605