142d1f039Swdenk /* 261a21e98SAndy Fleming * Copyright 2004, 2007 Freescale Semiconductor. 342d1f039Swdenk * Copyright(c) 2003 Motorola Inc. 442d1f039Swdenk */ 542d1f039Swdenk 642d1f039Swdenk #ifndef __MPC85xx_H__ 742d1f039Swdenk #define __MPC85xx_H__ 842d1f039Swdenk 961a21e98SAndy Fleming /* define for common ppc_asm.tmpl */ 1061a21e98SAndy Fleming #define EXC_OFF_SYS_RESET 0x100 /* System reset */ 1161a21e98SAndy Fleming #define _START_OFFSET 0 1242d1f039Swdenk 1342d1f039Swdenk #if defined(CONFIG_E500) 1442d1f039Swdenk #include <e500.h> 1542d1f039Swdenk #endif 1642d1f039Swdenk 170ac6f8b7Swdenk /* 180ac6f8b7Swdenk * SCCR - System Clock Control Register, 9-8 1942d1f039Swdenk */ 2042d1f039Swdenk #define SCCR_CLPD 0x00000004 /* CPM Low Power Disable */ 210ac6f8b7Swdenk #define SCCR_DFBRG_MSK 0x00000003 /* Division by BRGCLK Mask */ 2242d1f039Swdenk #define SCCR_DFBRG_SHIFT 0 2342d1f039Swdenk 2442d1f039Swdenk #define SCCR_DFBRG00 0x00000000 /* BRGCLK division by 4 */ 250ac6f8b7Swdenk #define SCCR_DFBRG01 0x00000001 /* BRGCLK div by 16 (normal) */ 2642d1f039Swdenk #define SCCR_DFBRG10 0x00000002 /* BRGCLK division by 64 */ 2742d1f039Swdenk #define SCCR_DFBRG11 0x00000003 /* BRGCLK division by 256 */ 2842d1f039Swdenk 29*e46fedfeSTimur Tabi /* 30*e46fedfeSTimur Tabi * Define default values for some CCSR macros to make header files cleaner* 31*e46fedfeSTimur Tabi * 32*e46fedfeSTimur Tabi * To completely disable CCSR relocation in a board header file, define 33*e46fedfeSTimur Tabi * CONFIG_SYS_CCSR_DO_NOT_RELOCATE. This will force CONFIG_SYS_CCSRBAR_PHYS 34*e46fedfeSTimur Tabi * to a value that is the same as CONFIG_SYS_CCSRBAR. 35*e46fedfeSTimur Tabi */ 36*e46fedfeSTimur Tabi 37*e46fedfeSTimur Tabi #ifdef CONFIG_SYS_CCSRBAR_PHYS 38*e46fedfeSTimur Tabi #error "Do not define CONFIG_SYS_CCSRBAR_PHYS directly. Use \ 39*e46fedfeSTimur Tabi CONFIG_SYS_CCSRBAR_PHYS_LOW and/or CONFIG_SYS_CCSRBAR_PHYS_HIGH instead." 40*e46fedfeSTimur Tabi #endif 41*e46fedfeSTimur Tabi 42*e46fedfeSTimur Tabi #ifdef CONFIG_SYS_CCSR_DO_NOT_RELOCATE 43*e46fedfeSTimur Tabi #undef CONFIG_SYS_CCSRBAR_PHYS_HIGH 44*e46fedfeSTimur Tabi #undef CONFIG_SYS_CCSRBAR_PHYS_LOW 45*e46fedfeSTimur Tabi #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0 46*e46fedfeSTimur Tabi #endif 47*e46fedfeSTimur Tabi 48*e46fedfeSTimur Tabi #ifndef CONFIG_SYS_CCSRBAR 49*e46fedfeSTimur Tabi #define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT 50*e46fedfeSTimur Tabi #endif 51*e46fedfeSTimur Tabi 52*e46fedfeSTimur Tabi #ifndef CONFIG_SYS_CCSRBAR_PHYS_HIGH 53*e46fedfeSTimur Tabi #ifdef CONFIG_PHYS_64BIT 54*e46fedfeSTimur Tabi #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0xf 55*e46fedfeSTimur Tabi #else 56*e46fedfeSTimur Tabi #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0 57*e46fedfeSTimur Tabi #endif 58*e46fedfeSTimur Tabi #endif 59*e46fedfeSTimur Tabi 60*e46fedfeSTimur Tabi #ifndef CONFIG_SYS_CCSRBAR_PHYS_LOW 61*e46fedfeSTimur Tabi #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT 62*e46fedfeSTimur Tabi #endif 63*e46fedfeSTimur Tabi 64*e46fedfeSTimur Tabi #define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \ 65*e46fedfeSTimur Tabi CONFIG_SYS_CCSRBAR_PHYS_LOW) 66*e46fedfeSTimur Tabi 67*e46fedfeSTimur Tabi #ifndef CONFIG_SYS_IMMR 68*e46fedfeSTimur Tabi #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR 69*e46fedfeSTimur Tabi #endif 70*e46fedfeSTimur Tabi 7142d1f039Swdenk #endif /* __MPC85xx_H__ */ 72