142d1f039Swdenk /* 2*61a21e98SAndy Fleming * Copyright 2004, 2007 Freescale Semiconductor. 342d1f039Swdenk * Copyright(c) 2003 Motorola Inc. 442d1f039Swdenk */ 542d1f039Swdenk 642d1f039Swdenk #ifndef __MPC85xx_H__ 742d1f039Swdenk #define __MPC85xx_H__ 842d1f039Swdenk 9*61a21e98SAndy Fleming /* define for common ppc_asm.tmpl */ 10*61a21e98SAndy Fleming #define EXC_OFF_SYS_RESET 0x100 /* System reset */ 11*61a21e98SAndy Fleming #define _START_OFFSET 0 1242d1f039Swdenk 1342d1f039Swdenk #if defined(CONFIG_E500) 1442d1f039Swdenk #include <e500.h> 1542d1f039Swdenk #endif 1642d1f039Swdenk 170ac6f8b7Swdenk /* 180ac6f8b7Swdenk * SCCR - System Clock Control Register, 9-8 1942d1f039Swdenk */ 2042d1f039Swdenk #define SCCR_CLPD 0x00000004 /* CPM Low Power Disable */ 210ac6f8b7Swdenk #define SCCR_DFBRG_MSK 0x00000003 /* Division by BRGCLK Mask */ 2242d1f039Swdenk #define SCCR_DFBRG_SHIFT 0 2342d1f039Swdenk 2442d1f039Swdenk #define SCCR_DFBRG00 0x00000000 /* BRGCLK division by 4 */ 250ac6f8b7Swdenk #define SCCR_DFBRG01 0x00000001 /* BRGCLK div by 16 (normal) */ 2642d1f039Swdenk #define SCCR_DFBRG10 0x00000002 /* BRGCLK division by 64 */ 2742d1f039Swdenk #define SCCR_DFBRG11 0x00000003 /* BRGCLK division by 256 */ 2842d1f039Swdenk 29ca27381dSWolfgang Denk /* 30ca27381dSWolfgang Denk * Local Bus Controller - memory controller registers 31ca27381dSWolfgang Denk */ 32ca27381dSWolfgang Denk #define BRx_V 0x00000001 /* Bank Valid */ 33ca27381dSWolfgang Denk #define BRx_MS_GPCM 0x00000000 /* G.P.C.M. Machine Select */ 34ca27381dSWolfgang Denk #define BRx_MS_SDRAM 0x00000000 /* SDRAM Machine Select */ 35ca27381dSWolfgang Denk #define BRx_MS_UPMA 0x00000080 /* U.P.M.A Machine Select */ 36ca27381dSWolfgang Denk #define BRx_MS_UPMB 0x000000a0 /* U.P.M.B Machine Select */ 37ca27381dSWolfgang Denk #define BRx_MS_UPMC 0x000000c0 /* U.P.M.C Machine Select */ 38ca27381dSWolfgang Denk #define BRx_PS_8 0x00000800 /* 8 bit port size */ 39ca27381dSWolfgang Denk #define BRx_PS_32 0x00001800 /* 32 bit port size */ 40ca27381dSWolfgang Denk #define BRx_BA_MSK 0xffff8000 /* Base Address Mask */ 41ca27381dSWolfgang Denk 42ca27381dSWolfgang Denk #define ORxG_EAD 0x00000001 /* External addr latch delay */ 43ca27381dSWolfgang Denk #define ORxG_EHTR 0x00000002 /* Extended hold time on read */ 44ca27381dSWolfgang Denk #define ORxG_TRLX 0x00000004 /* Timing relaxed */ 45ca27381dSWolfgang Denk #define ORxG_SETA 0x00000008 /* External address termination */ 46ca27381dSWolfgang Denk #define ORxG_SCY_10_CLK 0x000000a0 /* 10 clock cycles wait states */ 47ca27381dSWolfgang Denk #define ORxG_SCY_15_CLK 0x000000f0 /* 15 clock cycles wait states */ 48ca27381dSWolfgang Denk #define ORxG_XACS 0x00000100 /* Extra addr to CS setup */ 49ca27381dSWolfgang Denk #define ORxG_ACS_DIV2 0x00000600 /* CS is output 1/2 a clock later*/ 50ca27381dSWolfgang Denk #define ORxG_CSNT 0x00000800 /* Chip Select Negation Time */ 51ca27381dSWolfgang Denk 52ca27381dSWolfgang Denk #define ORxU_BI 0x00000100 /* Burst Inhibit */ 53ca27381dSWolfgang Denk #define ORxU_AM_MSK 0xffff8000 /* Address Mask Mask */ 54ca27381dSWolfgang Denk 55ca27381dSWolfgang Denk #define MxMR_OP_NORM 0x00000000 /* Normal Operation */ 56ca27381dSWolfgang Denk #define MxMR_DSx_2_CYCL 0x00400000 /* 2 cycle Disable Period */ 57ca27381dSWolfgang Denk #define MxMR_OP_WARR 0x10000000 /* Write to Array */ 58ca27381dSWolfgang Denk #define MxMR_BSEL 0x80000000 /* Bus Select */ 59ca27381dSWolfgang Denk 60ca27381dSWolfgang Denk /* helpers to convert values into an OR address mask (GPCM mode) */ 61ca27381dSWolfgang Denk #define P2SZ_TO_AM(s) ((~((s) - 1)) & 0xffff8000) /* must be pow of 2 */ 62ca27381dSWolfgang Denk #define MEG_TO_AM(m) P2SZ_TO_AM((m) << 20) 63ca27381dSWolfgang Denk 6442d1f039Swdenk #endif /* __MPC85xx_H__ */ 65