1*42d1f039Swdenk /* 2*42d1f039Swdenk * Copyright(c) 2003 Motorola Inc. 3*42d1f039Swdenk * Xianghua Xiao (x.xiao@motorola.com) 4*42d1f039Swdenk */ 5*42d1f039Swdenk 6*42d1f039Swdenk #ifndef __MPC85xx_H__ 7*42d1f039Swdenk #define __MPC85xx_H__ 8*42d1f039Swdenk 9*42d1f039Swdenk #define EXC_OFF_SYS_RESET 0x0100 /* System reset */ 10*42d1f039Swdenk 11*42d1f039Swdenk #if defined(CONFIG_E500) 12*42d1f039Swdenk #include <e500.h> 13*42d1f039Swdenk #endif 14*42d1f039Swdenk 15*42d1f039Swdenk #if defined(CONFIG_DDR_ECC) 16*42d1f039Swdenk void dma_init(void); 17*42d1f039Swdenk uint dma_check(void); 18*42d1f039Swdenk int dma_xfer(void *dest, uint count, void *src); 19*42d1f039Swdenk #endif 20*42d1f039Swdenk /*----------------------------------------------------------------------- 21*42d1f039Swdenk * SCCR - System Clock Control Register 9-8 22*42d1f039Swdenk */ 23*42d1f039Swdenk #define SCCR_CLPD 0x00000004 /* CPM Low Power Disable */ 24*42d1f039Swdenk #define SCCR_DFBRG_MSK 0x00000003 /* Division factor of BRGCLK Mask */ 25*42d1f039Swdenk #define SCCR_DFBRG_SHIFT 0 26*42d1f039Swdenk 27*42d1f039Swdenk #define SCCR_DFBRG00 0x00000000 /* BRGCLK division by 4 */ 28*42d1f039Swdenk #define SCCR_DFBRG01 0x00000001 /* BRGCLK division by 16 (normal op.)*/ 29*42d1f039Swdenk #define SCCR_DFBRG10 0x00000002 /* BRGCLK division by 64 */ 30*42d1f039Swdenk #define SCCR_DFBRG11 0x00000003 /* BRGCLK division by 256 */ 31*42d1f039Swdenk 32*42d1f039Swdenk #endif /* __MPC85xx_H__ */ 33