142d1f039Swdenk /* 2*0ac6f8b7Swdenk * Copyright 2004 Freescale Semiconductor. 342d1f039Swdenk * Copyright(c) 2003 Motorola Inc. 442d1f039Swdenk * Xianghua Xiao (x.xiao@motorola.com) 542d1f039Swdenk */ 642d1f039Swdenk 742d1f039Swdenk #ifndef __MPC85xx_H__ 842d1f039Swdenk #define __MPC85xx_H__ 942d1f039Swdenk 1042d1f039Swdenk #define EXC_OFF_SYS_RESET 0x0100 /* System reset */ 1142d1f039Swdenk 1242d1f039Swdenk #if defined(CONFIG_E500) 1342d1f039Swdenk #include <e500.h> 1442d1f039Swdenk #endif 1542d1f039Swdenk 16*0ac6f8b7Swdenk /* 17*0ac6f8b7Swdenk * SCCR - System Clock Control Register, 9-8 1842d1f039Swdenk */ 1942d1f039Swdenk #define SCCR_CLPD 0x00000004 /* CPM Low Power Disable */ 20*0ac6f8b7Swdenk #define SCCR_DFBRG_MSK 0x00000003 /* Division by BRGCLK Mask */ 2142d1f039Swdenk #define SCCR_DFBRG_SHIFT 0 2242d1f039Swdenk 2342d1f039Swdenk #define SCCR_DFBRG00 0x00000000 /* BRGCLK division by 4 */ 24*0ac6f8b7Swdenk #define SCCR_DFBRG01 0x00000001 /* BRGCLK div by 16 (normal) */ 2542d1f039Swdenk #define SCCR_DFBRG10 0x00000002 /* BRGCLK division by 64 */ 2642d1f039Swdenk #define SCCR_DFBRG11 0x00000003 /* BRGCLK division by 256 */ 2742d1f039Swdenk 2842d1f039Swdenk #endif /* __MPC85xx_H__ */ 29