142d1f039Swdenk /* 261a21e98SAndy Fleming * Copyright 2004, 2007 Freescale Semiconductor. 342d1f039Swdenk * Copyright(c) 2003 Motorola Inc. 442d1f039Swdenk */ 542d1f039Swdenk 642d1f039Swdenk #ifndef __MPC85xx_H__ 742d1f039Swdenk #define __MPC85xx_H__ 842d1f039Swdenk 942d1f039Swdenk #if defined(CONFIG_E500) 1042d1f039Swdenk #include <e500.h> 1142d1f039Swdenk #endif 1242d1f039Swdenk 130ac6f8b7Swdenk /* 140ac6f8b7Swdenk * SCCR - System Clock Control Register, 9-8 1542d1f039Swdenk */ 1642d1f039Swdenk #define SCCR_CLPD 0x00000004 /* CPM Low Power Disable */ 170ac6f8b7Swdenk #define SCCR_DFBRG_MSK 0x00000003 /* Division by BRGCLK Mask */ 1842d1f039Swdenk #define SCCR_DFBRG_SHIFT 0 1942d1f039Swdenk 2042d1f039Swdenk #define SCCR_DFBRG00 0x00000000 /* BRGCLK division by 4 */ 210ac6f8b7Swdenk #define SCCR_DFBRG01 0x00000001 /* BRGCLK div by 16 (normal) */ 2242d1f039Swdenk #define SCCR_DFBRG10 0x00000002 /* BRGCLK division by 64 */ 2342d1f039Swdenk #define SCCR_DFBRG11 0x00000003 /* BRGCLK division by 256 */ 2442d1f039Swdenk 25*e46fedfeSTimur Tabi /* 26*e46fedfeSTimur Tabi * Define default values for some CCSR macros to make header files cleaner* 27*e46fedfeSTimur Tabi * 28*e46fedfeSTimur Tabi * To completely disable CCSR relocation in a board header file, define 29*e46fedfeSTimur Tabi * CONFIG_SYS_CCSR_DO_NOT_RELOCATE. This will force CONFIG_SYS_CCSRBAR_PHYS 30*e46fedfeSTimur Tabi * to a value that is the same as CONFIG_SYS_CCSRBAR. 31*e46fedfeSTimur Tabi */ 32*e46fedfeSTimur Tabi 33*e46fedfeSTimur Tabi #ifdef CONFIG_SYS_CCSRBAR_PHYS 34*e46fedfeSTimur Tabi #error "Do not define CONFIG_SYS_CCSRBAR_PHYS directly. Use \ 35*e46fedfeSTimur Tabi CONFIG_SYS_CCSRBAR_PHYS_LOW and/or CONFIG_SYS_CCSRBAR_PHYS_HIGH instead." 36*e46fedfeSTimur Tabi #endif 37*e46fedfeSTimur Tabi 38*e46fedfeSTimur Tabi #ifdef CONFIG_SYS_CCSR_DO_NOT_RELOCATE 39*e46fedfeSTimur Tabi #undef CONFIG_SYS_CCSRBAR_PHYS_HIGH 40*e46fedfeSTimur Tabi #undef CONFIG_SYS_CCSRBAR_PHYS_LOW 41*e46fedfeSTimur Tabi #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0 42*e46fedfeSTimur Tabi #endif 43*e46fedfeSTimur Tabi 44*e46fedfeSTimur Tabi #ifndef CONFIG_SYS_CCSRBAR 45*e46fedfeSTimur Tabi #define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT 46*e46fedfeSTimur Tabi #endif 47*e46fedfeSTimur Tabi 48*e46fedfeSTimur Tabi #ifndef CONFIG_SYS_CCSRBAR_PHYS_HIGH 49*e46fedfeSTimur Tabi #ifdef CONFIG_PHYS_64BIT 50*e46fedfeSTimur Tabi #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0xf 51*e46fedfeSTimur Tabi #else 52*e46fedfeSTimur Tabi #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0 53*e46fedfeSTimur Tabi #endif 54*e46fedfeSTimur Tabi #endif 55*e46fedfeSTimur Tabi 56*e46fedfeSTimur Tabi #ifndef CONFIG_SYS_CCSRBAR_PHYS_LOW 57*e46fedfeSTimur Tabi #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT 58*e46fedfeSTimur Tabi #endif 59*e46fedfeSTimur Tabi 60*e46fedfeSTimur Tabi #define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \ 61*e46fedfeSTimur Tabi CONFIG_SYS_CCSRBAR_PHYS_LOW) 62*e46fedfeSTimur Tabi 63*e46fedfeSTimur Tabi #ifndef CONFIG_SYS_IMMR 64*e46fedfeSTimur Tabi #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR 65*e46fedfeSTimur Tabi #endif 66*e46fedfeSTimur Tabi 6742d1f039Swdenk #endif /* __MPC85xx_H__ */ 68