1 /* 2 * Copyright (C) 2004-2006 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 /* 24 * mpc83xx.h 25 * 26 * MPC83xx specific definitions 27 */ 28 29 #ifndef __MPC83XX_H__ 30 #define __MPC83XX_H__ 31 32 #include <config.h> 33 #if defined(CONFIG_E300) 34 #include <asm/e300.h> 35 #endif 36 37 /* 38 * MPC83xx cpu provide RCR register to do reset thing specially. easier 39 * to implement 40 */ 41 42 #define MPC83xx_RESET 43 44 /* 45 * System reset offset (PowerPC standard) 46 */ 47 #define EXC_OFF_SYS_RESET 0x0100 48 49 /* 50 * Default Internal Memory Register Space (Freescale recomandation) 51 */ 52 #define CONFIG_DEFAULT_IMMR 0xFF400000 53 54 /* 55 * Watchdog 56 */ 57 #define SWCRR 0x0204 58 #define SWCRR_SWTC 0xFFFF0000 /* Software Watchdog Time Count. */ 59 #define SWCRR_SWEN 0x00000004 /* Watchdog Enable bit. */ 60 #define SWCRR_SWRI 0x00000002 /* Software Watchdog Reset/Interrupt Select bit. */ 61 #define SWCRR_SWPR 0x00000001 /* Software Watchdog Counter Prescale bit. */ 62 #define SWCRR_RES ~(SWCRR_SWTC | SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR) 63 64 #define SWCNR 0x0208 65 #define SWCNR_SWCN 0x0000FFFF Software Watchdog Count Field. 66 #define SWCNR_RES ~(SWCNR_SWCN) 67 68 #define SWSRR 0x020E 69 70 /* 71 * Default Internal Memory Register Space (Freescale recomandation) 72 */ 73 #define IMMRBAR 0x0000 74 #define IMMRBAR_BASE_ADDR 0xFFF00000 /* Identifies the 12 most-significant address bits of the base of the 1 MByte internal memory window. */ 75 #define IMMRBAR_RES ~(IMMRBAR_BASE_ADDR) 76 77 /* 78 * Default Internal Memory Register Space (Freescale recomandation) 79 */ 80 #define LBLAWBAR0 0x0020 81 #define LBLAWAR0 0x0024 82 #define LBLAWBAR1 0x0028 83 #define LBLAWAR1 0x002C 84 #define LBLAWBAR2 0x0030 85 #define LBLAWAR2 0x0034 86 #define LBLAWBAR3 0x0038 87 #define LBLAWAR3 0x003C 88 89 /* 90 * The device ID and revision numbers 91 */ 92 #define SPR_8349E_REV10 0x80300100 93 #define SPR_8349E_REV11 0x80300101 94 95 /* 96 * Base Registers & Option Registers 97 */ 98 #define BR0 0x5000 99 #define BR1 0x5008 100 #define BR2 0x5010 101 #define BR3 0x5018 102 #define BR4 0x5020 103 #define BR5 0x5028 104 #define BR6 0x5030 105 #define BR7 0x5038 106 107 #define BR_BA 0xFFFF8000 108 #define BR_BA_SHIFT 15 109 #define BR_PS 0x00001800 110 #define BR_PS_SHIFT 11 111 #define BR_PS_8 0x00000800 /* Port Size 8 bit */ 112 #define BR_PS_16 0x00001000 /* Port Size 16 bit */ 113 #define BR_PS_32 0x00001800 /* Port Size 32 bit */ 114 #define BR_DECC 0x00000600 115 #define BR_DECC_SHIFT 9 116 #define BR_WP 0x00000100 117 #define BR_WP_SHIFT 8 118 #define BR_MSEL 0x000000E0 119 #define BR_MSEL_SHIFT 5 120 #define BR_MS_GPCM 0x00000000 /* GPCM */ 121 #define BR_MS_SDRAM 0x00000060 /* SDRAM */ 122 #define BR_MS_UPMA 0x00000080 /* UPMA */ 123 #define BR_MS_UPMB 0x000000A0 /* UPMB */ 124 #define BR_MS_UPMC 0x000000C0 /* UPMC */ 125 #define BR_V 0x00000001 126 #define BR_V_SHIFT 0 127 #define BR_RES ~(BR_BA|BR_PS|BR_DECC|BR_WP|BR_MSEL|BR_V) 128 129 #define OR0 0x5004 130 #define OR1 0x500C 131 #define OR2 0x5014 132 #define OR3 0x501C 133 #define OR4 0x5024 134 #define OR5 0x502C 135 #define OR6 0x5034 136 #define OR7 0x503C 137 138 #define OR_GPCM_AM 0xFFFF8000 139 #define OR_GPCM_AM_SHIFT 15 140 #define OR_GPCM_BCTLD 0x00001000 141 #define OR_GPCM_BCTLD_SHIFT 12 142 #define OR_GPCM_CSNT 0x00000800 143 #define OR_GPCM_CSNT_SHIFT 11 144 #define OR_GPCM_ACS 0x00000600 145 #define OR_GPCM_ACS_SHIFT 9 146 #define OR_GPCM_ACS_0b10 0x00000400 147 #define OR_GPCM_ACS_0b11 0x00000600 148 #define OR_GPCM_XACS 0x00000100 149 #define OR_GPCM_XACS_SHIFT 8 150 #define OR_GPCM_SCY 0x000000F0 151 #define OR_GPCM_SCY_SHIFT 4 152 #define OR_GPCM_SCY_1 0x00000010 153 #define OR_GPCM_SCY_2 0x00000020 154 #define OR_GPCM_SCY_3 0x00000030 155 #define OR_GPCM_SCY_4 0x00000040 156 #define OR_GPCM_SCY_5 0x00000050 157 #define OR_GPCM_SCY_6 0x00000060 158 #define OR_GPCM_SCY_7 0x00000070 159 #define OR_GPCM_SCY_8 0x00000080 160 #define OR_GPCM_SCY_9 0x00000090 161 #define OR_GPCM_SCY_10 0x000000a0 162 #define OR_GPCM_SCY_11 0x000000b0 163 #define OR_GPCM_SCY_12 0x000000c0 164 #define OR_GPCM_SCY_13 0x000000d0 165 #define OR_GPCM_SCY_14 0x000000e0 166 #define OR_GPCM_SCY_15 0x000000f0 167 #define OR_GPCM_SETA 0x00000008 168 #define OR_GPCM_SETA_SHIFT 3 169 #define OR_GPCM_TRLX 0x00000004 170 #define OR_GPCM_TRLX_SHIFT 2 171 #define OR_GPCM_EHTR 0x00000002 172 #define OR_GPCM_EHTR_SHIFT 1 173 #define OR_GPCM_EAD 0x00000001 174 #define OR_GPCM_EAD_SHIFT 0 175 176 #define OR_UPM_AM 0xFFFF8000 177 #define OR_UPM_AM_SHIFT 15 178 #define OR_UPM_XAM 0x00006000 179 #define OR_UPM_XAM_SHIFT 13 180 #define OR_UPM_BCTLD 0x00001000 181 #define OR_UPM_BCTLD_SHIFT 12 182 #define OR_UPM_BI 0x00000100 183 #define OR_UPM_BI_SHIFT 8 184 #define OR_UPM_TRLX 0x00000004 185 #define OR_UPM_TRLX_SHIFT 2 186 #define OR_UPM_EHTR 0x00000002 187 #define OR_UPM_EHTR_SHIFT 1 188 #define OR_UPM_EAD 0x00000001 189 #define OR_UPM_EAD_SHIFT 0 190 191 #define OR_SDRAM_AM 0xFFFF8000 192 #define OR_SDRAM_AM_SHIFT 15 193 #define OR_SDRAM_XAM 0x00006000 194 #define OR_SDRAM_XAM_SHIFT 13 195 #define OR_SDRAM_COLS 0x00001C00 196 #define OR_SDRAM_COLS_SHIFT 10 197 #define OR_SDRAM_ROWS 0x000001C0 198 #define OR_SDRAM_ROWS_SHIFT 6 199 #define OR_SDRAM_PMSEL 0x00000020 200 #define OR_SDRAM_PMSEL_SHIFT 5 201 #define OR_SDRAM_EAD 0x00000001 202 #define OR_SDRAM_EAD_SHIFT 0 203 204 /* 205 * Hard Reset Configration Word - High 206 */ 207 #define HRCWH_PCI_AGENT 0x00000000 208 #define HRCWH_PCI_HOST 0x80000000 209 210 #define HRCWH_32_BIT_PCI 0x00000000 211 #define HRCWH_64_BIT_PCI 0x40000000 212 213 #define HRCWH_PCI1_ARBITER_DISABLE 0x00000000 214 #define HRCWH_PCI1_ARBITER_ENABLE 0x20000000 215 216 #define HRCWH_PCI2_ARBITER_DISABLE 0x00000000 217 #define HRCWH_PCI2_ARBITER_ENABLE 0x10000000 218 219 #define HRCWH_CORE_DISABLE 0x08000000 220 #define HRCWH_CORE_ENABLE 0x00000000 221 222 #define HRCWH_FROM_0X00000100 0x00000000 223 #define HRCWH_FROM_0XFFF00100 0x04000000 224 225 #define HRCWH_BOOTSEQ_DISABLE 0x00000000 226 #define HRCWH_BOOTSEQ_NORMAL 0x01000000 227 #define HRCWH_BOOTSEQ_EXTENDED 0x02000000 228 229 #define HRCWH_SW_WATCHDOG_DISABLE 0x00000000 230 #define HRCWH_SW_WATCHDOG_ENABLE 0x00800000 231 232 #define HRCWH_ROM_LOC_DDR_SDRAM 0x00000000 233 #define HRCWH_ROM_LOC_PCI1 0x00100000 234 #define HRCWH_ROM_LOC_PCI2 0x00200000 235 #define HRCWH_ROM_LOC_LOCAL_8BIT 0x00500000 236 #define HRCWH_ROM_LOC_LOCAL_16BIT 0x00600000 237 #define HRCWH_ROM_LOC_LOCAL_32BIT 0x00700000 238 239 #define HRCWH_TSEC1M_IN_RGMII 0x00000000 240 #define HRCWH_TSEC1M_IN_RTBI 0x00004000 241 #define HRCWH_TSEC1M_IN_GMII 0x00008000 242 #define HRCWH_TSEC1M_IN_TBI 0x0000C000 243 244 #define HRCWH_TSEC2M_IN_RGMII 0x00000000 245 #define HRCWH_TSEC2M_IN_RTBI 0x00001000 246 #define HRCWH_TSEC2M_IN_GMII 0x00002000 247 #define HRCWH_TSEC2M_IN_TBI 0x00003000 248 249 #define HRCWH_BIG_ENDIAN 0x00000000 250 #define HRCWH_LITTLE_ENDIAN 0x00000008 251 252 #define HRCWH_LALE_NORMAL 0x00000000 253 #define HRCWH_LALE_EARLY 0x00000004 254 255 #define HRCWH_LDP_SET 0x00000000 256 #define HRCWH_LDP_CLEAR 0x00000002 257 258 /* 259 * Hard Reset Configration Word - Low 260 */ 261 #define HRCWL_LCL_BUS_TO_SCB_CLK_1X1 0x00000000 262 #define HRCWL_LCL_BUS_TO_SCB_CLK_2X1 0x80000000 263 264 #define HRCWL_DDR_TO_SCB_CLK_1X1 0x00000000 265 #define HRCWL_DDR_TO_SCB_CLK_2X1 0x40000000 266 267 #define HRCWL_CSB_TO_CLKIN_16X1 0x00000000 268 #define HRCWL_CSB_TO_CLKIN_1X1 0x01000000 269 #define HRCWL_CSB_TO_CLKIN_2X1 0x02000000 270 #define HRCWL_CSB_TO_CLKIN_3X1 0x03000000 271 #define HRCWL_CSB_TO_CLKIN_4X1 0x04000000 272 #define HRCWL_CSB_TO_CLKIN_5X1 0x05000000 273 #define HRCWL_CSB_TO_CLKIN_6X1 0x06000000 274 #define HRCWL_CSB_TO_CLKIN_7X1 0x07000000 275 #define HRCWL_CSB_TO_CLKIN_8X1 0x08000000 276 #define HRCWL_CSB_TO_CLKIN_9X1 0x09000000 277 #define HRCWL_CSB_TO_CLKIN_10X1 0x0A000000 278 #define HRCWL_CSB_TO_CLKIN_11X1 0x0B000000 279 #define HRCWL_CSB_TO_CLKIN_12X1 0x0C000000 280 #define HRCWL_CSB_TO_CLKIN_13X1 0x0D000000 281 #define HRCWL_CSB_TO_CLKIN_14X1 0x0E000000 282 #define HRCWL_CSB_TO_CLKIN_15X1 0x0F000000 283 284 #define HRCWL_VCO_BYPASS 0x00000000 285 #define HRCWL_VCO_1X2 0x00000000 286 #define HRCWL_VCO_1X4 0x00200000 287 #define HRCWL_VCO_1X8 0x00400000 288 289 #define HRCWL_CORE_TO_CSB_BYPASS 0x00000000 290 #define HRCWL_CORE_TO_CSB_1X1 0x00020000 291 #define HRCWL_CORE_TO_CSB_1_5X1 0x00030000 292 #define HRCWL_CORE_TO_CSB_2X1 0x00040000 293 #define HRCWL_CORE_TO_CSB_2_5X1 0x00050000 294 #define HRCWL_CORE_TO_CSB_3X1 0x00060000 295 296 /* 297 * LCRR - Clock Ratio Register (10.3.1.16) 298 */ 299 #define LCRR_DBYP 0x80000000 300 #define LCRR_DBYP_SHIFT 31 301 #define LCRR_BUFCMDC 0x30000000 302 #define LCRR_BUFCMDC_1 0x10000000 303 #define LCRR_BUFCMDC_2 0x20000000 304 #define LCRR_BUFCMDC_3 0x30000000 305 #define LCRR_BUFCMDC_4 0x00000000 306 #define LCRR_BUFCMDC_SHIFT 28 307 #define LCRR_ECL 0x03000000 308 #define LCRR_ECL_4 0x00000000 309 #define LCRR_ECL_5 0x01000000 310 #define LCRR_ECL_6 0x02000000 311 #define LCRR_ECL_7 0x03000000 312 #define LCRR_ECL_SHIFT 24 313 #define LCRR_EADC 0x00030000 314 #define LCRR_EADC_1 0x00010000 315 #define LCRR_EADC_2 0x00020000 316 #define LCRR_EADC_3 0x00030000 317 #define LCRR_EADC_4 0x00000000 318 #define LCRR_EADC_SHIFT 16 319 #define LCRR_CLKDIV 0x0000000F 320 #define LCRR_CLKDIV_2 0x00000002 321 #define LCRR_CLKDIV_4 0x00000004 322 #define LCRR_CLKDIV_8 0x00000008 323 #define LCRR_CLKDIV_SHIFT 0 324 325 /* 326 * SCCR-System Clock Control Register 327 */ 328 #define SCCR_TSEC1CM_0 0x00000000 329 #define SCCR_TSEC1CM_1 0x40000000 330 #define SCCR_TSEC1CM_2 0x80000000 331 #define SCCR_TSEC1CM_3 0xC0000000 332 #define SCCR_TSEC2CM_0 0x00000000 333 #define SCCR_TSEC2CM_1 0x10000000 334 #define SCCR_TSEC2CM_2 0x20000000 335 #define SCCR_TSEC2CM_3 0x30000000 336 #define SCCR_ENCCM_0 0x00000000 337 #define SCCR_ENCCM_1 0x01000000 338 #define SCCR_ENCCM_2 0x02000000 339 #define SCCR_ENCCM_3 0x03000000 340 #define SCCR_USBCM_0 0x00000000 341 #define SCCR_USBCM_1 0x00500000 342 #define SCCR_USBCM_2 0x00A00000 343 #define SCCR_USBCM_3 0x00F00000 344 345 #define SCCR_CLK_MASK ( SCCR_TSEC1CM_3 \ 346 | SCCR_TSEC2CM_3 \ 347 | SCCR_ENCCM_3 \ 348 | SCCR_USBCM_3 ) 349 #define SCCR_DEFAULT 0xFFFFFFFF 350 351 #endif /* __MPC83XX_H__ */ 352