1 /* 2 * Copyright (C) 2004-2006 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 */ 12 13 #ifndef __MPC83XX_H__ 14 #define __MPC83XX_H__ 15 16 #include <config.h> 17 #if defined(CONFIG_E300) 18 #include <asm/e300.h> 19 #endif 20 21 /* MPC83xx cpu provide RCR register to do reset thing specially 22 */ 23 #define MPC83xx_RESET 24 25 /* System reset offset (PowerPC standard) 26 */ 27 #define EXC_OFF_SYS_RESET 0x0100 28 29 /* IMMRBAR - Internal Memory Register Base Address 30 */ 31 #define CONFIG_DEFAULT_IMMR 0xFF400000 /* Default IMMR base address */ 32 #define IMMRBAR 0x0000 /* Register offset to immr */ 33 #define IMMRBAR_BASE_ADDR 0xFFF00000 /* Base address mask */ 34 #define IMMRBAR_RES ~(IMMRBAR_BASE_ADDR) 35 36 /* LAWBAR - Local Access Window Base Address Register 37 */ 38 #define LBLAWBAR0 0x0020 /* Register offset to immr */ 39 #define LBLAWAR0 0x0024 40 #define LBLAWBAR1 0x0028 41 #define LBLAWAR1 0x002C 42 #define LBLAWBAR2 0x0030 43 #define LBLAWAR2 0x0034 44 #define LBLAWBAR3 0x0038 45 #define LBLAWAR3 0x003C 46 #define LAWBAR_BAR 0xFFFFF000 /* Base address mask */ 47 48 /* SPRIDR - System Part and Revision ID Register 49 */ 50 #define SPRIDR_PARTID 0xFFFF0000 /* Part Identification */ 51 #define SPRIDR_REVID 0x0000FFFF /* Revision Identification */ 52 53 #define SPR_8349E_REV10 0x80300100 54 #define SPR_8349_REV10 0x80310100 55 #define SPR_8347E_REV10_TBGA 0x80320100 56 #define SPR_8347_REV10_TBGA 0x80330100 57 #define SPR_8347E_REV10_PBGA 0x80340100 58 #define SPR_8347_REV10_PBGA 0x80350100 59 #define SPR_8343E_REV10 0x80360100 60 #define SPR_8343_REV10 0x80370100 61 62 #define SPR_8349E_REV11 0x80300101 63 #define SPR_8349_REV11 0x80310101 64 #define SPR_8347E_REV11_TBGA 0x80320101 65 #define SPR_8347_REV11_TBGA 0x80330101 66 #define SPR_8347E_REV11_PBGA 0x80340101 67 #define SPR_8347_REV11_PBGA 0x80350101 68 #define SPR_8343E_REV11 0x80360101 69 #define SPR_8343_REV11 0x80370101 70 71 #define SPR_8360E_REV10 0x80480010 72 #define SPR_8360_REV10 0x80490010 73 #define SPR_8360E_REV11 0x80480011 74 #define SPR_8360_REV11 0x80490011 75 #define SPR_8360E_REV12 0x80480012 76 #define SPR_8360_REV12 0x80490012 77 78 /* SPCR - System Priority Configuration Register 79 */ 80 #define SPCR_PCIHPE 0x10000000 /* PCI Highest Priority Enable */ 81 #define SPCR_PCIHPE_SHIFT (31-3) 82 #define SPCR_PCIPR 0x03000000 /* PCI bridge system bus request priority */ 83 #define SPCR_PCIPR_SHIFT (31-7) 84 #define SPCR_OPT 0x00800000 /* Optimize */ 85 #define SPCR_TBEN 0x00400000 /* E300 PowerPC core time base unit enable */ 86 #define SPCR_TBEN_SHIFT (31-9) 87 #define SPCR_COREPR 0x00300000 /* E300 PowerPC Core system bus request priority */ 88 #define SPCR_COREPR_SHIFT (31-11) 89 90 #if defined(CONFIG_MPC8349) 91 /* SPCR bits - MPC8349 specific */ 92 #define SPCR_TSEC1DP 0x00003000 /* TSEC1 data priority */ 93 #define SPCR_TSEC1DP_SHIFT (31-19) 94 #define SPCR_TSEC1BDP 0x00000C00 /* TSEC1 buffer descriptor priority */ 95 #define SPCR_TSEC1BDP_SHIFT (31-21) 96 #define SPCR_TSEC1EP 0x00000300 /* TSEC1 emergency priority */ 97 #define SPCR_TSEC1EP_SHIFT (31-23) 98 #define SPCR_TSEC2DP 0x00000030 /* TSEC2 data priority */ 99 #define SPCR_TSEC2DP_SHIFT (31-27) 100 #define SPCR_TSEC2BDP 0x0000000C /* TSEC2 buffer descriptor priority */ 101 #define SPCR_TSEC2BDP_SHIFT (31-29) 102 #define SPCR_TSEC2EP 0x00000003 /* TSEC2 emergency priority */ 103 #define SPCR_TSEC2EP_SHIFT (31-31) 104 #endif 105 106 /* SICRL/H - System I/O Configuration Register Low/High 107 */ 108 #if defined(CONFIG_MPC8349) 109 /* SICRL bits - MPC8349 specific */ 110 #define SICRL_LDP_A 0x80000000 111 #define SICRL_USB1 0x40000000 112 #define SICRL_USB0 0x20000000 113 #define SICRL_UART 0x0C000000 114 #define SICRL_GPIO1_A 0x02000000 115 #define SICRL_GPIO1_B 0x01000000 116 #define SICRL_GPIO1_C 0x00800000 117 #define SICRL_GPIO1_D 0x00400000 118 #define SICRL_GPIO1_E 0x00200000 119 #define SICRL_GPIO1_F 0x00180000 120 #define SICRL_GPIO1_G 0x00040000 121 #define SICRL_GPIO1_H 0x00020000 122 #define SICRL_GPIO1_I 0x00010000 123 #define SICRL_GPIO1_J 0x00008000 124 #define SICRL_GPIO1_K 0x00004000 125 #define SICRL_GPIO1_L 0x00003000 126 127 /* SICRH bits - MPC8349 specific */ 128 #define SICRH_DDR 0x80000000 129 #define SICRH_TSEC1_A 0x10000000 130 #define SICRH_TSEC1_B 0x08000000 131 #define SICRH_TSEC1_C 0x04000000 132 #define SICRH_TSEC1_D 0x02000000 133 #define SICRH_TSEC1_E 0x01000000 134 #define SICRH_TSEC1_F 0x00800000 135 #define SICRH_TSEC2_A 0x00400000 136 #define SICRH_TSEC2_B 0x00200000 137 #define SICRH_TSEC2_C 0x00100000 138 #define SICRH_TSEC2_D 0x00080000 139 #define SICRH_TSEC2_E 0x00040000 140 #define SICRH_TSEC2_F 0x00020000 141 #define SICRH_TSEC2_G 0x00010000 142 #define SICRH_TSEC2_H 0x00008000 143 #define SICRH_GPIO2_A 0x00004000 144 #define SICRH_GPIO2_B 0x00002000 145 #define SICRH_GPIO2_C 0x00001000 146 #define SICRH_GPIO2_D 0x00000800 147 #define SICRH_GPIO2_E 0x00000400 148 #define SICRH_GPIO2_F 0x00000200 149 #define SICRH_GPIO2_G 0x00000180 150 #define SICRH_GPIO2_H 0x00000060 151 #define SICRH_TSOBI1 0x00000002 152 #define SICRH_TSOBI2 0x00000001 153 154 #elif defined(CONFIG_MPC8360) 155 /* SICRL bits - MPC8360 specific */ 156 #define SICRL_LDP_A 0xC0000000 157 #define SICRL_LCLK_1 0x10000000 158 #define SICRL_LCLK_2 0x08000000 159 #define SICRL_SRCID_A 0x03000000 160 #define SICRL_IRQ_CKSTP_A 0x00C00000 161 162 /* SICRH bits - MPC8360 specific */ 163 #define SICRH_DDR 0x80000000 164 #define SICRH_SECONDARY_DDR 0x40000000 165 #define SICRH_SDDROE 0x20000000 166 #define SICRH_IRQ3 0x10000000 167 #define SICRH_UC1EOBI 0x00000004 168 #define SICRH_UC2E1OBI 0x00000002 169 #define SICRH_UC2E2OBI 0x00000001 170 #endif 171 172 /* SWCRR - System Watchdog Control Register 173 */ 174 #define SWCRR 0x0204 /* Register offset to immr */ 175 #define SWCRR_SWTC 0xFFFF0000 /* Software Watchdog Time Count */ 176 #define SWCRR_SWEN 0x00000004 /* Watchdog Enable bit */ 177 #define SWCRR_SWRI 0x00000002 /* Software Watchdog Reset/Interrupt Select bit */ 178 #define SWCRR_SWPR 0x00000001 /* Software Watchdog Counter Prescale bit */ 179 #define SWCRR_RES ~(SWCRR_SWTC | SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR) 180 181 /* SWCNR - System Watchdog Counter Register 182 */ 183 #define SWCNR 0x0208 /* Register offset to immr */ 184 #define SWCNR_SWCN 0x0000FFFF /* Software Watchdog Count mask */ 185 #define SWCNR_RES ~(SWCNR_SWCN) 186 187 /* SWSRR - System Watchdog Service Register 188 */ 189 #define SWSRR 0x020E /* Register offset to immr */ 190 191 /* ACR - Arbiter Configuration Register 192 */ 193 #define ACR_COREDIS 0x10000000 /* Core disable */ 194 #define ACR_COREDIS_SHIFT (31-7) 195 #define ACR_PIPE_DEP 0x00070000 /* Pipeline depth */ 196 #define ACR_PIPE_DEP_SHIFT (31-15) 197 #define ACR_PCI_RPTCNT 0x00007000 /* PCI repeat count */ 198 #define ACR_PCI_RPTCNT_SHIFT (31-19) 199 #define ACR_RPTCNT 0x00000700 /* Repeat count */ 200 #define ACR_RPTCNT_SHIFT (31-23) 201 #define ACR_APARK 0x00000030 /* Address parking */ 202 #define ACR_APARK_SHIFT (31-27) 203 #define ACR_PARKM 0x0000000F /* Parking master */ 204 #define ACR_PARKM_SHIFT (31-31) 205 206 /* ATR - Arbiter Timers Register 207 */ 208 #define ATR_DTO 0x00FF0000 /* Data time out */ 209 #define ATR_ATO 0x000000FF /* Address time out */ 210 211 /* AER - Arbiter Event Register 212 */ 213 #define AER_ETEA 0x00000020 /* Transfer error */ 214 #define AER_RES 0x00000010 /* Reserved transfer type */ 215 #define AER_ECW 0x00000008 /* External control word transfer type */ 216 #define AER_AO 0x00000004 /* Address Only transfer type */ 217 #define AER_DTO 0x00000002 /* Data time out */ 218 #define AER_ATO 0x00000001 /* Address time out */ 219 220 /* AEATR - Arbiter Event Address Register 221 */ 222 #define AEATR_EVENT 0x07000000 /* Event type */ 223 #define AEATR_MSTR_ID 0x001F0000 /* Master Id */ 224 #define AEATR_TBST 0x00000800 /* Transfer burst */ 225 #define AEATR_TSIZE 0x00000700 /* Transfer Size */ 226 #define AEATR_TTYPE 0x0000001F /* Transfer Type */ 227 228 /* HRCWL - Hard Reset Configuration Word Low 229 */ 230 #define HRCWL_LBIUCM 0x80000000 231 #define HRCWL_LBIUCM_SHIFT 31 232 #define HRCWL_LCL_BUS_TO_SCB_CLK_1X1 0x00000000 233 #define HRCWL_LCL_BUS_TO_SCB_CLK_2X1 0x80000000 234 235 #define HRCWL_DDRCM 0x40000000 236 #define HRCWL_DDRCM_SHIFT 30 237 #define HRCWL_DDR_TO_SCB_CLK_1X1 0x00000000 238 #define HRCWL_DDR_TO_SCB_CLK_2X1 0x40000000 239 240 #define HRCWL_SPMF 0x0f000000 241 #define HRCWL_SPMF_SHIFT 24 242 #define HRCWL_CSB_TO_CLKIN_16X1 0x00000000 243 #define HRCWL_CSB_TO_CLKIN_1X1 0x01000000 244 #define HRCWL_CSB_TO_CLKIN_2X1 0x02000000 245 #define HRCWL_CSB_TO_CLKIN_3X1 0x03000000 246 #define HRCWL_CSB_TO_CLKIN_4X1 0x04000000 247 #define HRCWL_CSB_TO_CLKIN_5X1 0x05000000 248 #define HRCWL_CSB_TO_CLKIN_6X1 0x06000000 249 #define HRCWL_CSB_TO_CLKIN_7X1 0x07000000 250 #define HRCWL_CSB_TO_CLKIN_8X1 0x08000000 251 #define HRCWL_CSB_TO_CLKIN_9X1 0x09000000 252 #define HRCWL_CSB_TO_CLKIN_10X1 0x0A000000 253 #define HRCWL_CSB_TO_CLKIN_11X1 0x0B000000 254 #define HRCWL_CSB_TO_CLKIN_12X1 0x0C000000 255 #define HRCWL_CSB_TO_CLKIN_13X1 0x0D000000 256 #define HRCWL_CSB_TO_CLKIN_14X1 0x0E000000 257 #define HRCWL_CSB_TO_CLKIN_15X1 0x0F000000 258 259 #define HRCWL_VCO_BYPASS 0x00000000 260 #define HRCWL_VCO_1X2 0x00000000 261 #define HRCWL_VCO_1X4 0x00200000 262 #define HRCWL_VCO_1X8 0x00400000 263 264 #define HRCWL_COREPLL 0x007F0000 265 #define HRCWL_COREPLL_SHIFT 16 266 #define HRCWL_CORE_TO_CSB_BYPASS 0x00000000 267 #define HRCWL_CORE_TO_CSB_1X1 0x00020000 268 #define HRCWL_CORE_TO_CSB_1_5X1 0x00030000 269 #define HRCWL_CORE_TO_CSB_2X1 0x00040000 270 #define HRCWL_CORE_TO_CSB_2_5X1 0x00050000 271 #define HRCWL_CORE_TO_CSB_3X1 0x00060000 272 273 #if defined(CONFIG_MPC8360) 274 #define HRCWL_CEVCOD 0x000000C0 275 #define HRCWL_CEVCOD_SHIFT 6 276 #define HRCWL_CE_PLL_VCO_DIV_4 0x00000000 277 #define HRCWL_CE_PLL_VCO_DIV_8 0x00000040 278 #define HRCWL_CE_PLL_VCO_DIV_2 0x00000080 279 280 #define HRCWL_CEPDF 0x00000020 281 #define HRCWL_CEPDF_SHIFT 5 282 #define HRCWL_CE_PLL_DIV_1X1 0x00000000 283 #define HRCWL_CE_PLL_DIV_2X1 0x00000020 284 285 #define HRCWL_CEPMF 0x0000001F 286 #define HRCWL_CEPMF_SHIFT 0 287 #define HRCWL_CE_TO_PLL_1X16_ 0x00000000 288 #define HRCWL_CE_TO_PLL_1X2 0x00000002 289 #define HRCWL_CE_TO_PLL_1X3 0x00000003 290 #define HRCWL_CE_TO_PLL_1X4 0x00000004 291 #define HRCWL_CE_TO_PLL_1X5 0x00000005 292 #define HRCWL_CE_TO_PLL_1X6 0x00000006 293 #define HRCWL_CE_TO_PLL_1X7 0x00000007 294 #define HRCWL_CE_TO_PLL_1X8 0x00000008 295 #define HRCWL_CE_TO_PLL_1X9 0x00000009 296 #define HRCWL_CE_TO_PLL_1X10 0x0000000A 297 #define HRCWL_CE_TO_PLL_1X11 0x0000000B 298 #define HRCWL_CE_TO_PLL_1X12 0x0000000C 299 #define HRCWL_CE_TO_PLL_1X13 0x0000000D 300 #define HRCWL_CE_TO_PLL_1X14 0x0000000E 301 #define HRCWL_CE_TO_PLL_1X15 0x0000000F 302 #define HRCWL_CE_TO_PLL_1X16 0x00000010 303 #define HRCWL_CE_TO_PLL_1X17 0x00000011 304 #define HRCWL_CE_TO_PLL_1X18 0x00000012 305 #define HRCWL_CE_TO_PLL_1X19 0x00000013 306 #define HRCWL_CE_TO_PLL_1X20 0x00000014 307 #define HRCWL_CE_TO_PLL_1X21 0x00000015 308 #define HRCWL_CE_TO_PLL_1X22 0x00000016 309 #define HRCWL_CE_TO_PLL_1X23 0x00000017 310 #define HRCWL_CE_TO_PLL_1X24 0x00000018 311 #define HRCWL_CE_TO_PLL_1X25 0x00000019 312 #define HRCWL_CE_TO_PLL_1X26 0x0000001A 313 #define HRCWL_CE_TO_PLL_1X27 0x0000001B 314 #define HRCWL_CE_TO_PLL_1X28 0x0000001C 315 #define HRCWL_CE_TO_PLL_1X29 0x0000001D 316 #define HRCWL_CE_TO_PLL_1X30 0x0000001E 317 #define HRCWL_CE_TO_PLL_1X31 0x0000001F 318 #endif 319 320 /* HRCWH - Hardware Reset Configuration Word High 321 */ 322 #define HRCWH_PCI_HOST 0x80000000 323 #define HRCWH_PCI_HOST_SHIFT 31 324 #define HRCWH_PCI_AGENT 0x00000000 325 326 #if defined(CONFIG_MPC8349) 327 #define HRCWH_32_BIT_PCI 0x00000000 328 #define HRCWH_64_BIT_PCI 0x40000000 329 #endif 330 331 #define HRCWH_PCI1_ARBITER_DISABLE 0x00000000 332 #define HRCWH_PCI1_ARBITER_ENABLE 0x20000000 333 334 #define HRCWH_PCI_ARBITER_DISABLE 0x00000000 335 #define HRCWH_PCI_ARBITER_ENABLE 0x20000000 336 337 #if defined(CONFIG_MPC8349) 338 #define HRCWH_PCI2_ARBITER_DISABLE 0x00000000 339 #define HRCWH_PCI2_ARBITER_ENABLE 0x10000000 340 341 #elif defined(CONFIG_MPC8360) 342 #define HRCWH_PCICKDRV_DISABLE 0x00000000 343 #define HRCWH_PCICKDRV_ENABLE 0x10000000 344 #endif 345 346 #define HRCWH_CORE_DISABLE 0x08000000 347 #define HRCWH_CORE_ENABLE 0x00000000 348 349 #define HRCWH_FROM_0X00000100 0x00000000 350 #define HRCWH_FROM_0XFFF00100 0x04000000 351 352 #define HRCWH_BOOTSEQ_DISABLE 0x00000000 353 #define HRCWH_BOOTSEQ_NORMAL 0x01000000 354 #define HRCWH_BOOTSEQ_EXTENDED 0x02000000 355 356 #define HRCWH_SW_WATCHDOG_DISABLE 0x00000000 357 #define HRCWH_SW_WATCHDOG_ENABLE 0x00800000 358 359 #define HRCWH_ROM_LOC_DDR_SDRAM 0x00000000 360 #define HRCWH_ROM_LOC_PCI1 0x00100000 361 #if defined(CONFIG_MPC8349) 362 #define HRCWH_ROM_LOC_PCI2 0x00200000 363 #endif 364 #define HRCWH_ROM_LOC_LOCAL_8BIT 0x00500000 365 #define HRCWH_ROM_LOC_LOCAL_16BIT 0x00600000 366 #define HRCWH_ROM_LOC_LOCAL_32BIT 0x00700000 367 368 #if defined(CONFIG_MPC8349) 369 #define HRCWH_TSEC1M_IN_RGMII 0x00000000 370 #define HRCWH_TSEC1M_IN_RTBI 0x00004000 371 #define HRCWH_TSEC1M_IN_GMII 0x00008000 372 #define HRCWH_TSEC1M_IN_TBI 0x0000C000 373 #define HRCWH_TSEC2M_IN_RGMII 0x00000000 374 #define HRCWH_TSEC2M_IN_RTBI 0x00001000 375 #define HRCWH_TSEC2M_IN_GMII 0x00002000 376 #define HRCWH_TSEC2M_IN_TBI 0x00003000 377 #endif 378 379 #if defined(CONFIG_MPC8360) 380 #define HRCWH_SECONDARY_DDR_DISABLE 0x00000000 381 #define HRCWH_SECONDARY_DDR_ENABLE 0x00000010 382 #endif 383 384 #define HRCWH_BIG_ENDIAN 0x00000000 385 #define HRCWH_LITTLE_ENDIAN 0x00000008 386 387 #define HRCWH_LALE_NORMAL 0x00000000 388 #define HRCWH_LALE_EARLY 0x00000004 389 390 #define HRCWH_LDP_SET 0x00000000 391 #define HRCWH_LDP_CLEAR 0x00000002 392 393 /* RSR - Reset Status Register 394 */ 395 #define RSR_RSTSRC 0xE0000000 /* Reset source */ 396 #define RSR_RSTSRC_SHIFT 29 397 #define RSR_BSF 0x00010000 /* Boot seq. fail */ 398 #define RSR_BSF_SHIFT 16 399 #define RSR_SWSR 0x00002000 /* software soft reset */ 400 #define RSR_SWSR_SHIFT 13 401 #define RSR_SWHR 0x00001000 /* software hard reset */ 402 #define RSR_SWHR_SHIFT 12 403 #define RSR_JHRS 0x00000200 /* jtag hreset */ 404 #define RSR_JHRS_SHIFT 9 405 #define RSR_JSRS 0x00000100 /* jtag sreset status */ 406 #define RSR_JSRS_SHIFT 8 407 #define RSR_CSHR 0x00000010 /* checkstop reset status */ 408 #define RSR_CSHR_SHIFT 4 409 #define RSR_SWRS 0x00000008 /* software watchdog reset status */ 410 #define RSR_SWRS_SHIFT 3 411 #define RSR_BMRS 0x00000004 /* bus monitop reset status */ 412 #define RSR_BMRS_SHIFT 2 413 #define RSR_SRS 0x00000002 /* soft reset status */ 414 #define RSR_SRS_SHIFT 1 415 #define RSR_HRS 0x00000001 /* hard reset status */ 416 #define RSR_HRS_SHIFT 0 417 #define RSR_RES ~(RSR_RSTSRC | RSR_BSF | RSR_SWSR | RSR_SWHR |\ 418 RSR_JHRS | RSR_JSRS | RSR_CSHR | RSR_SWRS |\ 419 RSR_BMRS | RSR_SRS | RSR_HRS) 420 /* RMR - Reset Mode Register 421 */ 422 #define RMR_CSRE 0x00000001 /* checkstop reset enable */ 423 #define RMR_CSRE_SHIFT 0 424 #define RMR_RES ~(RMR_CSRE) 425 426 /* RCR - Reset Control Register 427 */ 428 #define RCR_SWHR 0x00000002 /* software hard reset */ 429 #define RCR_SWSR 0x00000001 /* software soft reset */ 430 #define RCR_RES ~(RCR_SWHR | RCR_SWSR) 431 432 /* RCER - Reset Control Enable Register 433 */ 434 #define RCER_CRE 0x00000001 /* software hard reset */ 435 #define RCER_RES ~(RCER_CRE) 436 437 /* SPMR - System PLL Mode Register 438 */ 439 #define SPMR_LBIUCM 0x80000000 440 #define SPMR_DDRCM 0x40000000 441 #define SPMR_SPMF 0x0F000000 442 #define SPMR_CKID 0x00800000 443 #define SPMR_CKID_SHIFT 23 444 #define SPMR_COREPLL 0x007F0000 445 #define SPMR_CEVCOD 0x000000C0 446 #define SPMR_CEPDF 0x00000020 447 #define SPMR_CEPMF 0x0000001F 448 449 /* OCCR - Output Clock Control Register 450 */ 451 #define OCCR_PCICOE0 0x80000000 452 #define OCCR_PCICOE1 0x40000000 453 #define OCCR_PCICOE2 0x20000000 454 #define OCCR_PCICOE3 0x10000000 455 #define OCCR_PCICOE4 0x08000000 456 #define OCCR_PCICOE5 0x04000000 457 #define OCCR_PCICOE6 0x02000000 458 #define OCCR_PCICOE7 0x01000000 459 #define OCCR_PCICD0 0x00800000 460 #define OCCR_PCICD1 0x00400000 461 #define OCCR_PCICD2 0x00200000 462 #define OCCR_PCICD3 0x00100000 463 #define OCCR_PCICD4 0x00080000 464 #define OCCR_PCICD5 0x00040000 465 #define OCCR_PCICD6 0x00020000 466 #define OCCR_PCICD7 0x00010000 467 #define OCCR_PCI1CR 0x00000002 468 #define OCCR_PCI2CR 0x00000001 469 #define OCCR_PCICR OCCR_PCI1CR 470 471 /* SCCR - System Clock Control Register 472 */ 473 #define SCCR_ENCCM 0x03000000 474 #define SCCR_ENCCM_SHIFT 24 475 #define SCCR_ENCCM_0 0x00000000 476 #define SCCR_ENCCM_1 0x01000000 477 #define SCCR_ENCCM_2 0x02000000 478 #define SCCR_ENCCM_3 0x03000000 479 480 #define SCCR_PCICM 0x00010000 481 #define SCCR_PCICM_SHIFT 16 482 483 /* SCCR bits - MPC8349 specific */ 484 #define SCCR_TSEC1CM 0xc0000000 485 #define SCCR_TSEC1CM_SHIFT 30 486 #define SCCR_TSEC1CM_0 0x00000000 487 #define SCCR_TSEC1CM_1 0x40000000 488 #define SCCR_TSEC1CM_2 0x80000000 489 #define SCCR_TSEC1CM_3 0xC0000000 490 491 #define SCCR_TSEC2CM 0x30000000 492 #define SCCR_TSEC2CM_SHIFT 28 493 #define SCCR_TSEC2CM_0 0x00000000 494 #define SCCR_TSEC2CM_1 0x10000000 495 #define SCCR_TSEC2CM_2 0x20000000 496 #define SCCR_TSEC2CM_3 0x30000000 497 498 #define SCCR_USBMPHCM 0x00c00000 499 #define SCCR_USBMPHCM_SHIFT 22 500 #define SCCR_USBDRCM 0x00300000 501 #define SCCR_USBDRCM_SHIFT 20 502 503 #define SCCR_USBCM_0 0x00000000 504 #define SCCR_USBCM_1 0x00500000 505 #define SCCR_USBCM_2 0x00A00000 506 #define SCCR_USBCM_3 0x00F00000 507 508 #define SCCR_CLK_MASK ( SCCR_TSEC1CM_3 \ 509 | SCCR_TSEC2CM_3 \ 510 | SCCR_ENCCM_3 \ 511 | SCCR_USBCM_3 ) 512 513 #define SCCR_DEFAULT 0xFFFFFFFF 514 515 /* CSn_BDNS - Chip Select memory Bounds Register 516 */ 517 #define CSBNDS_SA 0x00FF0000 518 #define CSBNDS_SA_SHIFT 8 519 #define CSBNDS_EA 0x000000FF 520 #define CSBNDS_EA_SHIFT 24 521 522 /* CSn_CONFIG - Chip Select Configuration Register 523 */ 524 #define CSCONFIG_EN 0x80000000 525 #define CSCONFIG_AP 0x00800000 526 #define CSCONFIG_ROW_BIT 0x00000700 527 #define CSCONFIG_ROW_BIT_12 0x00000000 528 #define CSCONFIG_ROW_BIT_13 0x00000100 529 #define CSCONFIG_ROW_BIT_14 0x00000200 530 #define CSCONFIG_COL_BIT 0x00000007 531 #define CSCONFIG_COL_BIT_8 0x00000000 532 #define CSCONFIG_COL_BIT_9 0x00000001 533 #define CSCONFIG_COL_BIT_10 0x00000002 534 #define CSCONFIG_COL_BIT_11 0x00000003 535 536 /* TIMING_CFG_1 - DDR SDRAM Timing Configuration 1 537 */ 538 #define TIMING_CFG1_PRETOACT 0x70000000 539 #define TIMING_CFG1_PRETOACT_SHIFT 28 540 #define TIMING_CFG1_ACTTOPRE 0x0F000000 541 #define TIMING_CFG1_ACTTOPRE_SHIFT 24 542 #define TIMING_CFG1_ACTTORW 0x00700000 543 #define TIMING_CFG1_ACTTORW_SHIFT 20 544 #define TIMING_CFG1_CASLAT 0x00070000 545 #define TIMING_CFG1_CASLAT_SHIFT 16 546 #define TIMING_CFG1_REFREC 0x0000F000 547 #define TIMING_CFG1_REFREC_SHIFT 12 548 #define TIMING_CFG1_WRREC 0x00000700 549 #define TIMING_CFG1_WRREC_SHIFT 8 550 #define TIMING_CFG1_ACTTOACT 0x00000070 551 #define TIMING_CFG1_ACTTOACT_SHIFT 4 552 #define TIMING_CFG1_WRTORD 0x00000007 553 #define TIMING_CFG1_WRTORD_SHIFT 0 554 #define TIMING_CFG1_CASLAT_20 0x00030000 /* CAS latency = 2.0 */ 555 #define TIMING_CFG1_CASLAT_25 0x00040000 /* CAS latency = 2.5 */ 556 557 /* TIMING_CFG_2 - DDR SDRAM Timing Configuration 2 558 */ 559 #define TIMING_CFG2_CPO 0x0F000000 560 #define TIMING_CFG2_CPO_SHIFT 24 561 #define TIMING_CFG2_ACSM 0x00080000 562 #define TIMING_CFG2_WR_DATA_DELAY 0x00001C00 563 #define TIMING_CFG2_WR_DATA_DELAY_SHIFT 10 564 #define TIMING_CFG2_CPO_DEF 0x00000000 /* default (= CASLAT + 1) */ 565 566 /* DDR_SDRAM_CFG - DDR SDRAM Control Configuration 567 */ 568 #define SDRAM_CFG_MEM_EN 0x80000000 569 #define SDRAM_CFG_SREN 0x40000000 570 #define SDRAM_CFG_ECC_EN 0x20000000 571 #define SDRAM_CFG_RD_EN 0x10000000 572 #define SDRAM_CFG_SDRAM_TYPE 0x03000000 573 #define SDRAM_CFG_SDRAM_TYPE_SHIFT 24 574 #define SDRAM_CFG_DYN_PWR 0x00200000 575 #define SDRAM_CFG_32_BE 0x00080000 576 #define SDRAM_CFG_8_BE 0x00040000 577 #define SDRAM_CFG_NCAP 0x00020000 578 #define SDRAM_CFG_2T_EN 0x00008000 579 #define SDRAM_CFG_SDRAM_TYPE_DDR 0x02000000 580 581 /* DDR_SDRAM_MODE - DDR SDRAM Mode Register 582 */ 583 #define SDRAM_MODE_ESD 0xFFFF0000 584 #define SDRAM_MODE_ESD_SHIFT 16 585 #define SDRAM_MODE_SD 0x0000FFFF 586 #define SDRAM_MODE_SD_SHIFT 0 587 #define DDR_MODE_EXT_MODEREG 0x4000 /* select extended mode reg */ 588 #define DDR_MODE_EXT_OPMODE 0x3FF8 /* operating mode, mask */ 589 #define DDR_MODE_EXT_OP_NORMAL 0x0000 /* normal operation */ 590 #define DDR_MODE_QFC 0x0004 /* QFC / compatibility, mask */ 591 #define DDR_MODE_QFC_COMP 0x0000 /* compatible to older SDRAMs */ 592 #define DDR_MODE_WEAK 0x0002 /* weak drivers */ 593 #define DDR_MODE_DLL_DIS 0x0001 /* disable DLL */ 594 #define DDR_MODE_CASLAT 0x0070 /* CAS latency, mask */ 595 #define DDR_MODE_CASLAT_15 0x0010 /* CAS latency 1.5 */ 596 #define DDR_MODE_CASLAT_20 0x0020 /* CAS latency 2 */ 597 #define DDR_MODE_CASLAT_25 0x0060 /* CAS latency 2.5 */ 598 #define DDR_MODE_CASLAT_30 0x0030 /* CAS latency 3 */ 599 #define DDR_MODE_BTYPE_SEQ 0x0000 /* sequential burst */ 600 #define DDR_MODE_BTYPE_ILVD 0x0008 /* interleaved burst */ 601 #define DDR_MODE_BLEN_2 0x0001 /* burst length 2 */ 602 #define DDR_MODE_BLEN_4 0x0002 /* burst length 4 */ 603 #define DDR_REFINT_166MHZ_7US 1302 /* exact value for 7.8125us */ 604 #define DDR_BSTOPRE 256 /* use 256 cycles as a starting point */ 605 #define DDR_MODE_MODEREG 0x0000 /* select mode register */ 606 607 /* DDR_SDRAM_INTERVAL - DDR SDRAM Interval Register 608 */ 609 #define SDRAM_INTERVAL_REFINT 0x3FFF0000 610 #define SDRAM_INTERVAL_REFINT_SHIFT 16 611 #define SDRAM_INTERVAL_BSTOPRE 0x00003FFF 612 #define SDRAM_INTERVAL_BSTOPRE_SHIFT 0 613 614 /* DDR_SDRAM_CLK_CNTL - DDR SDRAM Clock Control Register 615 */ 616 #define DDR_SDRAM_CLK_CNTL_SS_EN 0x80000000 617 #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_025 0x01000000 618 #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 0x02000000 619 #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075 0x03000000 620 #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_1 0x04000000 621 622 /* ECC_ERR_INJECT - Memory data path error injection mask ECC 623 */ 624 #define ECC_ERR_INJECT_EMB (0x80000000>>22) /* ECC Mirror Byte */ 625 #define ECC_ERR_INJECT_EIEN (0x80000000>>23) /* Error Injection Enable */ 626 #define ECC_ERR_INJECT_EEIM (0xff000000>>24) /* ECC Erroe Injection Enable */ 627 #define ECC_ERR_INJECT_EEIM_SHIFT 0 628 629 /* CAPTURE_ECC - Memory data path read capture ECC 630 */ 631 #define CAPTURE_ECC_ECE (0xff000000>>24) 632 #define CAPTURE_ECC_ECE_SHIFT 0 633 634 /* ERR_DETECT - Memory error detect 635 */ 636 #define ECC_ERROR_DETECT_MME (0x80000000>>0) /* Multiple Memory Errors */ 637 #define ECC_ERROR_DETECT_MBE (0x80000000>>28) /* Multiple-Bit Error */ 638 #define ECC_ERROR_DETECT_SBE (0x80000000>>29) /* Single-Bit ECC Error Pickup */ 639 #define ECC_ERROR_DETECT_MSE (0x80000000>>31) /* Memory Select Error */ 640 641 /* ERR_DISABLE - Memory error disable 642 */ 643 #define ECC_ERROR_DISABLE_MBED (0x80000000>>28) /* Multiple-Bit ECC Error Disable */ 644 #define ECC_ERROR_DISABLE_SBED (0x80000000>>29) /* Sinle-Bit ECC Error disable */ 645 #define ECC_ERROR_DISABLE_MSED (0x80000000>>31) /* Memory Select Error Disable */ 646 #define ECC_ERROR_ENABLE ~(ECC_ERROR_DISABLE_MSED | ECC_ERROR_DISABLE_SBED |\ 647 ECC_ERROR_DISABLE_MBED) 648 /* ERR_INT_EN - Memory error interrupt enable 649 */ 650 #define ECC_ERR_INT_EN_MBEE (0x80000000>>28) /* Multiple-Bit ECC Error Interrupt Enable */ 651 #define ECC_ERR_INT_EN_SBEE (0x80000000>>29) /* Single-Bit ECC Error Interrupt Enable */ 652 #define ECC_ERR_INT_EN_MSEE (0x80000000>>31) /* Memory Select Error Interrupt Enable */ 653 #define ECC_ERR_INT_DISABLE ~(ECC_ERR_INT_EN_MBEE | ECC_ERR_INT_EN_SBEE |\ 654 ECC_ERR_INT_EN_MSEE) 655 /* CAPTURE_ATTRIBUTES - Memory error attributes capture 656 */ 657 #define ECC_CAPT_ATTR_BNUM (0xe0000000>>1) /* Data Beat Num */ 658 #define ECC_CAPT_ATTR_BNUM_SHIFT 28 659 #define ECC_CAPT_ATTR_TSIZ (0xc0000000>>6) /* Transaction Size */ 660 #define ECC_CAPT_ATTR_TSIZ_FOUR_DW 0 661 #define ECC_CAPT_ATTR_TSIZ_ONE_DW 1 662 #define ECC_CAPT_ATTR_TSIZ_TWO_DW 2 663 #define ECC_CAPT_ATTR_TSIZ_THREE_DW 3 664 #define ECC_CAPT_ATTR_TSIZ_SHIFT 24 665 #define ECC_CAPT_ATTR_TSRC (0xf8000000>>11) /* Transaction Source */ 666 #define ECC_CAPT_ATTR_TSRC_E300_CORE_DT 0x0 667 #define ECC_CAPT_ATTR_TSRC_E300_CORE_IF 0x2 668 #define ECC_CAPT_ATTR_TSRC_TSEC1 0x4 669 #define ECC_CAPT_ATTR_TSRC_TSEC2 0x5 670 #define ECC_CAPT_ATTR_TSRC_USB (0x06|0x07) 671 #define ECC_CAPT_ATTR_TSRC_ENCRYPT 0x8 672 #define ECC_CAPT_ATTR_TSRC_I2C 0x9 673 #define ECC_CAPT_ATTR_TSRC_JTAG 0xA 674 #define ECC_CAPT_ATTR_TSRC_PCI1 0xD 675 #define ECC_CAPT_ATTR_TSRC_PCI2 0xE 676 #define ECC_CAPT_ATTR_TSRC_DMA 0xF 677 #define ECC_CAPT_ATTR_TSRC_SHIFT 16 678 #define ECC_CAPT_ATTR_TTYP (0xe0000000>>18) /* Transaction Type */ 679 #define ECC_CAPT_ATTR_TTYP_WRITE 0x1 680 #define ECC_CAPT_ATTR_TTYP_READ 0x2 681 #define ECC_CAPT_ATTR_TTYP_R_M_W 0x3 682 #define ECC_CAPT_ATTR_TTYP_SHIFT 12 683 #define ECC_CAPT_ATTR_VLD (0x80000000>>31) /* Valid */ 684 685 /* ERR_SBE - Single bit ECC memory error management 686 */ 687 #define ECC_ERROR_MAN_SBET (0xff000000>>8) /* Single-Bit Error Threshold 0..255 */ 688 #define ECC_ERROR_MAN_SBET_SHIFT 16 689 #define ECC_ERROR_MAN_SBEC (0xff000000>>24) /* Single Bit Error Counter 0..255 */ 690 #define ECC_ERROR_MAN_SBEC_SHIFT 0 691 692 /* BR - Base Registers 693 */ 694 #define BR0 0x5000 /* Register offset to immr */ 695 #define BR1 0x5008 696 #define BR2 0x5010 697 #define BR3 0x5018 698 #define BR4 0x5020 699 #define BR5 0x5028 700 #define BR6 0x5030 701 #define BR7 0x5038 702 703 #define BR_BA 0xFFFF8000 704 #define BR_BA_SHIFT 15 705 #define BR_PS 0x00001800 706 #define BR_PS_SHIFT 11 707 #define BR_PS_8 0x00000800 /* Port Size 8 bit */ 708 #define BR_PS_16 0x00001000 /* Port Size 16 bit */ 709 #define BR_PS_32 0x00001800 /* Port Size 32 bit */ 710 #define BR_DECC 0x00000600 711 #define BR_DECC_SHIFT 9 712 #define BR_WP 0x00000100 713 #define BR_WP_SHIFT 8 714 #define BR_MSEL 0x000000E0 715 #define BR_MSEL_SHIFT 5 716 #define BR_MS_GPCM 0x00000000 /* GPCM */ 717 #define BR_MS_SDRAM 0x00000060 /* SDRAM */ 718 #define BR_MS_UPMA 0x00000080 /* UPMA */ 719 #define BR_MS_UPMB 0x000000A0 /* UPMB */ 720 #define BR_MS_UPMC 0x000000C0 /* UPMC */ 721 #if defined(CONFIG_MPC8360) 722 #define BR_ATOM 0x0000000C 723 #define BR_ATOM_SHIFT 2 724 #endif 725 #define BR_V 0x00000001 726 #define BR_V_SHIFT 0 727 728 #if defined(CONFIG_MPC8349) 729 #define BR_RES ~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_V) 730 #elif defined(CONFIG_MPC8360) 731 #define BR_RES ~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_ATOM | BR_V) 732 #endif 733 734 /* OR - Option Registers 735 */ 736 #define OR0 0x5004 /* Register offset to immr */ 737 #define OR1 0x500C 738 #define OR2 0x5014 739 #define OR3 0x501C 740 #define OR4 0x5024 741 #define OR5 0x502C 742 #define OR6 0x5034 743 #define OR7 0x503C 744 745 #define OR_GPCM_AM 0xFFFF8000 746 #define OR_GPCM_AM_SHIFT 15 747 #define OR_GPCM_BCTLD 0x00001000 748 #define OR_GPCM_BCTLD_SHIFT 12 749 #define OR_GPCM_CSNT 0x00000800 750 #define OR_GPCM_CSNT_SHIFT 11 751 #define OR_GPCM_ACS 0x00000600 752 #define OR_GPCM_ACS_SHIFT 9 753 #define OR_GPCM_ACS_0b10 0x00000400 754 #define OR_GPCM_ACS_0b11 0x00000600 755 #define OR_GPCM_XACS 0x00000100 756 #define OR_GPCM_XACS_SHIFT 8 757 #define OR_GPCM_SCY 0x000000F0 758 #define OR_GPCM_SCY_SHIFT 4 759 #define OR_GPCM_SCY_1 0x00000010 760 #define OR_GPCM_SCY_2 0x00000020 761 #define OR_GPCM_SCY_3 0x00000030 762 #define OR_GPCM_SCY_4 0x00000040 763 #define OR_GPCM_SCY_5 0x00000050 764 #define OR_GPCM_SCY_6 0x00000060 765 #define OR_GPCM_SCY_7 0x00000070 766 #define OR_GPCM_SCY_8 0x00000080 767 #define OR_GPCM_SCY_9 0x00000090 768 #define OR_GPCM_SCY_10 0x000000a0 769 #define OR_GPCM_SCY_11 0x000000b0 770 #define OR_GPCM_SCY_12 0x000000c0 771 #define OR_GPCM_SCY_13 0x000000d0 772 #define OR_GPCM_SCY_14 0x000000e0 773 #define OR_GPCM_SCY_15 0x000000f0 774 #define OR_GPCM_SETA 0x00000008 775 #define OR_GPCM_SETA_SHIFT 3 776 #define OR_GPCM_TRLX 0x00000004 777 #define OR_GPCM_TRLX_SHIFT 2 778 #define OR_GPCM_EHTR 0x00000002 779 #define OR_GPCM_EHTR_SHIFT 1 780 #define OR_GPCM_EAD 0x00000001 781 #define OR_GPCM_EAD_SHIFT 0 782 783 #define OR_UPM_AM 0xFFFF8000 784 #define OR_UPM_AM_SHIFT 15 785 #define OR_UPM_XAM 0x00006000 786 #define OR_UPM_XAM_SHIFT 13 787 #define OR_UPM_BCTLD 0x00001000 788 #define OR_UPM_BCTLD_SHIFT 12 789 #define OR_UPM_BI 0x00000100 790 #define OR_UPM_BI_SHIFT 8 791 #define OR_UPM_TRLX 0x00000004 792 #define OR_UPM_TRLX_SHIFT 2 793 #define OR_UPM_EHTR 0x00000002 794 #define OR_UPM_EHTR_SHIFT 1 795 #define OR_UPM_EAD 0x00000001 796 #define OR_UPM_EAD_SHIFT 0 797 798 #define OR_SDRAM_AM 0xFFFF8000 799 #define OR_SDRAM_AM_SHIFT 15 800 #define OR_SDRAM_XAM 0x00006000 801 #define OR_SDRAM_XAM_SHIFT 13 802 #define OR_SDRAM_COLS 0x00001C00 803 #define OR_SDRAM_COLS_SHIFT 10 804 #define OR_SDRAM_ROWS 0x000001C0 805 #define OR_SDRAM_ROWS_SHIFT 6 806 #define OR_SDRAM_PMSEL 0x00000020 807 #define OR_SDRAM_PMSEL_SHIFT 5 808 #define OR_SDRAM_EAD 0x00000001 809 #define OR_SDRAM_EAD_SHIFT 0 810 811 /* LBCR - Local Bus Configuration Register 812 */ 813 #define LBCR_LDIS 0x80000000 814 #define LBCR_LDIS_SHIFT 31 815 #define LBCR_BCTLC 0x00C00000 816 #define LBCR_BCTLC_SHIFT 22 817 #define LBCR_LPBSE 0x00020000 818 #define LBCR_LPBSE_SHIFT 17 819 #define LBCR_EPAR 0x00010000 820 #define LBCR_EPAR_SHIFT 16 821 #define LBCR_BMT 0x0000FF00 822 #define LBCR_BMT_SHIFT 8 823 824 /* LCRR - Clock Ratio Register 825 */ 826 #define LCRR_DBYP 0x80000000 827 #define LCRR_DBYP_SHIFT 31 828 #define LCRR_BUFCMDC 0x30000000 829 #define LCRR_BUFCMDC_SHIFT 28 830 #define LCRR_BUFCMDC_1 0x10000000 831 #define LCRR_BUFCMDC_2 0x20000000 832 #define LCRR_BUFCMDC_3 0x30000000 833 #define LCRR_BUFCMDC_4 0x00000000 834 #define LCRR_ECL 0x03000000 835 #define LCRR_ECL_SHIFT 24 836 #define LCRR_ECL_4 0x00000000 837 #define LCRR_ECL_5 0x01000000 838 #define LCRR_ECL_6 0x02000000 839 #define LCRR_ECL_7 0x03000000 840 #define LCRR_EADC 0x00030000 841 #define LCRR_EADC_SHIFT 16 842 #define LCRR_EADC_1 0x00010000 843 #define LCRR_EADC_2 0x00020000 844 #define LCRR_EADC_3 0x00030000 845 #define LCRR_EADC_4 0x00000000 846 #define LCRR_CLKDIV 0x0000000F 847 #define LCRR_CLKDIV_SHIFT 0 848 #define LCRR_CLKDIV_2 0x00000002 849 #define LCRR_CLKDIV_4 0x00000004 850 #define LCRR_CLKDIV_8 0x00000008 851 852 /* DMAMR - DMA Mode Register 853 */ 854 #define DMA_CHANNEL_START 0x00000001 /* Bit - DMAMRn CS */ 855 #define DMA_CHANNEL_TRANSFER_MODE_DIRECT 0x00000004 /* Bit - DMAMRn CTM */ 856 #define DMA_CHANNEL_SOURCE_ADRESSS_HOLD_EN 0x00001000 /* Bit - DMAMRn SAHE */ 857 #define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_1B 0x00000000 /* 2Bit- DMAMRn SAHTS 1byte */ 858 #define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_2B 0x00004000 /* 2Bit- DMAMRn SAHTS 2bytes */ 859 #define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_4B 0x00008000 /* 2Bit- DMAMRn SAHTS 4bytes */ 860 #define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_8B 0x0000c000 /* 2Bit- DMAMRn SAHTS 8bytes */ 861 #define DMA_CHANNEL_SNOOP 0x00010000 /* Bit - DMAMRn DMSEN */ 862 863 /* DMASR - DMA Status Register 864 */ 865 #define DMA_CHANNEL_BUSY 0x00000004 /* Bit - DMASRn CB */ 866 #define DMA_CHANNEL_TRANSFER_ERROR 0x00000080 /* Bit - DMASRn TE */ 867 868 /* CONFIG_ADDRESS - PCI Config Address Register 869 */ 870 #define PCI_CONFIG_ADDRESS_EN 0x80000000 871 #define PCI_CONFIG_ADDRESS_BN_SHIFT 16 872 #define PCI_CONFIG_ADDRESS_BN_MASK 0x00ff0000 873 #define PCI_CONFIG_ADDRESS_DN_SHIFT 11 874 #define PCI_CONFIG_ADDRESS_DN_MASK 0x0000f800 875 #define PCI_CONFIG_ADDRESS_FN_SHIFT 8 876 #define PCI_CONFIG_ADDRESS_FN_MASK 0x00000700 877 #define PCI_CONFIG_ADDRESS_RN_SHIFT 0 878 #define PCI_CONFIG_ADDRESS_RN_MASK 0x000000fc 879 880 /* POTAR - PCI Outbound Translation Address Register 881 */ 882 #define POTAR_TA_MASK 0x000fffff 883 884 /* POBAR - PCI Outbound Base Address Register 885 */ 886 #define POBAR_BA_MASK 0x000fffff 887 888 /* POCMR - PCI Outbound Comparision Mask Register 889 */ 890 #define POCMR_EN 0x80000000 891 #define POCMR_IO 0x40000000 /* 0-memory space 1-I/O space */ 892 #define POCMR_SE 0x20000000 /* streaming enable */ 893 #define POCMR_DST 0x10000000 /* 0-PCI1 1-PCI2 */ 894 #define POCMR_CM_MASK 0x000fffff 895 #define POCMR_CM_4G 0x00000000 896 #define POCMR_CM_2G 0x00080000 897 #define POCMR_CM_1G 0x000C0000 898 #define POCMR_CM_512M 0x000E0000 899 #define POCMR_CM_256M 0x000F0000 900 #define POCMR_CM_128M 0x000F8000 901 #define POCMR_CM_64M 0x000FC000 902 #define POCMR_CM_32M 0x000FE000 903 #define POCMR_CM_16M 0x000FF000 904 #define POCMR_CM_8M 0x000FF800 905 #define POCMR_CM_4M 0x000FFC00 906 #define POCMR_CM_2M 0x000FFE00 907 #define POCMR_CM_1M 0x000FFF00 908 #define POCMR_CM_512K 0x000FFF80 909 #define POCMR_CM_256K 0x000FFFC0 910 #define POCMR_CM_128K 0x000FFFE0 911 #define POCMR_CM_64K 0x000FFFF0 912 #define POCMR_CM_32K 0x000FFFF8 913 #define POCMR_CM_16K 0x000FFFFC 914 #define POCMR_CM_8K 0x000FFFFE 915 #define POCMR_CM_4K 0x000FFFFF 916 917 /* PITAR - PCI Inbound Translation Address Register 918 */ 919 #define PITAR_TA_MASK 0x000fffff 920 921 /* PIBAR - PCI Inbound Base/Extended Address Register 922 */ 923 #define PIBAR_MASK 0xffffffff 924 #define PIEBAR_EBA_MASK 0x000fffff 925 926 /* PIWAR - PCI Inbound Windows Attributes Register 927 */ 928 #define PIWAR_EN 0x80000000 929 #define PIWAR_PF 0x20000000 930 #define PIWAR_RTT_MASK 0x000f0000 931 #define PIWAR_RTT_NO_SNOOP 0x00040000 932 #define PIWAR_RTT_SNOOP 0x00050000 933 #define PIWAR_WTT_MASK 0x0000f000 934 #define PIWAR_WTT_NO_SNOOP 0x00004000 935 #define PIWAR_WTT_SNOOP 0x00005000 936 #define PIWAR_IWS_MASK 0x0000003F 937 #define PIWAR_IWS_4K 0x0000000B 938 #define PIWAR_IWS_8K 0x0000000C 939 #define PIWAR_IWS_16K 0x0000000D 940 #define PIWAR_IWS_32K 0x0000000E 941 #define PIWAR_IWS_64K 0x0000000F 942 #define PIWAR_IWS_128K 0x00000010 943 #define PIWAR_IWS_256K 0x00000011 944 #define PIWAR_IWS_512K 0x00000012 945 #define PIWAR_IWS_1M 0x00000013 946 #define PIWAR_IWS_2M 0x00000014 947 #define PIWAR_IWS_4M 0x00000015 948 #define PIWAR_IWS_8M 0x00000016 949 #define PIWAR_IWS_16M 0x00000017 950 #define PIWAR_IWS_32M 0x00000018 951 #define PIWAR_IWS_64M 0x00000019 952 #define PIWAR_IWS_128M 0x0000001A 953 #define PIWAR_IWS_256M 0x0000001B 954 #define PIWAR_IWS_512M 0x0000001C 955 #define PIWAR_IWS_1G 0x0000001D 956 #define PIWAR_IWS_2G 0x0000001E 957 958 #endif /* __MPC83XX_H__ */ 959